diff options
| author | Alex Deucher <alexander.deucher@amd.com> | 2021-10-04 15:19:10 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-10-04 15:23:01 -0400 |
| commit | 1d789535a03679e5ce0b56a0d32a5e44596dfcdb (patch) | |
| tree | ccc2b1827bb7efc4b939f56b49fc4bb7236d100b /drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c | |
| parent | d0761fd24ea1e57ce4e4ae7e373fef7b8a2caed8 (diff) | |
drm/amdgpu: convert IP version array to include instances
Allow us to query instances versions more cleanly.
Instancing support is not consistent unfortunately. SDMA is a
good example. Sienna cichlid has 4 total SDMA instances, each
enumerated separately (HWIDs 42, 43, 68, 69). Arcturus has 8
total SDMA instances, but they are enumerated as multiple
instances of the same HWIDs (4x HWID 42, 4x HWID 43). UMC
is another example. On most chips there are multiple
instances with the same HWID. This allows us to support both
forms.
v2: rebase
v3: clarify instancing support
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c index 88938115557b..eecfb1545c1e 100644 --- a/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c +++ b/drivers/gpu/drm/amd/amdgpu/hdp_v4_0.c @@ -49,7 +49,7 @@ static void hdp_v4_0_flush_hdp(struct amdgpu_device *adev, static void hdp_v4_0_invalidate_hdp(struct amdgpu_device *adev, struct amdgpu_ring *ring) { - if (adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 4, 0)) + if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 4, 0)) return; if (!ring || !ring->funcs->emit_wreg) @@ -79,7 +79,7 @@ static void hdp_v4_0_reset_ras_error_count(struct amdgpu_device *adev) if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__HDP)) return; - if (adev->ip_versions[HDP_HWIP] >= IP_VERSION(4, 4, 0)) + if (adev->ip_versions[HDP_HWIP][0] >= IP_VERSION(4, 4, 0)) WREG32_SOC15(HDP, 0, mmHDP_EDC_CNT, 0); else /*read back hdp ras counter to reset it to 0 */ @@ -91,10 +91,10 @@ static void hdp_v4_0_update_clock_gating(struct amdgpu_device *adev, { uint32_t def, data; - if (adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 0, 0) || - adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 0, 1) || - adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 1, 1) || - adev->ip_versions[HDP_HWIP] == IP_VERSION(4, 1, 0)) { + if (adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 0) || + adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 0, 1) || + adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 1) || + adev->ip_versions[HDP_HWIP][0] == IP_VERSION(4, 1, 0)) { def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); if (enable && (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)) @@ -136,7 +136,7 @@ static void hdp_v4_0_get_clockgating_state(struct amdgpu_device *adev, static void hdp_v4_0_init_registers(struct amdgpu_device *adev) { - switch (adev->ip_versions[HDP_HWIP]) { + switch (adev->ip_versions[HDP_HWIP][0]) { case IP_VERSION(4, 2, 1): WREG32_FIELD15(HDP, 0, HDP_MMHUB_CNTL, HDP_MMHUB_GCC, 1); break; |