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authorHawking Zhang <Hawking.Zhang@amd.com>2022-04-06 12:08:12 +0800
committerAlex Deucher <alexander.deucher@amd.com>2022-05-04 10:43:54 -0400
commit65b462fc7ef97dad2fe99b58f0172a14b8948329 (patch)
tree729489bfd48ac5976c516927cd3b7b6faaa111ce /drivers/gpu/drm/amd/amdgpu/mes_v10_1.c
parentb21348a28bffd1fd10eaa92c3fe85b5d7220b76f (diff)
drm/amdgpu: enable GENERIC0_INT for gfx/compute pipes
To generate an interrupt to RLC for accessing indirect registers that CP can not access directly Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/mes_v10_1.c')
0 files changed, 0 insertions, 0 deletions