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authorLinus Torvalds <torvalds@linux-foundation.org>2021-03-04 19:06:28 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2021-03-04 19:06:28 -0800
commit280d542f6ffac0e6d65dc267f92191d509b13b64 (patch)
tree48977edeb46f13e59871733256a7472c011086e3 /drivers/gpu/drm/amd/amdgpu/nv.c
parent44195bd7711b8a463aa4a0f93c25ce27c5e68cb5 (diff)
parenta1f1054124936c717a64e47862e3d0d820f67a87 (diff)
Merge tag 'drm-fixes-2021-03-05' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie: "More may show up but this is what I have at this stage: just a single nouveau regression fix, and a bunch of amdgpu fixes. amdgpu: - S0ix fix - Handle new NV12 SKU - Misc power fixes - Display uninitialized value fix - PCIE debugfs register access fix nouveau: - regression fix for gk104" * tag 'drm-fixes-2021-03-05' of git://anongit.freedesktop.org/drm/drm: drm/amdgpu: fix parameter error of RREG32_PCIE() in amdgpu_regs_pcie drm/amd/display: fix the return of the uninitialized value in ret drm/amdgpu: enable BACO runpm by default on sienna cichlid and navy flounder drm/amd/pm: correct Arcturus mmTHM_BACO_CNTL register address drm/amdgpu/swsmu/vangogh: Only use RLCPowerNotify msg for disable drm/amdgpu/pm: make unsupported power profile messages debug drm/amdgpu:disable VCN for Navi12 SKU drm/amdgpu: Only check for S0ix if AMD_PMC is configured drm/nouveau/fifo/gk104-gp1xx: fix creation of sw class
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/nv.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/nv.c6
1 files changed, 4 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 160fa5f59805..c625c5d8ed89 100644
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -558,7 +558,8 @@ static bool nv_is_headless_sku(struct pci_dev *pdev)
{
if ((pdev->device == 0x731E &&
(pdev->revision == 0xC6 || pdev->revision == 0xC7)) ||
- (pdev->device == 0x7340 && pdev->revision == 0xC9))
+ (pdev->device == 0x7340 && pdev->revision == 0xC9) ||
+ (pdev->device == 0x7360 && pdev->revision == 0xC7))
return true;
return false;
}
@@ -634,7 +635,8 @@ int nv_set_ip_blocks(struct amdgpu_device *adev)
if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT &&
!amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, &smu_v11_0_ip_block);
- amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
+ if (!nv_is_headless_sku(adev->pdev))
+ amdgpu_device_ip_block_add(adev, &vcn_v2_0_ip_block);
if (!amdgpu_sriov_vf(adev))
amdgpu_device_ip_block_add(adev, &jpeg_v2_0_ip_block);
break;