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authorEvan Quan <evan.quan@amd.com>2022-04-14 10:14:34 -0400
committerAlex Deucher <alexander.deucher@amd.com>2022-05-04 10:43:54 -0400
commitb21348a28bffd1fd10eaa92c3fe85b5d7220b76f (patch)
tree8c82115b6e47c2ad15e2967f557ff92477ef8130 /drivers/gpu/drm/amd/amdgpu/soc21.c
parent390db4b84aacbf3ef631b8045a7c37465b1248ea (diff)
drm/amdgpu: enable fgcg for soc21
Enable Fine Grained Clock Gating on soc21 asics. Signed-off-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/soc21.c')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/soc21.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index dc200d11fcca..d738635ecf1d 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -481,7 +481,8 @@ static int soc21_common_early_init(void *handle)
switch (adev->ip_versions[GC_HWIP][0]) {
case IP_VERSION(11, 0, 0):
adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
- AMD_CG_SUPPORT_GFX_CGLS;
+ AMD_CG_SUPPORT_GFX_CGLS |
+ AMD_CG_SUPPORT_REPEATER_FGCG;
adev->pg_flags = AMD_PG_SUPPORT_ATHUB |
AMD_PG_SUPPORT_MMHUB;
adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update