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| author | Dave Airlie <airlied@redhat.com> | 2021-07-30 16:48:35 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2021-07-30 16:48:35 +1000 |
| commit | 04d505de7f82c8f2daa6139b460b05dc01e354e0 (patch) | |
| tree | a5b4f62c721cffa1ff4f1625d76e9d8f79a9d0df /drivers/gpu/drm/amd/amdgpu/umc_v6_7.c | |
| parent | f1b7996551a40a4ebb551130c83077a0cabcb935 (diff) | |
| parent | 544dcd74b7093ad4befac99b11d90331aa73348e (diff) | |
Merge tag 'amd-drm-next-5.15-2021-07-29' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-5.15-2021-07-29:
amdgpu:
- VCN/JPEG power down sequencing fixes
- Various navi pcie link handling fixes
- Clockgating fixes
- Yellow Carp fixes
- Beige Goby fixes
- Misc code cleanups
- S0ix fixes
- SMU i2c bus rework
- EEPROM handling rework
- PSP ucode handling cleanup
- SMU error handling rework
- AMD HDMI freesync fixes
- USB PD firmware update rework
- MMIO based vram access rework
- Misc display fixes
- Backlight fixes
- Add initial Cyan Skillfish support
- Overclocking fixes suspend/resume
amdkfd:
- Sysfs leak fix
- Add counters for vm faults and migration
- GPUVM TLB optimizations
radeon:
- Misc fixes
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210730033455.3852-1-alexander.deucher@amd.com
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/umc_v6_7.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/umc_v6_7.c | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c index 3a8f787374c0..7da12110425c 100644 --- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c +++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.c @@ -28,6 +28,21 @@ #include "umc/umc_6_7_0_offset.h" #include "umc/umc_6_7_0_sh_mask.h" +const uint32_t + umc_v6_7_channel_idx_tbl_second[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM] = { + {28, 12, 6, 22}, {19, 3, 9, 25}, + {20, 4, 30, 14}, {11, 27, 1, 17}, + {24, 8, 2, 18}, {15, 31, 5, 21}, + {16, 0, 26, 10}, {7, 23, 29, 13} +}; +const uint32_t + umc_v6_7_channel_idx_tbl_first[UMC_V6_7_UMC_INSTANCE_NUM][UMC_V6_7_CHANNEL_INSTANCE_NUM] = { + {19, 3, 9, 25}, {28, 12, 6, 22}, + {11, 27, 1, 17}, {20, 4, 30, 14}, + {15, 31, 5, 21}, {24, 8, 2, 18}, + {7, 23, 29, 13}, {16, 0, 26, 10} +}; + static inline uint32_t get_umc_v6_7_reg_offset(struct amdgpu_device *adev, uint32_t umc_inst, uint32_t ch_inst) |