diff options
| author | Tao Zhou <tao.zhou1@amd.com> | 2022-01-19 17:00:09 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2022-01-27 15:49:08 -0500 |
| commit | e63fa4dcea2f7afcbf8f2d013dfae23a61a273d8 (patch) | |
| tree | 50572f86bfbb3140771c3f255b38cb5d2472257e /drivers/gpu/drm/amd/amdgpu/umc_v6_7.h | |
| parent | 498d46fe7aa7eda5807352d62af133a2f432b814 (diff) | |
drm/amdgpu: update algorithm of umc address conversion
On ALDEBARAN, we need to traverse all column bits higher than
BIT11(C4C3C2) in a row, the shift of R14 bit should be also taken
into account. Retire all pages we find.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/umc_v6_7.h')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/umc_v6_7.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h index 9adebcf98582..b67677867b45 100644 --- a/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h +++ b/drivers/gpu/drm/amd/amdgpu/umc_v6_7.h @@ -45,6 +45,10 @@ #define UMC_V6_7_NA_MAP_PA_NUM 8 /* R14 bit shift should be considered, double the number */ #define UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL (UMC_V6_7_NA_MAP_PA_NUM * 2) +/* The C2 bit in SOC physical address */ +#define UMC_V6_7_PA_C2_BIT 17 +/* The R14 bit in SOC physical address */ +#define UMC_V6_7_PA_R14_BIT 34 /* UMC regiser per channel offset */ #define UMC_V6_7_PER_CHANNEL_OFFSET 0x400 extern struct amdgpu_umc_ras umc_v6_7_ras; |