diff options
| author | Huang Rui <ray.huang@amd.com> | 2019-07-21 20:58:31 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2019-08-12 12:47:50 -0500 |
| commit | 444a0fea5107e9ad7e3cbbafed78678489e31713 (patch) | |
| tree | 346d22c85cdcda6025d42d7a3ded27daac1bbfe5 /drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | |
| parent | 8deac2363638f65d08742c571b6bc26cf8ca7ed8 (diff) | |
drm/amdgpu: use direct loading on renoir vcn for the moment
PSP has issue for renoir, that will cause VCN fw failed to be loaded. So use
direct loading for the moment till the issue is addressed.
Acked-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Aaron Liu <aaron.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c index 36ad0c0e8efb..9a076f99bc0f 100644 --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c @@ -142,7 +142,8 @@ static int vcn_v2_0_sw_init(void *handle) if (r) return r; - if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && + adev->asic_type != CHIP_RENOIR) { const struct common_firmware_header *hdr; hdr = (const struct common_firmware_header *)adev->vcn.fw->data; adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN; @@ -366,7 +367,8 @@ static void vcn_v2_0_mc_resume(struct amdgpu_device *adev) uint32_t offset; /* cache window 0: fw */ - if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && + adev->asic_type != CHIP_RENOIR) { WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW, (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo)); WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH, @@ -411,7 +413,8 @@ static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirec uint32_t offset; /* cache window 0: fw */ - if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { + if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP && + adev->asic_type != CHIP_RENOIR) { if (!indirect) { WREG32_SOC15_DPG_MODE_2_0(SOC15_DPG_MODE_OFFSET_2_0( UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), |