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authorLikun Gao <Likun.Gao@amd.com>2024-04-01 16:57:33 +0800
committerAlex Deucher <alexander.deucher@amd.com>2024-05-17 17:10:31 -0400
commitef5715846283e9ea6031d773e3c772034f4879f4 (patch)
tree51e64a4aeac4a50b972f6dfe91e5f677218ce3a2 /drivers/gpu/drm/amd/amdgpu
parent74ab6253dc077263a61bebfbdd3766b5c11e94be (diff)
drm/amdgpu: support imu for gc 12_0_0
Support IMU for ASIC with GC 12.0.0 Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu')
-rw-r--r--drivers/gpu/drm/amd/amdgpu/imu_v12_0.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c b/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c
index 032ae12b2be2..0c8ef908d112 100644
--- a/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/imu_v12_0.c
@@ -32,6 +32,7 @@
#include "gc/gc_12_0_0_sh_mask.h"
#include "mmhub/mmhub_4_1_0_offset.h"
+MODULE_FIRMWARE("amdgpu/gc_12_0_0_imu.bin");
MODULE_FIRMWARE("amdgpu/gc_12_0_1_imu.bin");
#define TRANSFER_RAM_MASK 0x001c0000
@@ -367,6 +368,7 @@ static void imu_v12_0_program_rlc_ram(struct amdgpu_device *adev)
WREG32_SOC15(GC, 0, regGFX_IMU_RLC_RAM_INDEX, 0x2);
switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
+ case IP_VERSION(12, 0, 0):
case IP_VERSION(12, 0, 1):
if (!r)
program_imu_rlc_ram(adev, data, (const u32)size);