diff options
| author | Vladimir Stempen <vladimir.stempen@amd.com> | 2021-02-24 14:02:32 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-03-02 14:07:59 -0500 |
| commit | 783bf4035cb7f2707ad760fbc06f6be01a553f0a (patch) | |
| tree | 227c008f5b0c41de8ebf935f90bc10219169f4c5 /drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | |
| parent | 640a28b50c4ad502b931750f13a5f743449e5755 (diff) | |
drm/amd/display: Fix 64 bit divisions on 32 bit platforms by using div64 API
[why]
Synchronization displays with different timings feature uses division
operator for 64 bit division, which is not supported by 32 bit platforms
[how]
Use div64 API for 64 bit division
Signed-off-by: Vladimir Stempen <vladimir.stempen@amd.com>
Tested-by: Bindu Ramamurthy<bindu.r@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c index 6f47f9bab5ee..2c7eb982eabc 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c @@ -1013,9 +1013,9 @@ static bool get_pixel_clk_frequency_100hz( * not be programmed equal to DPREFCLK */ modulo_hz = REG_READ(MODULO[inst]); - *pixel_clk_khz = ((uint64_t)clock_hz* - clock_source->ctx->dc->clk_mgr->dprefclk_khz*10)/ - modulo_hz; + *pixel_clk_khz = div_u64((uint64_t)clock_hz* + clock_source->ctx->dc->clk_mgr->dprefclk_khz*10, + modulo_hz); } else { /* NOTE: There is agreement with VBIOS here that MODULO is * programmed equal to DPREFCLK, in which case PHASE will be |