diff options
| author | Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> | 2016-12-19 15:41:49 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2017-09-26 17:06:37 -0400 |
| commit | ae799430c59edb6915e87c7c3ab972a931c796d3 (patch) | |
| tree | 9d0179249412234334fcdf67d6b0683f54871d34 /drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h | |
| parent | 540f7d8068a7278ee0604083aad3c88f0deab6ed (diff) | |
drm/amd/display: minor clock source refactor
This should make it easier to share code with newer ASICs
Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h index 067e4ac0e67a..8ee00712ef8e 100644 --- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h +++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.h @@ -41,6 +41,7 @@ #define CS_COMMON_REG_LIST_DCE_112(id) \ SRI(PIXCLK_RESYNC_CNTL, PHYPLL, id) + #define CS_SF(reg_name, field_name, post_fix)\ .field_name = reg_name ## __ ## field_name ## post_fix @@ -48,11 +49,11 @@ CS_SF(PLL_CNTL, PLL_REF_DIV_SRC, mask_sh),\ CS_SF(PIXCLK1_RESYNC_CNTL, DCCG_DEEP_COLOR_CNTL1, mask_sh),\ CS_SF(PLL_POST_DIV, PLL_POST_DIV_PIXCLK, mask_sh),\ - CS_SF(PLL_REF_DIV, PLL_REF_DIV, mask_sh),\ + CS_SF(PLL_REF_DIV, PLL_REF_DIV, mask_sh) #define CS_COMMON_MASK_SH_LIST_DCE_112(mask_sh)\ CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_DCCG_DEEP_COLOR_CNTL, mask_sh),\ - CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh),\ + CS_SF(PHYPLLA_PIXCLK_RESYNC_CNTL, PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, mask_sh) #define CS_REG_FIELD_LIST(type) \ type PLL_REF_DIV_SRC; \ @@ -61,6 +62,7 @@ type PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE; \ type PLL_POST_DIV_PIXCLK; \ type PLL_REF_DIV; \ + type DP_DTO0_ENABLE; struct dce110_clk_src_shift { CS_REG_FIELD_LIST(uint8_t) @@ -74,6 +76,9 @@ struct dce110_clk_src_regs { uint32_t RESYNC_CNTL; uint32_t PIXCLK_RESYNC_CNTL; uint32_t PLL_CNTL; + uint32_t PHASE; + uint32_t MODULO; + uint32_t PIXEL_RATE_CNTL; }; struct dce110_clk_src { |