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authorHugo Hu <hugo.hu@amd.com>2020-10-06 17:21:00 +0800
committerAlex Deucher <alexander.deucher@amd.com>2020-11-02 15:31:10 -0500
commit3a372bed1e337efa450d8288bc75cfc9237b7bad (patch)
tree7ba10106226aa2010cca196621c2a2f4d062bdad /drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
parentcae78e0331459643e21b982e4833a6525a43e498 (diff)
drm/amd/display: correct eDP T9 delay
[Why] The current end of T9 delay is relay on polling sink status by DPCD. But the polling for sink status change after NoVideoStream_flag set to 0. [How] Add function edp_add_delay_for_T9 to add T9 delay. Move the sink status polling after blank. Signed-off-by: Hugo Hu <hugo.hu@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc/link_hwss.h')
-rw-r--r--drivers/gpu/drm/amd/display/dc/inc/link_hwss.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
index 9af7ee5bc8ee..33590a728fc5 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/link_hwss.h
@@ -51,6 +51,7 @@ void dp_enable_link_phy(
const struct dc_link_settings *link_settings);
void dp_receiver_power_ctrl(struct dc_link *link, bool on);
+void edp_add_delay_for_T9(struct dc_link *link);
bool edp_receiver_ready_T9(struct dc_link *link);
bool edp_receiver_ready_T7(struct dc_link *link);