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authorHansen Dsouza <Hansen.Dsouza@amd.com>2024-10-15 17:33:15 -0400
committerAlex Deucher <alexander.deucher@amd.com>2024-10-28 16:32:29 -0400
commit69f22c5b454f7a3d77f323ed96b4ad6ac7bbe378 (patch)
treef6d638836058bf59007adccb1ec2dc04e5516dbd /drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
parent7a65e88f13b1294a41814a6b679fbc3e3fedb68b (diff)
drm/amd/display: Add a boot option to reduce phy ssc for HBR3
[Why] Spread on DPREFCLK by 0.3 percent can have a negative effect on sink when PHY SSC is also spread by 0.3 percent [How] Add boot option for DMU to lower PHY SSC Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Hansen Dsouza <Hansen.Dsouza@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h')
-rw-r--r--drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
index 6edd3d34c7b5..6d96a840d24d 100644
--- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
+++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
@@ -694,7 +694,8 @@ union dmub_fw_boot_options {
uint32_t ips_disable: 3; /* options to disable ips support*/
uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */
uint32_t disable_sldo_opt: 1; /**< 1 to disable SLDO optimizations */
- uint32_t reserved : 7; /**< reserved */
+ uint32_t lower_hbr3_phy_ssc: 1; /**< 1 to lower hbr3 phy ssc to 0.125 percent */
+ uint32_t reserved : 6; /**< reserved */
} bits; /**< boot bits */
uint32_t all; /**< 32-bit access to bits */
};