diff options
| author | Yongqiang Sun <yongqiang.sun@amd.com> | 2021-02-19 14:50:23 -0500 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2021-03-02 14:07:10 -0500 |
| commit | 70732504c53b2d3aae2cebc457515a304672d5bb (patch) | |
| tree | 4ab85b325e0118c62913a0334743757a095557a2 /drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h | |
| parent | 8039bc7130ef4206a58e4dc288621bc97eba08eb (diff) | |
drm/amd/display: Implement dmub trace event
[Why & How]
DMUB FW send trace event via outbox0 interrupt. Driver will handle it.
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h | 17 |
1 files changed, 15 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h index df85c3b86607..de5351cd5abc 100644 --- a/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h +++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_dcn20.h @@ -40,6 +40,10 @@ struct dmub_srv; DMUB_SR(DMCUB_INBOX1_SIZE) \ DMUB_SR(DMCUB_INBOX1_RPTR) \ DMUB_SR(DMCUB_INBOX1_WPTR) \ + DMUB_SR(DMCUB_OUTBOX0_BASE_ADDRESS) \ + DMUB_SR(DMCUB_OUTBOX0_SIZE) \ + DMUB_SR(DMCUB_OUTBOX0_RPTR) \ + DMUB_SR(DMCUB_OUTBOX0_WPTR) \ DMUB_SR(DMCUB_OUTBOX1_BASE_ADDRESS) \ DMUB_SR(DMCUB_OUTBOX1_SIZE) \ DMUB_SR(DMCUB_OUTBOX1_RPTR) \ @@ -102,7 +106,8 @@ struct dmub_srv; DMUB_SR(CC_DC_PIPE_DIS) \ DMUB_SR(MMHUBBUB_SOFT_RESET) \ DMUB_SR(DCN_VM_FB_LOCATION_BASE) \ - DMUB_SR(DCN_VM_FB_OFFSET) + DMUB_SR(DCN_VM_FB_OFFSET) \ + DMUB_SR(DMCUB_INTERRUPT_ACK) #define DMUB_COMMON_FIELDS() \ DMUB_SF(DMCUB_CNTL, DMCUB_ENABLE) \ @@ -135,7 +140,8 @@ struct dmub_srv; DMUB_SF(CC_DC_PIPE_DIS, DC_DMCUB_ENABLE) \ DMUB_SF(MMHUBBUB_SOFT_RESET, DMUIF_SOFT_RESET) \ DMUB_SF(DCN_VM_FB_LOCATION_BASE, FB_BASE) \ - DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET) + DMUB_SF(DCN_VM_FB_OFFSET, FB_OFFSET) \ + DMUB_SF(DMCUB_INTERRUPT_ACK, DMCUB_OUTBOX0_READY_INT_ACK) struct dmub_srv_common_reg_offset { #define DMUB_SR(reg) uint32_t reg; @@ -196,6 +202,13 @@ uint32_t dmub_dcn20_get_outbox1_wptr(struct dmub_srv *dmub); void dmub_dcn20_set_outbox1_rptr(struct dmub_srv *dmub, uint32_t rptr_offset); +void dmub_dcn20_setup_outbox0(struct dmub_srv *dmub, + const struct dmub_region *outbox0); + +uint32_t dmub_dcn20_get_outbox0_wptr(struct dmub_srv *dmub); + +void dmub_dcn20_set_outbox0_rptr(struct dmub_srv *dmub, uint32_t rptr_offset); + bool dmub_dcn20_is_hw_init(struct dmub_srv *dmub); bool dmub_dcn20_is_supported(struct dmub_srv *dmub); |