drm/amd/display: Support for DMUB AUX

[WHY]
To process AUX transactions with DMUB using inbox1 and outbox1 mail boxes.

[HOW]
1) Added inbox1 command DMUB_CMD__DP_AUX_ACCESS to issue AUX commands
   to DMUB in dc_process_dmub_aux_transfer_async(). DMUB processes AUX cmd
   with DCN and sends reply back in an outbox1 message triggering an
   outbox1 interrupt to driver.
2) In existing driver implementation, AUX commands are processed
   synchronously by configuring DCN reg. But in DMUB AUX, driver sends an
   inbox1 message and waits for a conditional variable (CV) which will be
   signaled by outbox1 ISR.
3) As the driver holds dal and dc locks while waiting for CV, the outbox1
   ISR is registered with noMutexWait set to true, which allows ISR to run
   and signal CV. This sets a constraint on ISR to not modify variables
   such as dc, dmub, etc.
4) Created dmub_outbox.c with dmub_enable_outbox_notification() to enable
   outbox1 mailbox.
5) New mailbox address ranges allocated for outbox1 of size DMUB_RB_SIZE.
   Created dmub functions for Outbox1: dmub_dcn20_setup_out_mailbox(),
   dmub_dcn20_get_outbox1_wptr() and dmub_dcn20_set_outbox1_rptr().
6) Added functions dc_stat_get_dmub_notification() and
   dmub_srv_stat_get_notification() to retrieve Outbox1 message.
7) Currently, DMUB doesn't opens DDC in AUX mode before issuing AUX
   transaction. A workaround is added in dce_aux_transfer_dmub_raw() to
   open in DDC in AUX mode for every AUX transaction.
8) Added dc debug option enable_dmub_aux_for_legacy_ddc enable/disable
   DMUB AUX. This debug option is checked dce_aux_transfer_with_retries()
   to select the method to process AUX transactions.

Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com>
Reviewed-by: Jun Lei <Jun.Lei@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

1 files changed, 27 insertions, 4 deletions

diff --git a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
index 61f64a295f06..6943bf679b42 100644
--- a/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dmub/src/dmub_srv.c
@@ -46,8 +46,8 @@
 /* Context size. */
 #define DMUB_CONTEXT_SIZE (512 * 1024)
 
-/* Mailbox size */
-#define DMUB_MAILBOX_SIZE (DMUB_RB_SIZE)
+/* Mailbox size : Ring buffers are required for both inbox and outbox */
+#define DMUB_MAILBOX_SIZE ((2 * DMUB_RB_SIZE))
 
 /* Default state size if meta is absent. */
 #define DMUB_FW_STATE_SIZE (64 * 1024)
@@ -157,6 +157,11 @@ static bool dmub_srv_hw_setup(struct dmub_srv *dmub, enum dmub_asic asic)
 		funcs->enable_dmub_boot_options = dmub_dcn20_enable_dmub_boot_options;
 		funcs->skip_dmub_panel_power_sequence = dmub_dcn20_skip_dmub_panel_power_sequence;
 
+		// Out mailbox register access functions for RN and above
+		funcs->setup_out_mailbox = dmub_dcn20_setup_out_mailbox;
+		funcs->get_outbox1_wptr = dmub_dcn20_get_outbox1_wptr;
+		funcs->set_outbox1_rptr = dmub_dcn20_set_outbox1_rptr;
+
 		if (asic == DMUB_ASIC_DCN21) {
 			dmub->regs = &dmub_srv_dcn21_regs;
 
@@ -397,7 +402,7 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
 
 	struct dmub_rb_init_params rb_params;
 	struct dmub_window cw0, cw1, cw2, cw3, cw4, cw5, cw6;
-	struct dmub_region inbox1;
+	struct dmub_region inbox1, outbox1;
 
 	if (!dmub->sw_init)
 		return DMUB_STATUS_INVALID;
@@ -444,8 +449,17 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
 		cw4.region.base = DMUB_CW4_BASE;
 		cw4.region.top = cw4.region.base + mail_fb->size;
 
+		/**
+		 * Doubled the mailbox region to accomodate inbox and outbox.
+		 * Note: Currently, currently total mailbox size is 16KB. It is split
+		 * equally into 8KB between inbox and outbox. If this config is
+		 * changed, then uncached base address configuration of outbox1
+		 * has to be updated in funcs->setup_out_mailbox.
+		 */
 		inbox1.base = cw4.region.base;
-		inbox1.top = cw4.region.top;
+		inbox1.top = cw4.region.base + DMUB_RB_SIZE;
+		outbox1.base = inbox1.top;
+		outbox1.top = cw4.region.top;
 
 		cw5.offset.quad_part = tracebuff_fb->gpu_addr;
 		cw5.region.base = DMUB_CW5_BASE;
@@ -465,6 +479,8 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
 
 		if (dmub->hw_funcs.setup_mailbox)
 			dmub->hw_funcs.setup_mailbox(dmub, &inbox1);
+		if (dmub->hw_funcs.setup_out_mailbox)
+			dmub->hw_funcs.setup_out_mailbox(dmub, &outbox1);
 	}
 
 	if (mail_fb) {
@@ -474,6 +490,13 @@ enum dmub_status dmub_srv_hw_init(struct dmub_srv *dmub,
 		rb_params.capacity = DMUB_RB_SIZE;
 
 		dmub_rb_init(&dmub->inbox1_rb, &rb_params);
+
+		// Initialize outbox1 ring buffer
+		rb_params.ctx = dmub;
+		rb_params.base_address = (void *) ((uint64_t) (mail_fb->cpu_addr) + DMUB_RB_SIZE);
+		rb_params.capacity = DMUB_RB_SIZE;
+		dmub_rb_init(&dmub->outbox1_rb, &rb_params);
+
 	}
 
 	if (dmub->hw_funcs.reset_release)