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authorRodrigo Vivi <rodrigo.vivi@intel.com>2021-05-26 09:40:54 -0400
committerRodrigo Vivi <rodrigo.vivi@intel.com>2021-05-26 09:40:54 -0400
commitabfe041de01f16d74df522d92cf5e3f6523971dd (patch)
tree1cd997085149cf09e110baa4f98725ed18ffa05a /drivers/gpu/drm/amd/display/include/dal_asic_id.h
parent7bc188cc2c8c7b21bfa0782f0d22bbf245ce1f63 (diff)
parent9a91e5e0af5e03940d0eec72c36364a1701de240 (diff)
Merge drm/drm-next into drm-intel-next
Getting in sync with -rc2 Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/amd/display/include/dal_asic_id.h')
-rw-r--r--drivers/gpu/drm/amd/display/include/dal_asic_id.h4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index 24346f1d7dd0..cb35eae29ca0 100644
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -196,6 +196,7 @@ enum {
NV_NAVI14_M_A0 = 20,
NV_SIENNA_CICHLID_P_A0 = 40,
NV_DIMGREY_CAVEFISH_P_A0 = 60,
+ NV_BEIGE_GOBY_P_A0 = 70,
NV_UNKNOWN = 0xFF
};
@@ -204,7 +205,8 @@ enum {
#define ASICREV_IS_NAVI14_M(eChipRev) ((eChipRev >= NV_NAVI14_M_A0) && (eChipRev < NV_UNKNOWN))
#define ASICREV_IS_RENOIR(eChipRev) ((eChipRev >= RENOIR_A0) && (eChipRev < RAVEN1_F0))
#define ASICREV_IS_SIENNA_CICHLID_P(eChipRev) ((eChipRev >= NV_SIENNA_CICHLID_P_A0) && (eChipRev < NV_DIMGREY_CAVEFISH_P_A0))
-#define ASICREV_IS_DIMGREY_CAVEFISH_P(eChipRev) ((eChipRev >= NV_DIMGREY_CAVEFISH_P_A0) && (eChipRev < NV_UNKNOWN))
+#define ASICREV_IS_DIMGREY_CAVEFISH_P(eChipRev) ((eChipRev >= NV_DIMGREY_CAVEFISH_P_A0) && (eChipRev < NV_BEIGE_GOBY_P_A0))
+#define ASICREV_IS_BEIGE_GOBY_P(eChipRev) ((eChipRev >= NV_BEIGE_GOBY_P_A0) && (eChipRev < NV_UNKNOWN))
#define GREEN_SARDINE_A0 0xA1
#ifndef ASICREV_IS_GREEN_SARDINE
#define ASICREV_IS_GREEN_SARDINE(eChipRev) ((eChipRev >= GREEN_SARDINE_A0) && (eChipRev < 0xFF))