diff options
| author | Dave Airlie <airlied@redhat.com> | 2023-06-15 14:11:22 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2023-06-15 14:11:22 +1000 |
| commit | 901bdf5ea1a836400ee69aa32b04e9c209271ec7 (patch) | |
| tree | ccb1851c8a71e776dbccf1ccae132dc9b5f093c6 /drivers/gpu/drm/amd/include/asic_reg/mmhub | |
| parent | ba57b9b11f78530146f02b776854b2b6b6d344a4 (diff) | |
| parent | 3b718dcaf163d17fe907ea098c8449e0cd6bc271 (diff) | |
Merge tag 'amd-drm-next-6.5-2023-06-09' of https://gitlab.freedesktop.org/agd5f/linux into drm-next
amd-drm-next-6.5-2023-06-02:
amdgpu:
- SR-IOV fixes
- Warning fixes
- Misc code cleanups and spelling fixes
- DCN 3.2 updates
- Improved DC FAMS support for better power management
- Improved DC SubVP support for better power management
- DCN 3.1.x fixes
- Max IB size query
- DC GPU reset fixes
- RAS updates
- DCN 3.0.x fixes
- S/G display fixes
- CP shadow buffer support
- Implement connector force callback
- Z8 power improvements
- PSP 13.0.10 vbflash support
- Mode2 reset fixes
- Store MQDs in VRAM to improve queue switch latency
- VCN 3.x fixes
- JPEG 3.x fixes
- Enable DC_FP on LoongArch
- GFXOFF fixes
- GC 9.4.3 partition support
- SDMA 4.4.2 partition support
- VCN/JPEG 4.0.3 partition support
- VCN 4.0.3 updates
- NBIO 7.9 updates
- GC 9.4.3 updates
- Take NUMA into account when allocating memory
- Handle NUMA for partitions
- SMU 13.0.6 updates
- GC 9.4.3 RAS updates
- Stop including unused swiotlb.h
- SMU 13.0.7 fixes
- Fix clock output ordering on some APUs
- Clean up DC FPGA code
- GFX9 preemption fixes
- Misc irq fixes
- S0ix fixes
- Add new DRM_AMDGPU_WERROR config parameter to help with CI
- PCIe fix for RDNA2
- kdoc fixes
- Documentation updates
amdkfd:
- Query TTM mem limit rather than hardcoding it
- GC 9.4.3 partition support
- Handle NUMA for partitions
radeon:
- Fix possible double free
- Stop including unused swiotlb.h
- Fix possible division by zero
ttm:
- Add query for TTM mem limit
- Add NUMA awareness to pools
- Export ttm_pool_fini()
UAPI:
- Add new ctx query flag to better handle GPU resets
Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22290
- Add new interface to query and set shadow buffer for RDNA3
Mesa MR: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21986
- Add new INFO query for max IB size
Proposed userspace: https://gitlab.freedesktop.org/bnieuwenhuizen/mesa/-/commits/ib-rejection-v3
amd-drm-next-6.5-2023-06-09:
amdgpu:
- S0ix fixes
- Initial SMU13 Overdrive support
- kdoc fixes
- Misc clode cleanups
- Flexible array fixes
- Display OTG fixes
- SMU 13.0.6 updates
- Revert some broken clock counter updates
- Misc display fixes
- GFX9 preemption fixes
- Add support for newer EEPROM bad page table format
- Add missing radeon secondary id
- Add support for new colorspace KMS API
- CSA fix
- Stable pstate fixes for APUs
- make vbl interface admin only
- Handle PCI accelerator class
amdkfd:
- Add debugger support for gdb
radeon:
- Fix possible UAF
drm:
- Add Colorspace functionality
UAPI:
- Add debugger interface for enabling gdb
Proposed userspace: https://github.com/ROCm-Developer-Tools/ROCdbgapi/tree/wip-dbgapi
- Add KMS colorspace API
Discussion: https://lists.freedesktop.org/archives/dri-devel/2023-June/408128.html
From: Alex Deucher <alexander.deucher@amd.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230609174817.7764-1-alexander.deucher@amd.com
Diffstat (limited to 'drivers/gpu/drm/amd/include/asic_reg/mmhub')
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_8_0_offset.h | 56 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_8_0_sh_mask.h | 325 |
2 files changed, 373 insertions, 8 deletions
diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_8_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_8_0_offset.h index 8bcc81f2dfc0..879ee9de3ff3 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_8_0_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_8_0_offset.h @@ -1491,6 +1491,10 @@ #define regMMEA0_PERFCOUNTER1_CFG_BASE_IDX 0 #define regMMEA0_PERFCOUNTER_RSLT_CNTL 0x0400 #define regMMEA0_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regMMEA0_UE_ERR_STATUS_LO 0x0406 +#define regMMEA0_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regMMEA0_UE_ERR_STATUS_HI 0x0407 +#define regMMEA0_UE_ERR_STATUS_HI_BASE_IDX 0 #define regMMEA0_DSM_CNTL 0x0408 #define regMMEA0_DSM_CNTL_BASE_IDX 0 #define regMMEA0_DSM_CNTLA 0x0409 @@ -1511,8 +1515,12 @@ #define regMMEA0_ERR_STATUS_BASE_IDX 0 #define regMMEA0_MISC2 0x0412 #define regMMEA0_MISC2_BASE_IDX 0 +#define regMMEA0_CE_ERR_STATUS_LO 0x0414 +#define regMMEA0_CE_ERR_STATUS_LO_BASE_IDX 0 #define regMMEA0_MISC_AON 0x0415 #define regMMEA0_MISC_AON_BASE_IDX 0 +#define regMMEA0_CE_ERR_STATUS_HI 0x0416 +#define regMMEA0_CE_ERR_STATUS_HI_BASE_IDX 0 // addressBlock: aid_mmhub_ea_mmeadec1 @@ -1709,6 +1717,10 @@ #define regMMEA1_PERFCOUNTER1_CFG_BASE_IDX 0 #define regMMEA1_PERFCOUNTER_RSLT_CNTL 0x0540 #define regMMEA1_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regMMEA1_UE_ERR_STATUS_LO 0x0546 +#define regMMEA1_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regMMEA1_UE_ERR_STATUS_HI 0x0547 +#define regMMEA1_UE_ERR_STATUS_HI_BASE_IDX 0 #define regMMEA1_DSM_CNTL 0x0548 #define regMMEA1_DSM_CNTL_BASE_IDX 0 #define regMMEA1_DSM_CNTLA 0x0549 @@ -1729,8 +1741,12 @@ #define regMMEA1_ERR_STATUS_BASE_IDX 0 #define regMMEA1_MISC2 0x0552 #define regMMEA1_MISC2_BASE_IDX 0 +#define regMMEA1_CE_ERR_STATUS_LO 0x0554 +#define regMMEA1_CE_ERR_STATUS_LO_BASE_IDX 0 #define regMMEA1_MISC_AON 0x0555 #define regMMEA1_MISC_AON_BASE_IDX 0 +#define regMMEA1_CE_ERR_STATUS_HI 0x0556 +#define regMMEA1_CE_ERR_STATUS_HI_BASE_IDX 0 // addressBlock: aid_mmhub_ea_mmeadec2 @@ -1927,6 +1943,10 @@ #define regMMEA2_PERFCOUNTER1_CFG_BASE_IDX 0 #define regMMEA2_PERFCOUNTER_RSLT_CNTL 0x0680 #define regMMEA2_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regMMEA2_UE_ERR_STATUS_LO 0x0686 +#define regMMEA2_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regMMEA2_UE_ERR_STATUS_HI 0x0687 +#define regMMEA2_UE_ERR_STATUS_HI_BASE_IDX 0 #define regMMEA2_DSM_CNTL 0x0688 #define regMMEA2_DSM_CNTL_BASE_IDX 0 #define regMMEA2_DSM_CNTLA 0x0689 @@ -1947,8 +1967,12 @@ #define regMMEA2_ERR_STATUS_BASE_IDX 0 #define regMMEA2_MISC2 0x0692 #define regMMEA2_MISC2_BASE_IDX 0 +#define regMMEA2_CE_ERR_STATUS_LO 0x0694 +#define regMMEA2_CE_ERR_STATUS_LO_BASE_IDX 0 #define regMMEA2_MISC_AON 0x0695 #define regMMEA2_MISC_AON_BASE_IDX 0 +#define regMMEA2_CE_ERR_STATUS_HI 0x0696 +#define regMMEA2_CE_ERR_STATUS_HI_BASE_IDX 0 // addressBlock: aid_mmhub_ea_mmeadec3 @@ -2145,6 +2169,10 @@ #define regMMEA3_PERFCOUNTER1_CFG_BASE_IDX 0 #define regMMEA3_PERFCOUNTER_RSLT_CNTL 0x07c0 #define regMMEA3_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regMMEA3_UE_ERR_STATUS_LO 0x07c6 +#define regMMEA3_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regMMEA3_UE_ERR_STATUS_HI 0x07c7 +#define regMMEA3_UE_ERR_STATUS_HI_BASE_IDX 0 #define regMMEA3_DSM_CNTL 0x07c8 #define regMMEA3_DSM_CNTL_BASE_IDX 0 #define regMMEA3_DSM_CNTLA 0x07c9 @@ -2165,9 +2193,12 @@ #define regMMEA3_ERR_STATUS_BASE_IDX 0 #define regMMEA3_MISC2 0x07d2 #define regMMEA3_MISC2_BASE_IDX 0 +#define regMMEA3_CE_ERR_STATUS_LO 0x07d4 +#define regMMEA3_CE_ERR_STATUS_LO_BASE_IDX 0 #define regMMEA3_MISC_AON 0x07d5 #define regMMEA3_MISC_AON_BASE_IDX 0 - +#define regMMEA3_CE_ERR_STATUS_HI 0x07d6 +#define regMMEA3_CE_ERR_STATUS_HI_BASE_IDX 0 // addressBlock: aid_mmhub_ea_mmeadec4 // base address: 0x62000 @@ -2363,6 +2394,10 @@ #define regMMEA4_PERFCOUNTER1_CFG_BASE_IDX 0 #define regMMEA4_PERFCOUNTER_RSLT_CNTL 0x0900 #define regMMEA4_PERFCOUNTER_RSLT_CNTL_BASE_IDX 0 +#define regMMEA4_UE_ERR_STATUS_LO 0x0906 +#define regMMEA4_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regMMEA4_UE_ERR_STATUS_HI 0x0907 +#define regMMEA4_UE_ERR_STATUS_HI_BASE_IDX 0 #define regMMEA4_DSM_CNTL 0x0908 #define regMMEA4_DSM_CNTL_BASE_IDX 0 #define regMMEA4_DSM_CNTLA 0x0909 @@ -2383,9 +2418,12 @@ #define regMMEA4_ERR_STATUS_BASE_IDX 0 #define regMMEA4_MISC2 0x0912 #define regMMEA4_MISC2_BASE_IDX 0 +#define regMMEA4_CE_ERR_STATUS_LO 0x0914 +#define regMMEA4_CE_ERR_STATUS_LO_BASE_IDX 0 #define regMMEA4_MISC_AON 0x0915 #define regMMEA4_MISC_AON_BASE_IDX 0 - +#define regMMEA4_CE_ERR_STATUS_HI 0x0916 +#define regMMEA4_CE_ERR_STATUS_HI_BASE_IDX 0 // addressBlock: aid_mmhub_pctldec0 // base address: 0x62a00 @@ -3310,5 +3348,19 @@ #define regL2TLB_PERFCOUNTER_HI 0x0d2d #define regL2TLB_PERFCOUNTER_HI_BASE_IDX 0 +// addressBlock: aid_mmhub_mm_cane_mmcanedec +// base address: 0x635f0 +#define regMM_CANE_ICG_CTRL 0x0d8a +#define regMM_CANE_ICG_CTRL_BASE_IDX 0 +#define regMM_CANE_ERR_STATUS 0x0d8c +#define regMM_CANE_ERR_STATUS_BASE_IDX 0 +#define regMM_CANE_UE_ERR_STATUS_LO 0x0d8d +#define regMM_CANE_UE_ERR_STATUS_LO_BASE_IDX 0 +#define regMM_CANE_UE_ERR_STATUS_HI 0x0d8e +#define regMM_CANE_UE_ERR_STATUS_HI_BASE_IDX 0 +#define regMM_CANE_CE_ERR_STATUS_LO 0x0d8f +#define regMM_CANE_CE_ERR_STATUS_LO_BASE_IDX 0 +#define regMM_CANE_CE_ERR_STATUS_HI 0x0d90 +#define regMM_CANE_CE_ERR_STATUS_HI_BASE_IDX 0 #endif diff --git a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_8_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_8_0_sh_mask.h index af41468ce69f..088c1f02aa43 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_8_0_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/mmhub/mmhub_1_8_0_sh_mask.h @@ -10470,6 +10470,30 @@ #define MMEA0_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L #define MMEA0_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L #define MMEA0_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//MMEA0_UE_ERR_STATUS_LO +#define MMEA0_UE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT 0x0 +#define MMEA0_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define MMEA0_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define MMEA0_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define MMEA0_UE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK 0x00000001L +#define MMEA0_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define MMEA0_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define MMEA0_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//MMEA0_UE_ERR_STATUS_HI +#define MMEA0_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define MMEA0_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define MMEA0_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define MMEA0_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define MMEA0_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define MMEA0_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define MMEA0_UE_ERR_STATUS_HI__RESERVED_FIELD__SHIFT 0x1d +#define MMEA0_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define MMEA0_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define MMEA0_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define MMEA0_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define MMEA0_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define MMEA0_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define MMEA0_UE_ERR_STATUS_HI__RESERVED_FIELD_MASK 0xE0000000L //MMEA0_DSM_CNTL #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 #define MMEA0_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 @@ -10718,12 +10742,35 @@ #define MMEA0_MISC2__DRAM_WR_THROTTLE_MASK 0x00020000L #define MMEA0_MISC2__GMI_RD_THROTTLE_MASK 0x00040000L #define MMEA0_MISC2__GMI_WR_THROTTLE_MASK 0x00080000L +//MMEA0_CE_ERR_STATUS_LO +#define MMEA0_CE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT 0x0 +#define MMEA0_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define MMEA0_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define MMEA0_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define MMEA0_CE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK 0x00000001L +#define MMEA0_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define MMEA0_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define MMEA0_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L //MMEA0_MISC_AON #define MMEA0_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 #define MMEA0_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 #define MMEA0_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L #define MMEA0_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L - +//MMEA0_CE_ERR_STATUS_HI +#define MMEA0_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define MMEA0_CE_ERR_STATUS_HI__RESERVED_FIELD0__SHIFT 0x1 +#define MMEA0_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define MMEA0_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define MMEA0_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define MMEA0_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define MMEA0_CE_ERR_STATUS_HI__RESERVED_FIELD1__SHIFT 0x1b +#define MMEA0_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define MMEA0_CE_ERR_STATUS_HI__RESERVED_FIELD0_MASK 0x00000002L +#define MMEA0_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define MMEA0_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define MMEA0_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define MMEA0_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define MMEA0_CE_ERR_STATUS_HI__RESERVED_FIELD1_MASK 0xF8000000L // addressBlock: aid_mmhub_ea_mmeadec1 //MMEA1_DRAM_RD_CLI2GRP_MAP0 @@ -12418,6 +12465,30 @@ #define MMEA1_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L #define MMEA1_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L #define MMEA1_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//MMEA1_UE_ERR_STATUS_LO +#define MMEA1_UE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT 0x0 +#define MMEA1_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define MMEA1_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define MMEA1_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define MMEA1_UE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK 0x00000001L +#define MMEA1_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define MMEA1_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define MMEA1_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//MMEA1_UE_ERR_STATUS_HI +#define MMEA1_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define MMEA1_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define MMEA1_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define MMEA1_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define MMEA1_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define MMEA1_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define MMEA1_UE_ERR_STATUS_HI__RESERVED_FIELD__SHIFT 0x1d +#define MMEA1_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define MMEA1_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define MMEA1_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define MMEA1_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define MMEA1_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define MMEA1_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define MMEA1_UE_ERR_STATUS_HI__RESERVED_FIELD_MASK 0xE0000000L //MMEA1_DSM_CNTL #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 #define MMEA1_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 @@ -12666,12 +12737,35 @@ #define MMEA1_MISC2__DRAM_WR_THROTTLE_MASK 0x00020000L #define MMEA1_MISC2__GMI_RD_THROTTLE_MASK 0x00040000L #define MMEA1_MISC2__GMI_WR_THROTTLE_MASK 0x00080000L +//MMEA1_CE_ERR_STATUS_LO +#define MMEA1_CE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT 0x0 +#define MMEA1_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define MMEA1_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define MMEA1_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define MMEA1_CE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK 0x00000001L +#define MMEA1_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define MMEA1_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define MMEA1_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L //MMEA1_MISC_AON #define MMEA1_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 #define MMEA1_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 #define MMEA1_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L #define MMEA1_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L - +//MMEA1_CE_ERR_STATUS_HI +#define MMEA1_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define MMEA1_CE_ERR_STATUS_HI__RESERVED_FIELD0__SHIFT 0x1 +#define MMEA1_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define MMEA1_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define MMEA1_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define MMEA1_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define MMEA1_CE_ERR_STATUS_HI__RESERVED_FIELD1__SHIFT 0x1b +#define MMEA1_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define MMEA1_CE_ERR_STATUS_HI__RESERVED_FIELD0_MASK 0x00000002L +#define MMEA1_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define MMEA1_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define MMEA1_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define MMEA1_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define MMEA1_CE_ERR_STATUS_HI__RESERVED_FIELD1_MASK 0xF8000000L // addressBlock: aid_mmhub_ea_mmeadec2 //MMEA2_DRAM_RD_CLI2GRP_MAP0 @@ -14366,6 +14460,30 @@ #define MMEA2_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L #define MMEA2_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L #define MMEA2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//MMEA2_UE_ERR_STATUS_LO +#define MMEA2_UE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT 0x0 +#define MMEA2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define MMEA2_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define MMEA2_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define MMEA2_UE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK 0x00000001L +#define MMEA2_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define MMEA2_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define MMEA2_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//MMEA2_UE_ERR_STATUS_HI +#define MMEA2_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define MMEA2_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define MMEA2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define MMEA2_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define MMEA2_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define MMEA2_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define MMEA2_UE_ERR_STATUS_HI__RESERVED_FIELD__SHIFT 0x1d +#define MMEA2_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define MMEA2_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define MMEA2_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define MMEA2_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define MMEA2_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define MMEA2_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define MMEA2_UE_ERR_STATUS_HI__RESERVED_FIELD_MASK 0xE0000000L //MMEA2_DSM_CNTL #define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 #define MMEA2_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 @@ -14614,12 +14732,35 @@ #define MMEA2_MISC2__DRAM_WR_THROTTLE_MASK 0x00020000L #define MMEA2_MISC2__GMI_RD_THROTTLE_MASK 0x00040000L #define MMEA2_MISC2__GMI_WR_THROTTLE_MASK 0x00080000L +//MMEA2_CE_ERR_STATUS_LO +#define MMEA2_CE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT 0x0 +#define MMEA2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define MMEA2_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define MMEA2_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define MMEA2_CE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK 0x00000001L +#define MMEA2_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define MMEA2_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define MMEA2_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L //MMEA2_MISC_AON #define MMEA2_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 #define MMEA2_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 #define MMEA2_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L #define MMEA2_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L - +//MMEA2_CE_ERR_STATUS_HI +#define MMEA2_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define MMEA2_CE_ERR_STATUS_HI__RESERVED_FIELD0__SHIFT 0x1 +#define MMEA2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define MMEA2_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define MMEA2_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define MMEA2_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define MMEA2_CE_ERR_STATUS_HI__RESERVED_FIELD1__SHIFT 0x1b +#define MMEA2_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define MMEA2_CE_ERR_STATUS_HI__RESERVED_FIELD0_MASK 0x00000002L +#define MMEA2_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define MMEA2_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define MMEA2_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define MMEA2_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define MMEA2_CE_ERR_STATUS_HI__RESERVED_FIELD1_MASK 0xF8000000L // addressBlock: aid_mmhub_ea_mmeadec3 //MMEA3_DRAM_RD_CLI2GRP_MAP0 @@ -16314,6 +16455,30 @@ #define MMEA3_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L #define MMEA3_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L #define MMEA3_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//MMEA3_UE_ERR_STATUS_LO +#define MMEA3_UE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT 0x0 +#define MMEA3_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define MMEA3_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define MMEA3_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define MMEA3_UE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK 0x00000001L +#define MMEA3_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define MMEA3_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define MMEA3_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//MMEA3_UE_ERR_STATUS_HI +#define MMEA3_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define MMEA3_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define MMEA3_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define MMEA3_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define MMEA3_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define MMEA3_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define MMEA3_UE_ERR_STATUS_HI__RESERVED_FIELD__SHIFT 0x1d +#define MMEA3_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define MMEA3_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define MMEA3_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define MMEA3_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define MMEA3_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define MMEA3_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define MMEA3_UE_ERR_STATUS_HI__RESERVED_FIELD_MASK 0xE0000000L //MMEA3_DSM_CNTL #define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 #define MMEA3_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 @@ -16562,12 +16727,35 @@ #define MMEA3_MISC2__DRAM_WR_THROTTLE_MASK 0x00020000L #define MMEA3_MISC2__GMI_RD_THROTTLE_MASK 0x00040000L #define MMEA3_MISC2__GMI_WR_THROTTLE_MASK 0x00080000L +//MMEA3_CE_ERR_STATUS_LO +#define MMEA3_CE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT 0x0 +#define MMEA3_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define MMEA3_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define MMEA3_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define MMEA3_CE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK 0x00000001L +#define MMEA3_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define MMEA3_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define MMEA3_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L //MMEA3_MISC_AON #define MMEA3_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 #define MMEA3_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 #define MMEA3_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L #define MMEA3_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L - +//MMEA3_CE_ERR_STATUS_HI +#define MMEA3_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define MMEA3_CE_ERR_STATUS_HI__RESERVED_FIELD0__SHIFT 0x1 +#define MMEA3_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define MMEA3_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define MMEA3_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define MMEA3_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define MMEA3_CE_ERR_STATUS_HI__RESERVED_FIELD1__SHIFT 0x1b +#define MMEA3_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define MMEA3_CE_ERR_STATUS_HI__RESERVED_FIELD0_MASK 0x00000002L +#define MMEA3_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define MMEA3_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define MMEA3_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define MMEA3_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define MMEA3_CE_ERR_STATUS_HI__RESERVED_FIELD1_MASK 0xF8000000L // addressBlock: aid_mmhub_ea_mmeadec4 //MMEA4_DRAM_RD_CLI2GRP_MAP0 @@ -18262,6 +18450,30 @@ #define MMEA4_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK 0x01000000L #define MMEA4_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK 0x02000000L #define MMEA4_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK 0x04000000L +//MMEA4_UE_ERR_STATUS_LO +#define MMEA4_UE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT 0x0 +#define MMEA4_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define MMEA4_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define MMEA4_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define MMEA4_UE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK 0x00000001L +#define MMEA4_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define MMEA4_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define MMEA4_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//MMEA4_UE_ERR_STATUS_HI +#define MMEA4_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define MMEA4_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define MMEA4_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define MMEA4_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define MMEA4_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define MMEA4_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define MMEA4_UE_ERR_STATUS_HI__RESERVED_FIELD__SHIFT 0x1d +#define MMEA4_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define MMEA4_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define MMEA4_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define MMEA4_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define MMEA4_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define MMEA4_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +#define MMEA4_UE_ERR_STATUS_HI__RESERVED_FIELD_MASK 0xE0000000L //MMEA4_DSM_CNTL #define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_DSM_IRRITATOR_DATA__SHIFT 0x0 #define MMEA4_DSM_CNTL__DRAMRD_CMDMEM_ENABLE_SINGLE_WRITE__SHIFT 0x2 @@ -18510,12 +18722,35 @@ #define MMEA4_MISC2__DRAM_WR_THROTTLE_MASK 0x00020000L #define MMEA4_MISC2__GMI_RD_THROTTLE_MASK 0x00040000L #define MMEA4_MISC2__GMI_WR_THROTTLE_MASK 0x00080000L +//MMEA4_CE_ERR_STATUS_LO +#define MMEA4_CE_ERR_STATUS_LO__STATUS_VALID_FLAG__SHIFT 0x0 +#define MMEA4_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define MMEA4_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define MMEA4_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define MMEA4_CE_ERR_STATUS_LO__STATUS_VALID_FLAG_MASK 0x00000001L +#define MMEA4_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define MMEA4_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define MMEA4_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L //MMEA4_MISC_AON #define MMEA4_MISC_AON__LINKMGR_PARTACK_HYSTERESIS__SHIFT 0x0 #define MMEA4_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE__SHIFT 0x2 #define MMEA4_MISC_AON__LINKMGR_PARTACK_HYSTERESIS_MASK 0x00000003L #define MMEA4_MISC_AON__LINKMGR_PARTACK_DEASSERT_MODE_MASK 0x00000004L - +//MMEA4_CE_ERR_STATUS_HI +#define MMEA4_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define MMEA4_CE_ERR_STATUS_HI__RESERVED_FIELD0__SHIFT 0x1 +#define MMEA4_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define MMEA4_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define MMEA4_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define MMEA4_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define MMEA4_CE_ERR_STATUS_HI__RESERVED_FIELD1__SHIFT 0x1b +#define MMEA4_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define MMEA4_CE_ERR_STATUS_HI__RESERVED_FIELD0_MASK 0x00000002L +#define MMEA4_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define MMEA4_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define MMEA4_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define MMEA4_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L +#define MMEA4_CE_ERR_STATUS_HI__RESERVED_FIELD1_MASK 0xF8000000L // addressBlock: aid_mmhub_pctldec0 //PCTL0_CTRL @@ -22311,5 +22546,83 @@ #define L2TLB_PERFCOUNTER_HI__COUNTER_HI_MASK 0x0000FFFFL #define L2TLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK 0xFFFF0000L - +// addressBlock: aid_mmhub_mm_cane_mmcanedec +//MM_CANE_ICG_CTRL +#define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_IREQ0__SHIFT 0x0 +#define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_ATRET__SHIFT 0x1 +#define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_OREQ__SHIFT 0x2 +#define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_REGISTER__SHIFT 0x3 +#define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_SDPM_RETURN__SHIFT 0x4 +#define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_IREQ0_MASK 0x00000001L +#define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_ATRET_MASK 0x00000002L +#define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_OREQ_MASK 0x00000004L +#define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_REGISTER_MASK 0x00000008L +#define MM_CANE_ICG_CTRL__SOFT_OVERRIDE_SDPM_RETURN_MASK 0x00000010L +//MM_CANE_ERR_STATUS +#define MM_CANE_ERR_STATUS__SDPM_RDRSP_STATUS__SHIFT 0x0 +#define MM_CANE_ERR_STATUS__SDPM_WRRSP_STATUS__SHIFT 0x4 +#define MM_CANE_ERR_STATUS__SDPM_RDRSP_DATASTATUS__SHIFT 0x8 +#define MM_CANE_ERR_STATUS__SDPM_RDRSP_DATAPARITY_ERROR__SHIFT 0xa +#define MM_CANE_ERR_STATUS__SDPS_DAT_ERROR__SHIFT 0xb +#define MM_CANE_ERR_STATUS__SDPS_DAT_PARITY_ERROR__SHIFT 0xc +#define MM_CANE_ERR_STATUS__CLEAR_ERROR_STATUS__SHIFT 0xd +#define MM_CANE_ERR_STATUS__BUSY_ON_ERROR__SHIFT 0xe +#define MM_CANE_ERR_STATUS__BUSY_ON_UER_ERROR__SHIFT 0xf +#define MM_CANE_ERR_STATUS__FUE_FLAG__SHIFT 0x10 +#define MM_CANE_ERR_STATUS__INTERRUPT_ON_FATAL__SHIFT 0x11 +#define MM_CANE_ERR_STATUS__LEVEL_INTERRUPT__SHIFT 0x12 +#define MM_CANE_ERR_STATUS__SDPM_RDRSP_STATUS_MASK 0x0000000FL +#define MM_CANE_ERR_STATUS__SDPM_WRRSP_STATUS_MASK 0x000000F0L +#define MM_CANE_ERR_STATUS__SDPM_RDRSP_DATASTATUS_MASK 0x00000300L +#define MM_CANE_ERR_STATUS__SDPM_RDRSP_DATAPARITY_ERROR_MASK 0x00000400L +#define MM_CANE_ERR_STATUS__SDPS_DAT_ERROR_MASK 0x00000800L +#define MM_CANE_ERR_STATUS__SDPS_DAT_PARITY_ERROR_MASK 0x00001000L +#define MM_CANE_ERR_STATUS__CLEAR_ERROR_STATUS_MASK 0x00002000L +#define MM_CANE_ERR_STATUS__BUSY_ON_ERROR_MASK 0x00004000L +#define MM_CANE_ERR_STATUS__BUSY_ON_UER_ERROR_MASK 0x00008000L +#define MM_CANE_ERR_STATUS__FUE_FLAG_MASK 0x00010000L +#define MM_CANE_ERR_STATUS__INTERRUPT_ON_FATAL_MASK 0x00020000L +#define MM_CANE_ERR_STATUS__LEVEL_INTERRUPT_MASK 0x00040000L +//MM_CANE_UE_ERR_STATUS_LO +#define MM_CANE_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define MM_CANE_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define MM_CANE_UE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define MM_CANE_UE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define MM_CANE_UE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define MM_CANE_UE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define MM_CANE_UE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define MM_CANE_UE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//MM_CANE_UE_ERR_STATUS_HI +#define MM_CANE_UE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define MM_CANE_UE_ERR_STATUS_HI__PARITY__SHIFT 0x1 +#define MM_CANE_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define MM_CANE_UE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define MM_CANE_UE_ERR_STATUS_HI__UE_CNT__SHIFT 0x17 +#define MM_CANE_UE_ERR_STATUS_HI__FED_CNT__SHIFT 0x1a +#define MM_CANE_UE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define MM_CANE_UE_ERR_STATUS_HI__PARITY_MASK 0x00000002L +#define MM_CANE_UE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define MM_CANE_UE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define MM_CANE_UE_ERR_STATUS_HI__UE_CNT_MASK 0x03800000L +#define MM_CANE_UE_ERR_STATUS_HI__FED_CNT_MASK 0x1C000000L +//MM_CANE_CE_ERR_STATUS_LO +#define MM_CANE_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG__SHIFT 0x0 +#define MM_CANE_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG__SHIFT 0x1 +#define MM_CANE_CE_ERR_STATUS_LO__ADDRESS__SHIFT 0x2 +#define MM_CANE_CE_ERR_STATUS_LO__MEMORY_ID__SHIFT 0x18 +#define MM_CANE_CE_ERR_STATUS_LO__ERR_STATUS_VALID_FLAG_MASK 0x00000001L +#define MM_CANE_CE_ERR_STATUS_LO__ADDRESS_VALID_FLAG_MASK 0x00000002L +#define MM_CANE_CE_ERR_STATUS_LO__ADDRESS_MASK 0x00FFFFFCL +#define MM_CANE_CE_ERR_STATUS_LO__MEMORY_ID_MASK 0xFF000000L +//MM_CANE_CE_ERR_STATUS_HI +#define MM_CANE_CE_ERR_STATUS_HI__ECC__SHIFT 0x0 +#define MM_CANE_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG__SHIFT 0x2 +#define MM_CANE_CE_ERR_STATUS_HI__ERR_INFO__SHIFT 0x3 +#define MM_CANE_CE_ERR_STATUS_HI__CE_CNT__SHIFT 0x17 +#define MM_CANE_CE_ERR_STATUS_HI__POISON__SHIFT 0x1a +#define MM_CANE_CE_ERR_STATUS_HI__ECC_MASK 0x00000001L +#define MM_CANE_CE_ERR_STATUS_HI__ERR_INFO_VALID_FLAG_MASK 0x00000004L +#define MM_CANE_CE_ERR_STATUS_HI__ERR_INFO_MASK 0x007FFFF8L +#define MM_CANE_CE_ERR_STATUS_HI__CE_CNT_MASK 0x03800000L +#define MM_CANE_CE_ERR_STATUS_HI__POISON_MASK 0x04000000L #endif |