diff options
| author | Kenneth Feng <kenneth.feng@amd.com> | 2024-05-11 15:35:23 +0800 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2024-05-17 17:40:38 -0400 |
| commit | 512b322b9a16c2465b9926b98ab067421e5669f9 (patch) | |
| tree | a70899300bce8d27d740caea1189093fba0bf2fb /drivers/gpu/drm/amd/pm/swsmu/smu14 | |
| parent | d3620eeae82cccf8316e6754f8ddb52473e2e5ea (diff) | |
drm/amd/pm: support pp_dpm_pcie on smu v14.0.2/3
support pp_dpm_pcie on smu v14.0.2/3
Signed-off-by: Kenneth Feng <kenneth.feng@amd.com>
Reviewed-by: Jack Gui <Jack.Gui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/amd/pm/swsmu/smu14')
| -rw-r--r-- | drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c | 32 |
2 files changed, 33 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c index fe6834f1648b..fbfe9cae0e05 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0.c @@ -46,6 +46,8 @@ #define regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0 0x0342 #define regMP1_SMN_IH_SW_INT_CTRL_mp1_14_0_0_BASE_IDX 0 +const int decoded_link_speed[5] = {1, 2, 3, 4, 5}; +const int decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16}; /* * DO NOT use these for err/warn/info/debug messages. * Use dev_err, dev_warn, dev_info and dev_dbg instead. diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c index b594b748de47..1fbceb85d319 100644 --- a/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c +++ b/drivers/gpu/drm/amd/pm/swsmu/smu14/smu_v14_0_2_ppt.c @@ -1036,6 +1036,8 @@ static int smu_v14_0_2_print_clk_levels(struct smu_context *smu, struct smu_dpm_context *smu_dpm = &smu->smu_dpm; struct smu_14_0_dpm_context *dpm_context = smu_dpm->dpm_context; struct smu_14_0_dpm_table *single_dpm_table; + struct smu_14_0_pcie_table *pcie_table; + uint32_t gen_speed, lane_width; int i, curr_freq, size = 0; int ret = 0; @@ -1126,7 +1128,35 @@ static int smu_v14_0_2_print_clk_levels(struct smu_context *smu, } break; case SMU_PCIE: - // TODO + ret = smu_v14_0_2_get_smu_metrics_data(smu, + METRICS_PCIE_RATE, + &gen_speed); + if (ret) + return ret; + + ret = smu_v14_0_2_get_smu_metrics_data(smu, + METRICS_PCIE_WIDTH, + &lane_width); + if (ret) + return ret; + + pcie_table = &(dpm_context->dpm_tables.pcie_table); + for (i = 0; i < pcie_table->num_of_link_levels; i++) + size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i, + (pcie_table->pcie_gen[i] == 0) ? "2.5GT/s," : + (pcie_table->pcie_gen[i] == 1) ? "5.0GT/s," : + (pcie_table->pcie_gen[i] == 2) ? "8.0GT/s," : + (pcie_table->pcie_gen[i] == 3) ? "16.0GT/s," : "", + (pcie_table->pcie_lane[i] == 1) ? "x1" : + (pcie_table->pcie_lane[i] == 2) ? "x2" : + (pcie_table->pcie_lane[i] == 3) ? "x4" : + (pcie_table->pcie_lane[i] == 4) ? "x8" : + (pcie_table->pcie_lane[i] == 5) ? "x12" : + (pcie_table->pcie_lane[i] == 6) ? "x16" : "", + pcie_table->clk_freq[i], + (gen_speed == DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) && + (lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ? + "*" : ""); break; default: |