diff options
| author | Joel Stanley <joel@jms.id.au> | 2021-02-09 23:07:34 +1030 |
|---|---|---|
| committer | Joel Stanley <joel@jms.id.au> | 2021-02-10 10:56:16 +1030 |
| commit | bce724fa58e67d24fe9eddb40ebb665fbe4bd7e8 (patch) | |
| tree | a30fd17e9e83b1b33ddc09532b9b64d1de259a49 /drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c | |
| parent | 92614ad540171382d856e178cd2073377f2d1a7c (diff) | |
drm/aspeed: Use dt matching for default register values
There are minor differences in the values for the threshold value and
the scan line size between families of ASPEED SoC. Additionally the SCU
registers for the output control and scratch registers differ between
families.
This adds device tree matching to parameterise these values, allowing us
to add support for the AST2400 now, and in the future the AST2600.
Reviewed-by: Jeremy Kerr <jk@ozlabs.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://patchwork.freedesktop.org/patch/msgid/20210209123734.130483-3-joel@jms.id.au
Diffstat (limited to 'drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c')
| -rw-r--r-- | drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c index e54686c31a90..20c2197b270f 100644 --- a/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c +++ b/drivers/gpu/drm/aspeed/aspeed_gfx_crtc.c @@ -59,8 +59,8 @@ static void aspeed_gfx_enable_controller(struct aspeed_gfx *priv) u32 ctrl1 = readl(priv->base + CRT_CTRL1); u32 ctrl2 = readl(priv->base + CRT_CTRL2); - /* SCU2C: set DAC source for display output to Graphics CRT (GFX) */ - regmap_update_bits(priv->scu, 0x2c, BIT(16), BIT(16)); + /* Set DAC source for display output to Graphics CRT (GFX) */ + regmap_update_bits(priv->scu, priv->dac_reg, BIT(16), BIT(16)); writel(ctrl1 | CRT_CTRL_EN, priv->base + CRT_CTRL1); writel(ctrl2 | CRT_CTRL_DAC_EN, priv->base + CRT_CTRL2); @@ -74,7 +74,7 @@ static void aspeed_gfx_disable_controller(struct aspeed_gfx *priv) writel(ctrl1 & ~CRT_CTRL_EN, priv->base + CRT_CTRL1); writel(ctrl2 & ~CRT_CTRL_DAC_EN, priv->base + CRT_CTRL2); - regmap_update_bits(priv->scu, 0x2c, BIT(16), 0); + regmap_update_bits(priv->scu, priv->dac_reg, BIT(16), 0); } static void aspeed_gfx_crtc_mode_set_nofb(struct aspeed_gfx *priv) @@ -127,7 +127,8 @@ static void aspeed_gfx_crtc_mode_set_nofb(struct aspeed_gfx *priv) * Terminal Count: memory size of one scan line */ d_offset = m->hdisplay * bpp / 8; - t_count = (m->hdisplay * bpp + 127) / 128; + t_count = DIV_ROUND_UP(m->hdisplay * bpp, priv->scan_line_max); + writel(CRT_DISP_OFFSET(d_offset) | CRT_TERM_COUNT(t_count), priv->base + CRT_OFFSET); @@ -135,7 +136,7 @@ static void aspeed_gfx_crtc_mode_set_nofb(struct aspeed_gfx *priv) * Threshold: FIFO thresholds of refill and stop (16 byte chunks * per line, rounded up) */ - writel(G5_CRT_THROD_VAL, priv->base + CRT_THROD); + writel(priv->throd_val, priv->base + CRT_THROD); } static void aspeed_gfx_pipe_enable(struct drm_simple_display_pipe *pipe, |