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| author | Alexandre Courbot <acourbot@nvidia.com> | 2017-01-26 16:49:43 +0900 |
|---|---|---|
| committer | Ben Skeggs <bskeggs@redhat.com> | 2017-03-07 17:05:13 +1000 |
| commit | cfd044b02873b02236bcd93ff398504d489ddc13 (patch) | |
| tree | b32d65654f367799b149ad755e954fe259465aa4 /drivers/gpu/drm/drm_scatter.c | |
| parent | ad147b7f57547a5597ed338f2c46f03809d7792e (diff) | |
drm/nouveau/falcon: fix base address of FBIF registers
All falcons have their FBIF registers starting at offset 0x600, with the
exception of the PMU and NVENC engines.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/drm_scatter.c')
0 files changed, 0 insertions, 0 deletions