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| author | James Zhu <James.Zhu@amd.com> | 2018-09-10 16:00:36 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2018-09-26 21:09:24 -0500 |
| commit | 03d6e3aac81634a91dd2790f8c199ffb3927fe3c (patch) | |
| tree | 1c6e343575897cebfc58612cff171b91092c12de /drivers/gpu/drm/i2c | |
| parent | f28ff06210f444da0b52168450625ad883ff8a1f (diff) | |
drm/amdgpu:Add DPG mode read/write macro
Some registers read/write needs program through SDRAM pool under
DPG mode.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'drivers/gpu/drm/i2c')
0 files changed, 0 insertions, 0 deletions