diff options
| author | Matt Roper <matthew.d.roper@intel.com> | 2021-03-19 21:42:42 -0700 |
|---|---|---|
| committer | Matt Roper <matthew.d.roper@intel.com> | 2021-03-23 16:41:11 -0700 |
| commit | 005e95377249cb65133bf698926d0ab7876dddc3 (patch) | |
| tree | 27fe5658270ed29d805a52e9a47d54f5f8b30f13 /drivers/gpu/drm/i915/display/intel_dpll.c | |
| parent | 01eb15c9165e4169c8637703b025371586d27fbb (diff) | |
drm/i915/display: Eliminate most usage of INTEL_GEN()
Use Coccinelle to convert most of the usage of INTEL_GEN() and IS_GEN()
in the display code to use DISPLAY_VER() comparisons instead. The
following semantic patch was used:
@@ expression dev_priv, E; @@
- INTEL_GEN(dev_priv) == E
+ IS_DISPLAY_VER(dev_priv, E)
@@ expression dev_priv; @@
- INTEL_GEN(dev_priv)
+ DISPLAY_VER(dev_priv)
@@ expression dev_priv; expression E; @@
- IS_GEN(dev_priv, E)
+ IS_DISPLAY_VER(dev_priv, E)
@@
expression dev_priv;
expression from, until;
@@
- IS_GEN_RANGE(dev_priv, from, until)
+ IS_DISPLAY_RANGE(dev_priv, from, until)
There are still some display-related uses of INTEL_GEN() in intel_pm.c
(watermark code) and i915_irq.c. Those will be updated separately.
v2:
- Use new IS_DISPLAY_RANGE and IS_DISPLAY_VER helpers. (Jani)
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210320044245.3920043-4-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dpll.c')
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_dpll.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_dpll.c b/drivers/gpu/drm/i915/display/intel_dpll.c index 166e9a3a8c09..3e3c5eed1600 100644 --- a/drivers/gpu/drm/i915/display/intel_dpll.c +++ b/drivers/gpu/drm/i915/display/intel_dpll.c @@ -847,7 +847,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc, dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; break; } - if (INTEL_GEN(dev_priv) >= 4) + if (DISPLAY_VER(dev_priv) >= 4) dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); if (crtc_state->sdvo_tv_clock) @@ -861,7 +861,7 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc, dpll |= DPLL_VCO_ENABLE; crtc_state->dpll_hw_state.dpll = dpll; - if (INTEL_GEN(dev_priv) >= 4) { + if (DISPLAY_VER(dev_priv) >= 4) { u32 dpll_md = (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; crtc_state->dpll_hw_state.dpll_md = dpll_md; @@ -926,7 +926,7 @@ static int hsw_crtc_compute_clock(struct intel_crtc *crtc, to_intel_atomic_state(crtc_state->uapi.state); if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) || - INTEL_GEN(dev_priv) >= 11) { + DISPLAY_VER(dev_priv) >= 11) { struct intel_encoder *encoder = intel_get_crtc_new_encoder(state, crtc_state); @@ -1346,7 +1346,7 @@ static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, void intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv) { - if (INTEL_GEN(dev_priv) >= 9 || HAS_DDI(dev_priv)) + if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv)) dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock; else if (HAS_PCH_SPLIT(dev_priv)) dev_priv->display.crtc_compute_clock = ilk_crtc_compute_clock; @@ -1358,7 +1358,7 @@ intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv) dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; else if (IS_PINEVIEW(dev_priv)) dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; - else if (!IS_GEN(dev_priv, 2)) + else if (!IS_DISPLAY_VER(dev_priv, 2)) dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; else dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; @@ -1398,7 +1398,7 @@ void i9xx_enable_pll(struct intel_crtc *crtc, intel_de_posting_read(dev_priv, reg); udelay(150); - if (INTEL_GEN(dev_priv) >= 4) { + if (DISPLAY_VER(dev_priv) >= 4) { intel_de_write(dev_priv, DPLL_MD(crtc->pipe), crtc_state->dpll_hw_state.dpll_md); } else { |