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| author | Uma Shankar <uma.shankar@intel.com> | 2020-12-02 00:34:05 +0530 |
|---|---|---|
| committer | Uma Shankar <uma.shankar@intel.com> | 2020-12-02 19:08:33 +0530 |
| commit | 91bd7a441bf03f87fca72517541aa6e79909a624 (patch) | |
| tree | 34350c7106326c5a5c467b24ac733a0d599abe1e /drivers/gpu/drm/i915/display/intel_dvo.c | |
| parent | ca3fb8821fbc016c8baa3acbe6e8bf9cab684061 (diff) | |
drm/i915/display/tgl: Disable FBC with PSR2
There are some corner cases wrt underrun when we enable
FBC with PSR2 on TGL. Recommendation from hardware is to
keep this combination disabled.
Bspec: 50422 HSD: 14010260002
v2: Added psr2 enabled check from crtc_state (Anshuman)
Added Bspec link and HSD referneces (Jose)
v3: Moved the logic to disable fbc to intel_fbc_update_state_cache
and removed the crtc->config usages, as per Ville's recommendation.
v4: Introduced a variable in fbc state_cache instead of the earlier
plane.visible WA, as suggested by Jose.
v5: Dropped an extra check for fbc in intel_fbc_enable and addressed
review comments by Jose.
v6: Move WA to end of function and added Jose's RB.
Signed-off-by: Uma Shankar <uma.shankar@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201201190406.1752-2-uma.shankar@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/display/intel_dvo.c')
0 files changed, 0 insertions, 0 deletions