diff options
| author | Dave Airlie <airlied@redhat.com> | 2021-02-19 13:54:29 +1000 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2021-02-19 13:55:07 +1000 |
| commit | f730f39eb981af249d57336b47cfe3925632a7fd (patch) | |
| tree | 65e6d8e41d0d378382567096a90b1a4f4ab9c093 /drivers/gpu/drm/i915/gt/gen7_renderclear.c | |
| parent | 4f8ad4045b385dee8e9c0a4e7ca2042d6114d8e7 (diff) | |
| parent | 81ce8f04aa96f7f6cae05770f68b5d15be91f5a2 (diff) | |
Merge tag 'drm-intel-next-fixes-2021-02-18' of git://anongit.freedesktop.org/drm/drm-intel into drm-next
- Restrict DRM_I915_DEBUG to developer builds (Chris)
- Fix return and error codes (Dan)
- Suspend/Resume fix (Chris)
- Disable atomics in L3 for gen9 (Chris)
- Flush before changing register state (Chris)
- Fix for GLK's HDMI (Ville)
- Fix ILK+'s plane strides with Xtiling (Ville)
- Correct surface base address for renderclear (Chris)
Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/YC7uQY1kt6w0tRp+@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915/gt/gen7_renderclear.c')
| -rw-r--r-- | drivers/gpu/drm/i915/gt/gen7_renderclear.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/gt/gen7_renderclear.c b/drivers/gpu/drm/i915/gt/gen7_renderclear.c index 8551e6de50e8..de575fdb033f 100644 --- a/drivers/gpu/drm/i915/gt/gen7_renderclear.c +++ b/drivers/gpu/drm/i915/gt/gen7_renderclear.c @@ -240,7 +240,7 @@ gen7_emit_state_base_address(struct batch_chunk *batch, /* general */ *cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY; /* surface */ - *cs++ = batch_addr(batch) | surface_state_base | BASE_ADDRESS_MODIFY; + *cs++ = (batch_addr(batch) + surface_state_base) | BASE_ADDRESS_MODIFY; /* dynamic */ *cs++ = batch_addr(batch) | BASE_ADDRESS_MODIFY; /* indirect */ @@ -393,6 +393,7 @@ static void emit_batch(struct i915_vma * const vma, desc_count); /* Reset inherited context registers */ + gen7_emit_pipeline_flush(&cmds); gen7_emit_pipeline_invalidate(&cmds); batch_add(&cmds, MI_LOAD_REGISTER_IMM(2)); batch_add(&cmds, i915_mmio_reg_offset(CACHE_MODE_0_GEN7)); |