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authorMark Brown <broonie@kernel.org>2020-09-17 18:25:39 +0100
committerMark Brown <broonie@kernel.org>2020-09-17 18:25:39 +0100
commit0199f866615921ddc5d22fbbab7510e8b403d40c (patch)
treec8eb5b58efd4b22ef136f29ca9f62564ec57c1b2 /drivers/gpu/drm/i915/i915_cmd_parser.c
parent2b37a18b58ed12b711591ec54c2b2a0e2068cf6e (diff)
parentb014e9fae7e7de4329a7092ade4256982c5ce974 (diff)
Merge series "Support ROHM BD9576MUF and BD9573MUF PMICs" from Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>:
Initial support for ROHM BD9576MUF and BD9573MUF PMICs. These PMICs are primarily intended to be used to power the R-Car family processors. BD9576MUF includes some additional safety features the BD9573MUF does not have. This initial version of drivers does not utilize these features and for now the SW behaviour is identical. Please note that this version of drivers is only tested on BD9576MUF but according to the data-sheets the relevant parts of registers should be same so drivers should also work on BD9573MUF. This patch series includes MFD, watchdog and regulator drivers with basic functionality such as: - Enabling and pinging the watchdog - configuring watchog timeout / window from device-tree - reading regulator states/voltages - enabling/disabling VOUT1 (VD50) when control mode B is used. This patch series does not bring interrupt support. BD9576MUF and BD9573MUF are designed to keep the IRQ line low for whole duration of error condition. IRQ can't be 'acked'. So proper IRQ support would require some IRQ limiter implementation (delayed unmask?) in order to not hog the CPU. --- Matti Vaittinen (6): dt_bindings: mfd: Add ROHM BD9576MUF and BD9573MUF PMICs dt_bindings: regulator: Add ROHM BD9576MUF and BD9573MUF PMICs mfd: Support ROHM BD9576MUF and BD9573MUF wdt: Support wdt on ROHM BD9576MUF and BD9573MUF regulator: Support ROHM BD9576MUF and BD9573MUF MAINTAINERS: Add ROHM BD9576MUF and BD9573MUF drivers .../bindings/mfd/rohm,bd9576-pmic.yaml | 129 +++++++ .../regulator/rohm,bd9576-regulator.yaml | 33 ++ MAINTAINERS | 4 + drivers/mfd/Kconfig | 11 + drivers/mfd/Makefile | 1 + drivers/mfd/rohm-bd9576.c | 130 +++++++ drivers/regulator/Kconfig | 10 + drivers/regulator/Makefile | 1 + drivers/regulator/bd9576-regulator.c | 337 ++++++++++++++++++ drivers/watchdog/Kconfig | 13 + drivers/watchdog/Makefile | 1 + drivers/watchdog/bd9576_wdt.c | 295 +++++++++++++++ include/linux/mfd/rohm-bd957x.h | 61 ++++ include/linux/mfd/rohm-generic.h | 2 + 14 files changed, 1028 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/rohm,bd9576-pmic.yaml create mode 100644 Documentation/devicetree/bindings/regulator/rohm,bd9576-regulator.yaml create mode 100644 drivers/mfd/rohm-bd9576.c create mode 100644 drivers/regulator/bd9576-regulator.c create mode 100644 drivers/watchdog/bd9576_wdt.c create mode 100644 include/linux/mfd/rohm-bd957x.h base-commit: f4d51dffc6c01a9e94650d95ce0104964f8ae822 -- 2.21.0 -- Matti Vaittinen, Linux device drivers ROHM Semiconductors, Finland SWDC Kiviharjunlenkki 1E 90220 OULU FINLAND ~~~ "I don't think so," said Rene Descartes. Just then he vanished ~~~ Simon says - in Latin please. ~~~ "non cogito me" dixit Rene Descarte, deinde evanescavit ~~~ Thanks to Simon Glass for the translation =]
Diffstat (limited to 'drivers/gpu/drm/i915/i915_cmd_parser.c')
-rw-r--r--drivers/gpu/drm/i915/i915_cmd_parser.c14
1 files changed, 10 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 372354d33f55..5ac4a999f05a 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -1204,6 +1204,12 @@ static u32 *copy_batch(struct drm_i915_gem_object *dst_obj,
return dst;
}
+static inline bool cmd_desc_is(const struct drm_i915_cmd_descriptor * const desc,
+ const u32 cmd)
+{
+ return desc->cmd.value == (cmd & desc->cmd.mask);
+}
+
static bool check_cmd(const struct intel_engine_cs *engine,
const struct drm_i915_cmd_descriptor *desc,
const u32 *cmd, u32 length)
@@ -1242,19 +1248,19 @@ static bool check_cmd(const struct intel_engine_cs *engine,
* allowed mask/value pair given in the whitelist entry.
*/
if (reg->mask) {
- if (desc->cmd.value == MI_LOAD_REGISTER_MEM) {
+ if (cmd_desc_is(desc, MI_LOAD_REGISTER_MEM)) {
DRM_DEBUG("CMD: Rejected LRM to masked register 0x%08X\n",
reg_addr);
return false;
}
- if (desc->cmd.value == MI_LOAD_REGISTER_REG) {
+ if (cmd_desc_is(desc, MI_LOAD_REGISTER_REG)) {
DRM_DEBUG("CMD: Rejected LRR to masked register 0x%08X\n",
reg_addr);
return false;
}
- if (desc->cmd.value == MI_LOAD_REGISTER_IMM(1) &&
+ if (cmd_desc_is(desc, MI_LOAD_REGISTER_IMM(1)) &&
(offset + 2 > length ||
(cmd[offset + 1] & reg->mask) != reg->value)) {
DRM_DEBUG("CMD: Rejected LRI to masked register 0x%08X\n",
@@ -1478,7 +1484,7 @@ int intel_engine_cmd_parser(struct intel_engine_cs *engine,
break;
}
- if (desc->cmd.value == MI_BATCH_BUFFER_START) {
+ if (cmd_desc_is(desc, MI_BATCH_BUFFER_START)) {
ret = check_bbstart(cmd, offset, length, batch_length,
batch_addr, shadow_addr,
jump_whitelist);