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| author | Michel Thierry <michel.thierry@intel.com> | 2017-08-18 10:23:42 -0700 |
|---|---|---|
| committer | Chris Wilson <chris@chris-wilson.co.uk> | 2017-08-22 12:27:18 +0100 |
| commit | 41e61020e821487489526e50b8e2e223342b7b93 (patch) | |
| tree | b096c6a0e27a68c869053d7e1378a55d45a5d956 /drivers/gpu/drm/i915/intel_dp_mst.c | |
| parent | 1853a9daa19e150c32d0082e4f006391a7c6a997 (diff) | |
drm/i915: Re-enable per-engine reset for Broxton
The corruption in CSB mmio reads we were seeing has been tracked down to
incorrectly touching forcewake of all domains, following an engine reset.
It is still a mistery why we only catched this in Broxton, since it
could happen in any platform.
With that fix already merged, commit 4055dc75d6b5 ("drm/i915: Stop
touching forcewake following a gen6+ engine reset"), lets try to enable
per-engine resets in Broxton one more time.
This reverts commit f188258bde0f ("drm/i915: Disable per-engine reset for
Broxton").
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170818172342.7282-1-michel.thierry@intel.com
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_dp_mst.c')
0 files changed, 0 insertions, 0 deletions