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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-03-21 21:50:04 +0200 |
|---|---|---|
| committer | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2022-04-20 16:56:11 +0300 |
| commit | d90502d2ef99366d7d7c2bd9503165ec5baf590c (patch) | |
| tree | 17923a596cd533c1d8a12ab9b83313ff5feb79d2 /drivers/gpu/drm/i915/intel_pm.c | |
| parent | b962a068347533e72ddb60ace6d649a5b974485b (diff) | |
drm/i915: Program i830 DPLL FP register later
Follow the new i9xx DPLL FP register programming sequence
introduced in commit 62d66b218386 ("drm/i915: Fold
i9xx_set_pll_dividers() into i9xx_enable_pll()") in the
i830 "power well" code as well. Just for consistency.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220321195006.775-2-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_pm.c')
0 files changed, 0 insertions, 0 deletions