diff options
| author | Sonika Jindal <sonika.jindal@intel.com> | 2015-05-26 17:50:13 +0530 |
|---|---|---|
| committer | Jani Nikula <jani.nikula@intel.com> | 2015-06-03 10:51:01 +0300 |
| commit | 64987fc59d90738715703362292f743b7dbbe76b (patch) | |
| tree | 20cc4bf1d75487b0477901f1e8662da1de644255 /drivers/gpu/drm/i915/intel_ringbuffer.c | |
| parent | 5b6fd12a88a7233b58c669dc87979da9a69728b1 (diff) | |
drm/i915/bxt: edp1.4 Intermediate Freq support
BXT supports following intermediate link rates for edp:
2.16GHz, 2.43GHz, 3.24GHz, 4.32GHz.
Adding support for programming the intermediate rates.
v2: Adding clock in bxt_clk_div struct and then look for the entry with
required rate (Ville)
v3: 'clock' has the selected value, no need to use link_bw or rate_select
for selecting pll(Ville)
v4: Make bxt_dp_clk_val const and remove size (Ville)
v5: Rebased
v6: Removed setting of vco while rebasing in v5, adding it back
Signed-off-by: Sonika Jindal <sonika.jindal@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v4)
Reviewed-by: Vandana Kannan <vandana.kannan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Diffstat (limited to 'drivers/gpu/drm/i915/intel_ringbuffer.c')
0 files changed, 0 insertions, 0 deletions