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authorMatt Roper <matthew.d.roper@intel.com>2022-03-01 15:15:38 -0800
committerMatt Roper <matthew.d.roper@intel.com>2022-03-02 06:45:17 -0800
commit4b88ad503d6d2ea11891a355e656bf428ec815e6 (patch)
tree8d728d073d91cdefb04576b9beac76b4524eaf69 /drivers/gpu/drm/i915
parent944823c9463916dd53f365e9aa07f23360968080 (diff)
drm/i915/xehp: CCS shares the render reset domain
The reset domain is shared between render and all compute engines, so resetting one will affect the others. Note: Before performing a reset on an RCS or CCS engine, the GuC will attempt to preempt-to-idle the other non-hung RCS/CCS engines to avoid impacting other clients (since some shared modules will be reset). If other engines are executing non-preemptable workloads, the impact is unavoidable and some work may be lost. Bspec: 52549 Original-author: Michel Thierry Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> Cc: Vinay Belgaumkar <vinay.belgaumkar@intel.com> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com> Signed-off-by: Matt Roper <matthew.d.roper@intel.com> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20220301231549.1817978-3-matthew.d.roper@intel.com
Diffstat (limited to 'drivers/gpu/drm/i915')
-rw-r--r--drivers/gpu/drm/i915/gt/intel_engine_cs.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 3190b7b462a9..3150c0847f65 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -341,6 +341,10 @@ static u32 get_reset_domain(u8 ver, enum intel_engine_id id)
[VECS1] = GEN11_GRDOM_VECS2,
[VECS2] = GEN11_GRDOM_VECS3,
[VECS3] = GEN11_GRDOM_VECS4,
+ [CCS0] = GEN11_GRDOM_RENDER,
+ [CCS1] = GEN11_GRDOM_RENDER,
+ [CCS2] = GEN11_GRDOM_RENDER,
+ [CCS3] = GEN11_GRDOM_RENDER,
};
GEM_BUG_ON(id >= ARRAY_SIZE(engine_reset_domains) ||
!engine_reset_domains[id]);