Merge tag 'drm-msm-next-2021-06-23b' of https://gitlab.freedesktop.org/drm/msm into drm-next

* devcoredump support for display errors
* dpu: irq cleanup/refactor
* dpu: dt bindings conversion to yaml
* dsi: dt bindings conversion to yaml
* mdp5: alpha/blend_mode/zpos support
* a6xx: cached coherent buffer support
* a660 support
* gpu iova fault improvements:
   - info about which block triggered the fault, etc
   - generation of gpu devcoredump on fault
* assortment of other cleanups and fixes

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Rob Clark <robdclark@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/CAF6AEGs4=qsGBBbyn-4JWqW4-YUSTKh67X3DsPQ=T2D9aXKqNA@mail.gmail.com

1 files changed, 38 insertions, 94 deletions

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
index 5d6f9a7a5195..ac83c1159815 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
@@ -12,85 +12,32 @@
 #include "dpu_hw_util.h"
 #include "dpu_hw_mdss.h"
 
-/**
- * dpu_intr_type - HW Interrupt Type
- * @DPU_IRQ_TYPE_WB_ROT_COMP:		WB rotator done
- * @DPU_IRQ_TYPE_WB_WFD_COMP:		WB WFD done
- * @DPU_IRQ_TYPE_PING_PONG_COMP:	PingPong done
- * @DPU_IRQ_TYPE_PING_PONG_RD_PTR:	PingPong read pointer
- * @DPU_IRQ_TYPE_PING_PONG_WR_PTR:	PingPong write pointer
- * @DPU_IRQ_TYPE_PING_PONG_AUTO_REF:	PingPong auto refresh
- * @DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK:	PingPong Tear check
- * @DPU_IRQ_TYPE_PING_PONG_TE_CHECK:	PingPong TE detection
- * @DPU_IRQ_TYPE_INTF_UNDER_RUN:	INTF underrun
- * @DPU_IRQ_TYPE_INTF_VSYNC:		INTF VSYNC
- * @DPU_IRQ_TYPE_CWB_OVERFLOW:		Concurrent WB overflow
- * @DPU_IRQ_TYPE_HIST_VIG_DONE:		VIG Histogram done
- * @DPU_IRQ_TYPE_HIST_VIG_RSTSEQ:	VIG Histogram reset
- * @DPU_IRQ_TYPE_HIST_DSPP_DONE:	DSPP Histogram done
- * @DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ:	DSPP Histogram reset
- * @DPU_IRQ_TYPE_WD_TIMER:		Watchdog timer
- * @DPU_IRQ_TYPE_SFI_VIDEO_IN:		Video static frame INTR into static
- * @DPU_IRQ_TYPE_SFI_VIDEO_OUT:		Video static frame INTR out-of static
- * @DPU_IRQ_TYPE_SFI_CMD_0_IN:		DSI CMD0 static frame INTR into static
- * @DPU_IRQ_TYPE_SFI_CMD_0_OUT:		DSI CMD0 static frame INTR out-of static
- * @DPU_IRQ_TYPE_SFI_CMD_1_IN:		DSI CMD1 static frame INTR into static
- * @DPU_IRQ_TYPE_SFI_CMD_1_OUT:		DSI CMD1 static frame INTR out-of static
- * @DPU_IRQ_TYPE_SFI_CMD_2_IN:		DSI CMD2 static frame INTR into static
- * @DPU_IRQ_TYPE_SFI_CMD_2_OUT:		DSI CMD2 static frame INTR out-of static
- * @DPU_IRQ_TYPE_PROG_LINE:		Programmable Line interrupt
- * @DPU_IRQ_TYPE_AD4_BL_DONE:		AD4 backlight
- * @DPU_IRQ_TYPE_CTL_START:		Control start
- * @DPU_IRQ_TYPE_RESERVED:		Reserved for expansion
- */
-enum dpu_intr_type {
-	DPU_IRQ_TYPE_WB_ROT_COMP,
-	DPU_IRQ_TYPE_WB_WFD_COMP,
-	DPU_IRQ_TYPE_PING_PONG_COMP,
-	DPU_IRQ_TYPE_PING_PONG_RD_PTR,
-	DPU_IRQ_TYPE_PING_PONG_WR_PTR,
-	DPU_IRQ_TYPE_PING_PONG_AUTO_REF,
-	DPU_IRQ_TYPE_PING_PONG_TEAR_CHECK,
-	DPU_IRQ_TYPE_PING_PONG_TE_CHECK,
-	DPU_IRQ_TYPE_INTF_UNDER_RUN,
-	DPU_IRQ_TYPE_INTF_VSYNC,
-	DPU_IRQ_TYPE_CWB_OVERFLOW,
-	DPU_IRQ_TYPE_HIST_VIG_DONE,
-	DPU_IRQ_TYPE_HIST_VIG_RSTSEQ,
-	DPU_IRQ_TYPE_HIST_DSPP_DONE,
-	DPU_IRQ_TYPE_HIST_DSPP_RSTSEQ,
-	DPU_IRQ_TYPE_WD_TIMER,
-	DPU_IRQ_TYPE_SFI_VIDEO_IN,
-	DPU_IRQ_TYPE_SFI_VIDEO_OUT,
-	DPU_IRQ_TYPE_SFI_CMD_0_IN,
-	DPU_IRQ_TYPE_SFI_CMD_0_OUT,
-	DPU_IRQ_TYPE_SFI_CMD_1_IN,
-	DPU_IRQ_TYPE_SFI_CMD_1_OUT,
-	DPU_IRQ_TYPE_SFI_CMD_2_IN,
-	DPU_IRQ_TYPE_SFI_CMD_2_OUT,
-	DPU_IRQ_TYPE_PROG_LINE,
-	DPU_IRQ_TYPE_AD4_BL_DONE,
-	DPU_IRQ_TYPE_CTL_START,
-	DPU_IRQ_TYPE_RESERVED,
+/* When making changes be sure to sync with dpu_intr_set */
+enum dpu_hw_intr_reg {
+	MDP_SSPP_TOP0_INTR,
+	MDP_SSPP_TOP0_INTR2,
+	MDP_SSPP_TOP0_HIST_INTR,
+	MDP_INTF0_INTR,
+	MDP_INTF1_INTR,
+	MDP_INTF2_INTR,
+	MDP_INTF3_INTR,
+	MDP_INTF4_INTR,
+	MDP_AD4_0_INTR,
+	MDP_AD4_1_INTR,
+	MDP_INTF0_7xxx_INTR,
+	MDP_INTF1_7xxx_INTR,
+	MDP_INTF5_7xxx_INTR,
+	MDP_INTR_MAX,
 };
 
+#define DPU_IRQ_IDX(reg_idx, offset)	(reg_idx * 32 + offset)
+
 struct dpu_hw_intr;
 
 /**
  * Interrupt operations.
  */
 struct dpu_hw_intr_ops {
-	/**
-	 * irq_idx_lookup - Lookup IRQ index on the HW interrupt type
-	 *                 Used for all irq related ops
-	 * @intr:		HW interrupt handle
-	 * @intr_type:		Interrupt type defined in dpu_intr_type
-	 * @instance_idx:	HW interrupt block instance
-	 * @return:		irq_idx or -EINVAL for lookup fail
-	 */
-	int (*irq_idx_lookup)(struct dpu_hw_intr *intr,
-			enum dpu_intr_type intr_type,
-			u32 instance_idx);
 
 	/**
 	 * enable_irq - Enable IRQ based on lookup IRQ index
@@ -98,7 +45,7 @@ struct dpu_hw_intr_ops {
 	 * @irq_idx:	Lookup irq index return from irq_idx_lookup
 	 * @return:	0 for success, otherwise failure
 	 */
-	int (*enable_irq)(
+	int (*enable_irq_locked)(
 			struct dpu_hw_intr *intr,
 			int irq_idx);
 
@@ -108,7 +55,7 @@ struct dpu_hw_intr_ops {
 	 * @irq_idx:	Lookup irq index return from irq_idx_lookup
 	 * @return:	0 for success, otherwise failure
 	 */
-	int (*disable_irq)(
+	int (*disable_irq_locked)(
 			struct dpu_hw_intr *intr,
 			int irq_idx);
 
@@ -143,23 +90,6 @@ struct dpu_hw_intr_ops {
 			void *arg);
 
 	/**
-	 * get_interrupt_statuses - Gets and store value from all interrupt
-	 *                          status registers that are currently fired.
-	 * @intr:	HW interrupt handle
-	 */
-	void (*get_interrupt_statuses)(
-			struct dpu_hw_intr *intr);
-
-	/**
-	 * clear_intr_status_nolock() - clears the HW interrupts without lock
-	 * @intr:	HW interrupt handle
-	 * @irq_idx:	Lookup irq index return from irq_idx_lookup
-	 */
-	void (*clear_intr_status_nolock)(
-			struct dpu_hw_intr *intr,
-			int irq_idx);
-
-	/**
 	 * get_interrupt_status - Gets HW interrupt status, and clear if set,
 	 *                        based on given lookup IRQ index.
 	 * @intr:	HW interrupt handle
@@ -170,6 +100,22 @@ struct dpu_hw_intr_ops {
 			struct dpu_hw_intr *intr,
 			int irq_idx,
 			bool clear);
+
+	/**
+	 * lock - take the IRQ lock
+	 * @intr:	HW interrupt handle
+	 * @return:	irq_flags for the taken spinlock
+	 */
+	unsigned long (*lock)(
+			struct dpu_hw_intr *intr);
+
+	/**
+	 * unlock - take the IRQ lock
+	 * @intr:	HW interrupt handle
+	 * @irq_flags:  the irq_flags returned from lock
+	 */
+	void (*unlock)(
+			struct dpu_hw_intr *intr, unsigned long irq_flags);
 };
 
 /**
@@ -178,19 +124,17 @@ struct dpu_hw_intr_ops {
  * @ops:              function pointer mapping for IRQ handling
  * @cache_irq_mask:   array of IRQ enable masks reg storage created during init
  * @save_irq_status:  array of IRQ status reg storage created during init
- * @irq_idx_tbl_size: total number of irq_idx mapped in the hw_interrupts
+ * @total_irqs: total number of irq_idx mapped in the hw_interrupts
  * @irq_lock:         spinlock for accessing IRQ resources
- * @obsolete_irq:      irq types that are obsolete for a particular target
  */
 struct dpu_hw_intr {
 	struct dpu_hw_blk_reg_map hw;
 	struct dpu_hw_intr_ops ops;
 	u32 *cache_irq_mask;
 	u32 *save_irq_status;
-	u32 irq_idx_tbl_size;
+	u32 total_irqs;
 	spinlock_t irq_lock;
 	unsigned long irq_mask;
-	unsigned long obsolete_irq;
 };
 
 /**