diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2024-03-13 18:34:05 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2024-03-13 18:34:05 -0700 |
| commit | 480e035fc4c714fb5536e64ab9db04fedc89e910 (patch) | |
| tree | 01341ee43abe7ecb8efb4e7bbbb1c3b3b50f7ec8 /drivers/gpu/drm/msm | |
| parent | e5e038b7ae9da96b93974bf072ca1876899a01a3 (diff) | |
| parent | 119b225f01e4d3ce974cd3b4d982c76a380c796d (diff) | |
Merge tag 'drm-next-2024-03-13' of https://gitlab.freedesktop.org/drm/kernel
Pull drm updates from Dave Airlie:
"Highlights are usual, more AMD IP blocks for future hw, i915/xe
changes, Displayport tunnelling support for i915, msm YUV over DP
changes, new tests for ttm, but its mostly a lot of stuff all over the
place from lots of people.
core:
- EDID cleanups
- scheduler error handling fixes
- managed: add drmm_release_action() with tests
- add ratelimited drm debug print
- DPCD PSR early transport macro
- DP tunneling and bandwidth allocation helpers
- remove built-in edids
- dp: Avoid AUX transfers on powered-down displays
- dp: Add VSC SDP helpers
cross drivers:
- use new drm print helpers
- switch to ->read_edid callback
- gem: add stats for shared buffers plus updates to amdgpu, i915, xe
syncobj:
- fixes to waiting and sleeping
ttm:
- add tests
- fix errno codes
- simply busy-placement handling
- fix page decryption
media:
- tc358743: fix v4l device registration
video:
- move all kernel parameters for video behind CONFIG_VIDEO
sound:
- remove <drm/drm_edid.h> include from header
ci:
- add tests for msm
- fix apq8016 runner
efifb:
- use copy of global screen_info state
vesafb:
- use copy of global screen_info state
simplefb:
- fix logging
bridge:
- ite-6505: fix DP link-training bug
- samsung-dsim: fix error checking in probe
- samsung-dsim: add bsh-smm-s2/pro boards
- tc358767: fix regmap usage
- imx: add i.MX8MP HDMI PVI plus DT bindings
- imx: add i.MX8MP HDMI TX plus DT bindings
- sii902x: fix probing and unregistration
- tc358767: limit pixel PLL input range
- switch to new drm_bridge_read_edid() interface
panel:
- ltk050h3146w: error-handling fixes
- panel-edp: support delay between power-on and enable; use put_sync
in unprepare; support Mediatek MT8173 Chromebooks, BOE NV116WHM-N49
V8.0, BOE NV122WUM-N41, CSO MNC207QS1-1 plus DT bindings
- panel-lvds: support EDT ETML0700Z9NDHA plus DT bindings
- panel-novatek: FRIDA FRD400B25025-A-CTK plus DT bindings
- add BOE TH101MB31IG002-28A plus DT bindings
- add EDT ETML1010G3DRA plus DT bindings
- add Novatek NT36672E LCD DSI plus DT bindings
- nt36523: support 120Hz timings, fix includes
- simple: fix display timings on RK32FN48H
- visionox-vtdr6130: fix initialization
- add Powkiddy RGB10MAX3 plus DT bindings
- st7703: support panel rotation plus DT bindings
- add Himax HX83112A plus DT bindings
- ltk500hd1829: add support for ltk101b4029w and admatec 9904370
- simple: add BOE BP082WX1-100 8.2" panel plus DT bindungs
panel-orientation-quirks:
- GPD Win Mini
amdgpu:
- Validate DMABuf imports in compute VMs
- Add RAS ACA framework
- PSP 13 fixes
- Misc code cleanups
- Replay fixes
- Atom interpretor PS, WS bounds checking
- DML2 fixes
- Audio fixes
- DCN 3.5 Z state fixes
- Remove deprecated ida_simple usage
- UBSAN fixes
- RAS fixes
- Enable seq64 infrastructure
- DC color block enablement
- Documentation updates
- DC documentation updates
- DMCUB updates
- ATHUB 4.1 support
- LSDMA 7.0 support
- JPEG DPG support
- IH 7.0 support
- HDP 7.0 support
- VCN 5.0 support
- SMU 13.0.6 updates
- NBIO 7.11 updates
- SDMA 6.1 updates
- MMHUB 3.3 updates
- DCN 3.5.1 support
- NBIF 6.3.1 support
- VPE 6.1.1 support
amdkfd:
- Validate DMABuf imports in compute VMs
- SVM fixes
- Trap handler updates and enhancements
- Fix cache size reporting
- Relocate the trap handler
radeon:
- Atom interpretor PS, WS bounds checking
- Misc code cleanups
xe:
- new query for GuC submission version
- Remove unused persistent exec_queues
- Add vram frequency sysfs attributes
- Add the flag XE_VM_BIND_FLAG_DUMPABLE
- Drop pre-production workarounds
- Drop kunit tests for unsupported platforms
- Start pumbling SR-IOV support with memory based interrupts for VF
- Allow to map BO in GGTT with PAT index corresponding to XE_CACHE_UC
to work with memory based interrupts
- Add GuC Doorbells Manager as prep work SR-IOV
- Implement additional workarounds for xe2 and MTL
- Program a few registers according to perfomance guide spec for Xe2
- Fix remaining 32b build issues and enable it back
- Fix build with CONFIG_DEBUG_FS=n
- Fix warnings from GuC ABI headers
- Introduce Relay Communication for SR-IOV for VF <-> GuC <-> PF
- Release mmap mappings on rpm suspend
- Disable mid-thread preemption when not properly supported by
hardware
- Fix xe_exec by reserving extra fence slot for CPU bind
- Fix xe_exec with full long running exec queue
- Canonicalize addresses where needed for Xe2 and add to devcoredum
- Toggle USM support for Xe2
- Only allow 1 ufence per exec / bind IOCTL
- Add GuC firmware loading for Lunar Lake
- Add XE_VMA_PTE_64K VMA flag
i915:
- Add more ADL-N PCI IDs
- Enable fastboot also on older platforms
- Early transport for panel replay and PSR
- New ARL PCI IDs
- DP TPS4 PHY test pattern support
- Unify and improve VSC SDP for PSR and non-PSR cases
- Refactor memory regions and improve debug logging
- Rework global state serialization
- Remove unused CDCLK divider fields
- Unify HDCP connector logging format
- Use display instead of graphics version in display code
- Move VBT and opregion debugfs next to the implementation
- Abstract opregion interface, use opaque type
- MTL fixes
- HPD handling fixes
- Add GuC submission interface version query
- Atomically invalidate userptr on mmu-notifier
- Update handling of MMIO triggered reports
- Don't make assumptions about intel_wakeref_t type
- Extend driver code of Xe_LPG to Xe_LPG+
- Add flex arrays to struct i915_syncmap
- Allow for very slow HuC loading
- DP tunneling and bandwidth allocation support
msm:
- Correct bindings for MSM8976 and SM8650 platforms
- Start migration of MDP5 platforms to DPU driver
- X1E80100 MDSS support
- DPU:
- Improve DSC allocation, fixing several important corner cases
- Add support for SDM630/SDM660 platforms
- Simplify dpu_encoder_phys_ops
- Apply fixes targeting DSC support with a single DSC encoder
- Apply fixes for HCTL_EN timing configuration
- X1E80100 support
- Add support for YUV420 over DP
- GPU:
- fix sc7180 UBWC config
- fix a7xx LLC config
- new gpu support: a305B, a750, a702
- machine support: SM7150 (different power levels than other a618)
- a7xx devcoredump support
habanalabs:
- configure IRQ affinity according to NUMA node
- move HBM MMU page tables inside the HBM
- improve device reset
- check extended PCIe errors
ivpu:
- updates to firmware API
- refactor BO allocation
imx:
- use devm_ functions during init
hisilicon:
- fix EDID includes
mgag200:
- improve ioremap usage
- convert to struct drm_edid
- Work around PCI write bursts
nouveau:
- disp: use kmemdup()
- fix EDID includes
- documentation fixes
qaic:
- fixes to BO handling
- make use of DRM managed release
- fix order of remove operations
rockchip:
- analogix_dp: get encoder port from DT
- inno_hdmi: support HDMI for RK3128
- lvds: error-handling fixes
ssd130x:
- support SSD133x plus DT bindings
tegra:
- fix error handling
tilcdc:
- make use of DRM managed release
v3d:
- show memory stats in debugfs
- Support display MMU page size
vc4:
- fix error handling in plane prepare_fb
- fix framebuffer test in plane helpers
virtio:
- add venus capset defines
vkms:
- fix OOB access when programming the LUT
- Kconfig improvements
vmwgfx:
- unmap surface before changing plane state
- fix memory leak in error handling
- documentation fixes
- list command SVGA_3D_CMD_DEFINE_GB_SURFACE_V4 as invalid
- fix null-pointer deref in execbuf
- refactor display-mode probing
- fix fencing for creating cursor MOBs
- fix cursor-memory lifetime
xlnx:
- fix live video input for ZynqMP DPSUB
lima:
- fix memory leak
loongson:
- fail if no VRAM present
meson:
- switch to new drm_bridge_read_edid() interface
renesas:
- add RZ/G2L DU support plus DT bindings
mxsfb:
- Use managed mode config
sun4i:
- HDMI: updates to atomic mode setting
mediatek:
- Add display driver for MT8188 VDOSYS1
- DSI driver cleanups
- Filter modes according to hardware capability
- Fix a null pointer crash in mtk_drm_crtc_finish_page_flip
etnaviv:
- enhancements for NPU and MRT support"
* tag 'drm-next-2024-03-13' of https://gitlab.freedesktop.org/drm/kernel: (1420 commits)
drm/amd/display: Removed redundant @ symbol to fix kernel-doc warnings in -next repo
drm/amd/pm: wait for completion of the EnableGfxImu message
drm/amdgpu/soc21: add mode2 asic reset for SMU IP v14.0.1
drm/amdgpu: add smu 14.0.1 support
drm/amdgpu: add VPE 6.1.1 discovery support
drm/amdgpu/vpe: add VPE 6.1.1 support
drm/amdgpu/vpe: don't emit cond exec command under collaborate mode
drm/amdgpu/vpe: add collaborate mode support for VPE
drm/amdgpu/vpe: add PRED_EXE and COLLAB_SYNC OPCODE
drm/amdgpu/vpe: add multi instance VPE support
drm/amdgpu/discovery: add nbif v6_3_1 ip block
drm/amdgpu: Add nbif v6_3_1 ip block support
drm/amdgpu: Add pcie v6_1_0 ip headers (v5)
drm/amdgpu: Add nbif v6_3_1 ip headers (v5)
arch/powerpc: Remove <linux/fb.h> from backlight code
macintosh/via-pmu-backlight: Include <linux/backlight.h>
fbdev/chipsfb: Include <linux/backlight.h>
drm/etnaviv: Restore some id values
drm/amdkfd: make kfd_class constant
drm/amdgpu: add ring timeout information in devcoredump
...
Diffstat (limited to 'drivers/gpu/drm/msm')
79 files changed, 11416 insertions, 3758 deletions
diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index b1173128b5b9..b21ae2880c71 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -127,9 +127,8 @@ msm-$(CONFIG_DRM_MSM_DP)+= dp/dp_aux.o \ dp/dp_drm.o \ dp/dp_link.o \ dp/dp_panel.o \ - dp/dp_parser.o \ - dp/dp_power.o \ - dp/dp_audio.o + dp/dp_audio.o \ + dp/dp_utils.o msm-$(CONFIG_DRM_FBDEV_EMULATION) += msm_fbdev.o diff --git a/drivers/gpu/drm/msm/adreno/a2xx.xml.h b/drivers/gpu/drm/msm/adreno/a2xx.xml.h index f87a1312f580..23141cbcea97 100644 --- a/drivers/gpu/drm/msm/adreno/a2xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a2xx.xml.h @@ -3,28 +3,20 @@ /* Autogenerated file, DO NOT EDIT manually! -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://github.com/freedreno/envytools/ -git clone https://github.com/freedreno/envytools.git +This file was generated by the rules-ng-ng gen_header.py tool in this git repository: +http://gitlab.freedesktop.org/mesa/mesa/ +git clone https://gitlab.freedesktop.org/mesa/mesa.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2023-03-10 18:32:52) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 91929 bytes, from 2023-02-28 23:52:27) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from 2023-03-10 18:32:53) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 74995 bytes, from 2023-03-20 18:06:23) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113474 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149590 bytes, from 2023-02-14 19:37:12) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 198949 bytes, from 2023-03-20 18:06:23) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11404 bytes, from 2023-03-10 18:32:53) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 9055 bytes, from 2023-03-10 18:32:52) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2976 bytes, from 2023-03-10 18:32:52) - -Copyright (C) 2013-2023 by the following authors: -- Rob Clark <robdclark@gmail.com> (robclark) -- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) + +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 91929 bytes, from Fri Jun 2 14:59:26 2023) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from Fri Jun 2 14:59:26 2023) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 85691 bytes, from Fri Feb 16 09:49:01 2024) + +Copyright (C) 2013-2024 by the following authors: +- Rob Clark <robdclark@gmail.com> Rob Clark +- Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the @@ -45,8 +37,21 @@ IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifdef __KERNEL__ +#include <linux/bug.h> +#define assert(x) BUG_ON(!(x)) +#else +#include <assert.h> +#endif + +#ifdef __cplusplus +#define __struct_cast(X) +#else +#define __struct_cast(X) (struct X) +#endif enum a2xx_rb_dither_type { DITHER_PIXEL = 0, @@ -1442,16 +1447,18 @@ static inline uint32_t A2XX_MH_ARBITER_CONFIG_IN_FLIGHT_LIMIT(uint32_t val) #define A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT 0 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_WIDTH(uint32_t val) { - return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A2XX_A220_VSC_BIN_SIZE_WIDTH__SHIFT) & A2XX_A220_VSC_BIN_SIZE_WIDTH__MASK; } #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 #define A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT 5 static inline uint32_t A2XX_A220_VSC_BIN_SIZE_HEIGHT(uint32_t val) { - return ((val >> 5) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A2XX_A220_VSC_BIN_SIZE_HEIGHT__SHIFT) & A2XX_A220_VSC_BIN_SIZE_HEIGHT__MASK; } -static inline uint32_t REG_A2XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } +#define REG_A2XX_VSC_PIPE(i0) (0x00000c06 + 0x3*(i0)) static inline uint32_t REG_A2XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } @@ -1661,7 +1668,8 @@ static inline uint32_t A2XX_RB_COLOR_INFO_SWAP(uint32_t val) #define A2XX_RB_COLOR_INFO_BASE__SHIFT 12 static inline uint32_t A2XX_RB_COLOR_INFO_BASE(uint32_t val) { - return ((val >> 12) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A2XX_RB_COLOR_INFO_BASE__SHIFT) & A2XX_RB_COLOR_INFO_BASE__MASK; } #define REG_A2XX_RB_DEPTH_INFO 0x00002002 @@ -1675,7 +1683,8 @@ static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_form #define A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 static inline uint32_t A2XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) { - return ((val >> 12) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A2XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A2XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; } #define REG_A2XX_A225_RB_COLOR_INFO3 0x00002005 @@ -2654,7 +2663,8 @@ static inline uint32_t A2XX_RB_COPY_CONTROL_CLEAR_MASK(uint32_t val) #define A2XX_RB_COPY_DEST_PITCH__SHIFT 0 static inline uint32_t A2XX_RB_COPY_DEST_PITCH(uint32_t val) { - return ((val >> 5) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A2XX_RB_COPY_DEST_PITCH__SHIFT) & A2XX_RB_COPY_DEST_PITCH__MASK; } #define REG_A2XX_RB_COPY_DEST_INFO 0x0000231b @@ -3027,7 +3037,8 @@ static inline uint32_t A2XX_SQ_TEX_0_CLAMP_Z(enum sq_tex_clamp val) #define A2XX_SQ_TEX_0_PITCH__SHIFT 22 static inline uint32_t A2XX_SQ_TEX_0_PITCH(uint32_t val) { - return ((val >> 5) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A2XX_SQ_TEX_0_PITCH__SHIFT) & A2XX_SQ_TEX_0_PITCH__MASK; } #define A2XX_SQ_TEX_0_TILED 0x80000000 @@ -3061,7 +3072,8 @@ static inline uint32_t A2XX_SQ_TEX_1_CLAMP_POLICY(enum sq_tex_clamp_policy val) #define A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT 12 static inline uint32_t A2XX_SQ_TEX_1_BASE_ADDRESS(uint32_t val) { - return ((val >> 12) << A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT) & A2XX_SQ_TEX_1_BASE_ADDRESS__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A2XX_SQ_TEX_1_BASE_ADDRESS__SHIFT) & A2XX_SQ_TEX_1_BASE_ADDRESS__MASK; } #define REG_A2XX_SQ_TEX_2 0x00000002 @@ -3229,8 +3241,11 @@ static inline uint32_t A2XX_SQ_TEX_5_DIMENSION(enum sq_tex_dimension val) #define A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT 12 static inline uint32_t A2XX_SQ_TEX_5_MIP_ADDRESS(uint32_t val) { - return ((val >> 12) << A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT) & A2XX_SQ_TEX_5_MIP_ADDRESS__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A2XX_SQ_TEX_5_MIP_ADDRESS__SHIFT) & A2XX_SQ_TEX_5_MIP_ADDRESS__MASK; } +#ifdef __cplusplus +#endif #endif /* A2XX_XML */ diff --git a/drivers/gpu/drm/msm/adreno/a3xx.xml.h b/drivers/gpu/drm/msm/adreno/a3xx.xml.h index 237b564445be..5edd740ad3bb 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a3xx.xml.h @@ -3,28 +3,20 @@ /* Autogenerated file, DO NOT EDIT manually! -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://github.com/freedreno/envytools/ -git clone https://github.com/freedreno/envytools.git +This file was generated by the rules-ng-ng gen_header.py tool in this git repository: +http://gitlab.freedesktop.org/mesa/mesa/ +git clone https://gitlab.freedesktop.org/mesa/mesa.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2023-03-10 18:32:52) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 91929 bytes, from 2023-02-28 23:52:27) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from 2023-03-10 18:32:53) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 74995 bytes, from 2023-03-20 18:06:23) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113474 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149590 bytes, from 2023-02-14 19:37:12) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 198949 bytes, from 2023-03-20 18:06:23) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11404 bytes, from 2023-03-10 18:32:53) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 9055 bytes, from 2023-03-10 18:32:52) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2976 bytes, from 2023-03-10 18:32:52) - -Copyright (C) 2013-2022 by the following authors: -- Rob Clark <robdclark@gmail.com> (robclark) -- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) + +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84323 bytes, from Wed Aug 23 10:39:39 2023) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from Fri Jun 2 14:59:26 2023) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 85691 bytes, from Fri Feb 16 09:49:01 2024) + +Copyright (C) 2013-2024 by the following authors: +- Rob Clark <robdclark@gmail.com> Rob Clark +- Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the @@ -45,8 +37,21 @@ IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifdef __KERNEL__ +#include <linux/bug.h> +#define assert(x) BUG_ON(!(x)) +#else +#include <assert.h> +#endif + +#ifdef __cplusplus +#define __struct_cast(X) +#else +#define __struct_cast(X) (struct X) +#endif enum a3xx_tile_mode { LINEAR = 0, @@ -612,6 +617,7 @@ enum a3xx_tex_msaa { #define A3XX_INT0_CP_AHB_ERROR_HALT 0x00200000 #define A3XX_INT0_MISC_HANG_DETECT 0x01000000 #define A3XX_INT0_UCHE_OOB_ACCESS 0x02000000 + #define REG_A3XX_RBBM_HW_VERSION 0x00000000 #define REG_A3XX_RBBM_HW_RELEASE 0x00000001 @@ -672,13 +678,9 @@ enum a3xx_tex_msaa { #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3 0x0000005a #define REG_A3XX_RBBM_INT_SET_CMD 0x00000060 - #define REG_A3XX_RBBM_INT_CLEAR_CMD 0x00000061 - #define REG_A3XX_RBBM_INT_0_MASK 0x00000063 - #define REG_A3XX_RBBM_INT_0_STATUS 0x00000064 - #define REG_A3XX_RBBM_PERFCTR_CTL 0x00000080 #define A3XX_RBBM_PERFCTR_CTL_ENABLE 0x00000001 @@ -912,7 +914,7 @@ enum a3xx_tex_msaa { #define REG_A3XX_CP_PROTECT_STATUS 0x0000045f -static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; } +#define REG_A3XX_CP_PROTECT(i0) (0x00000460 + 0x1*(i0)) static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; } @@ -1167,7 +1169,8 @@ static inline uint32_t A3XX_RB_MODE_CONTROL_MRT(uint32_t val) #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT 4 static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val) { - return ((val >> 5) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK; } #define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00001000 #define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM 0x00002000 @@ -1218,7 +1221,7 @@ static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val) return ((_mesa_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK; } -static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; } +#define REG_A3XX_RB_MRT(i0) (0x000020c4 + 0x4*(i0)) static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; } #define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008 @@ -1267,7 +1270,8 @@ static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 17 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) { - return ((val >> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; } static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; } @@ -1275,7 +1279,8 @@ static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT 4 static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val) { - return ((val >> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK; } static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; } @@ -1407,7 +1412,8 @@ static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) #define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14 static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) { - return ((val >> 14) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK; + assert(!(val & 0x3fff)); + return (((val >> 14)) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK; } #define REG_A3XX_RB_COPY_DEST_BASE 0x000020ed @@ -1415,7 +1421,8 @@ static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) #define A3XX_RB_COPY_DEST_BASE_BASE__SHIFT 4 static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val) { - return ((val >> 5) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A3XX_RB_COPY_DEST_BASE_BASE__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A3XX_RB_COPY_DEST_BASE_BASE__MASK; } #define REG_A3XX_RB_COPY_DEST_PITCH 0x000020ee @@ -1423,7 +1430,8 @@ static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val) #define A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0 static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) { - return ((val >> 5) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK; } #define REG_A3XX_RB_COPY_DEST_INFO 0x000020ef @@ -1491,7 +1499,8 @@ static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_form #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 11 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) { - return ((val >> 12) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; } #define REG_A3XX_RB_DEPTH_PITCH 0x00002103 @@ -1499,7 +1508,8 @@ static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) #define A3XX_RB_DEPTH_PITCH__SHIFT 0 static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val) { - return ((val >> 3) << A3XX_RB_DEPTH_PITCH__SHIFT) & A3XX_RB_DEPTH_PITCH__MASK; + assert(!(val & 0x7)); + return (((val >> 3)) << A3XX_RB_DEPTH_PITCH__SHIFT) & A3XX_RB_DEPTH_PITCH__MASK; } #define REG_A3XX_RB_STENCIL_CONTROL 0x00002104 @@ -1562,7 +1572,8 @@ static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op v #define A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 11 static inline uint32_t A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) { - return ((val >> 12) << A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK; } #define REG_A3XX_RB_STENCIL_PITCH 0x00002107 @@ -1570,7 +1581,8 @@ static inline uint32_t A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) #define A3XX_RB_STENCIL_PITCH__SHIFT 0 static inline uint32_t A3XX_RB_STENCIL_PITCH(uint32_t val) { - return ((val >> 3) << A3XX_RB_STENCIL_PITCH__SHIFT) & A3XX_RB_STENCIL_PITCH__MASK; + assert(!(val & 0x7)); + return (((val >> 3)) << A3XX_RB_STENCIL_PITCH__SHIFT) & A3XX_RB_STENCIL_PITCH__MASK; } #define REG_A3XX_RB_STENCILREFMASK 0x00002108 @@ -1877,7 +1889,7 @@ static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val) return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK; } -static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0) { return 0x0000220b + 0x2*i0; } +#define REG_A3XX_HLSQ_CL_GLOBAL_WORK(i0) (0x0000220b + 0x2*(i0)) static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0; } @@ -1889,7 +1901,7 @@ static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return #define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG 0x00002214 -static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP(uint32_t i0) { return 0x00002215 + 0x1*i0; } +#define REG_A3XX_HLSQ_CL_KERNEL_GROUP(i0) (0x00002215 + 0x1*(i0)) static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO(uint32_t i0) { return 0x00002215 + 0x1*i0; } @@ -1965,7 +1977,7 @@ static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val) #define REG_A3XX_VFD_INDEX_OFFSET 0x00002245 -static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; } +#define REG_A3XX_VFD_FETCH(i0) (0x00002246 + 0x2*(i0)) static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; } #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f @@ -1997,7 +2009,7 @@ static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val) static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x00002247 + 0x2*i0; } -static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0) { return 0x00002266 + 0x1*i0; } +#define REG_A3XX_VFD_DECODE(i0) (0x00002266 + 0x1*(i0)) static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x00002266 + 0x1*i0; } #define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f @@ -2084,7 +2096,7 @@ static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) return ((val) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK; } -static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002282 + 0x1*i0; } +#define REG_A3XX_VPC_VARYING_INTERP(i0) (0x00002282 + 0x1*(i0)) static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002282 + 0x1*i0; } #define A3XX_VPC_VARYING_INTERP_MODE_C0__MASK 0x00000003 @@ -2184,7 +2196,7 @@ static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val) return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CF__MASK; } -static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; } +#define REG_A3XX_VPC_VARYING_PS_REPL(i0) (0x00002286 + 0x1*(i0)) static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; } #define A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK 0x00000003 @@ -2392,7 +2404,7 @@ static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; } -static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } +#define REG_A3XX_SP_VS_OUT(i0) (0x000022c7 + 0x1*(i0)) static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } #define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff @@ -2422,7 +2434,7 @@ static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK; } -static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; } +#define REG_A3XX_SP_VS_VPC_DST(i0) (0x000022d0 + 0x1*(i0)) static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; } #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x0000007f @@ -2477,7 +2489,8 @@ static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val) #define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT 0 static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val) { - return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK; + assert(!(val & 0x7f)); + return (((val >> 7)) << A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK; } #define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK 0x00ffff00 #define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT 8 @@ -2503,7 +2516,8 @@ static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val) #define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT 5 static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val) { - return ((val >> 5) << A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK; } #define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG 0x000022d8 @@ -2641,7 +2655,8 @@ static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val) #define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT 5 static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val) { - return ((val >> 5) << A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK; } #define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG 0x000022e6 @@ -2665,7 +2680,7 @@ static inline uint32_t A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val) return ((val) << A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK; } -static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; } +#define REG_A3XX_SP_FS_MRT(i0) (0x000022f0 + 0x1*(i0)) static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f0 + 0x1*i0; } #define A3XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff @@ -2678,7 +2693,7 @@ static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val) #define A3XX_SP_FS_MRT_REG_SINT 0x00000400 #define A3XX_SP_FS_MRT_REG_UINT 0x00000800 -static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0) { return 0x000022f4 + 0x1*i0; } +#define REG_A3XX_SP_FS_IMAGE_OUTPUT(i0) (0x000022f4 + 0x1*(i0)) static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) { return 0x000022f4 + 0x1*i0; } #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK 0x0000003f @@ -2821,18 +2836,20 @@ static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val) #define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val) { - return ((val >> 5) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A3XX_VSC_BIN_SIZE_WIDTH__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A3XX_VSC_BIN_SIZE_WIDTH__MASK; } #define A3XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 #define A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5 static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) { - return ((val >> 5) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK; } #define REG_A3XX_VSC_SIZE_ADDRESS 0x00000c02 -static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; } +#define REG_A3XX_VSC_PIPE(i0) (0x00000c06 + 0x3*(i0)) static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; } #define A3XX_VSC_PIPE_CONFIG_X__MASK 0x000003ff @@ -2887,7 +2904,7 @@ static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x000 #define REG_A3XX_GRAS_PERFCOUNTER3_SELECT 0x00000c8b -static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } +#define REG_A3XX_GRAS_CL_USER_PLANE(i0) (0x00000ca0 + 0x4*(i0)) static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { return 0x00000ca0 + 0x4*i0; } @@ -3228,7 +3245,8 @@ static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) #define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT 0 static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val) { - return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ1__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ1__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A3XX_TEX_CONST_3_LAYERSZ1__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ1__MASK; } #define A3XX_TEX_CONST_3_DEPTH__MASK 0x0ffe0000 #define A3XX_TEX_CONST_3_DEPTH__SHIFT 17 @@ -3240,8 +3258,11 @@ static inline uint32_t A3XX_TEX_CONST_3_DEPTH(uint32_t val) #define A3XX_TEX_CONST_3_LAYERSZ2__SHIFT 28 static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ2(uint32_t val) { - return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ2__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ2__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A3XX_TEX_CONST_3_LAYERSZ2__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ2__MASK; } +#ifdef __cplusplus +#endif #endif /* A3XX_XML */ diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c index c86b377f6f0d..5273dc849838 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c @@ -134,6 +134,13 @@ static int a3xx_hw_init(struct msm_gpu *gpu) /* Set up AOOO: */ gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c); gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c); + } else if (adreno_is_a305b(adreno_gpu)) { + gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x00181818); + gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x00181818); + gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x00000018); + gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x00000018); + gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x00000303); + gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003); } else if (adreno_is_a306(adreno_gpu)) { gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003); gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0000000a); @@ -230,7 +237,7 @@ static int a3xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001); /* Enable Clock gating: */ - if (adreno_is_a306(adreno_gpu)) + if (adreno_is_a305b(adreno_gpu) || adreno_is_a306(adreno_gpu)) gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa); else if (adreno_is_a320(adreno_gpu)) gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfffffff); @@ -333,7 +340,7 @@ static int a3xx_hw_init(struct msm_gpu *gpu) AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(2) | AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(6) | AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(14)); - } else if (adreno_is_a330(adreno_gpu)) { + } else if (adreno_is_a330(adreno_gpu) || adreno_is_a305b(adreno_gpu)) { /* NOTE: this (value take from downstream android driver) * includes some bits outside of the known bitfields. But * A330 has this "MERCIU queue" thing too, which might @@ -559,7 +566,7 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev) goto fail; /* if needed, allocate gmem: */ - if (adreno_is_a330(adreno_gpu)) { + if (adreno_is_a330(adreno_gpu) || adreno_is_a305b(adreno_gpu)) { ret = adreno_gpu_ocmem_init(&adreno_gpu->base.pdev->dev, adreno_gpu, &a3xx_gpu->ocmem); if (ret) diff --git a/drivers/gpu/drm/msm/adreno/a4xx.xml.h b/drivers/gpu/drm/msm/adreno/a4xx.xml.h index ff5f1e98a5fc..103a416a787f 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a4xx.xml.h @@ -3,28 +3,20 @@ /* Autogenerated file, DO NOT EDIT manually! -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://github.com/freedreno/envytools/ -git clone https://github.com/freedreno/envytools.git +This file was generated by the rules-ng-ng gen_header.py tool in this git repository: +http://gitlab.freedesktop.org/mesa/mesa/ +git clone https://gitlab.freedesktop.org/mesa/mesa.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2023-03-10 18:32:52) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 91929 bytes, from 2023-02-28 23:52:27) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from 2023-03-10 18:32:53) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 74995 bytes, from 2023-03-20 18:06:23) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113474 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149590 bytes, from 2023-02-14 19:37:12) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 198949 bytes, from 2023-03-20 18:06:23) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11404 bytes, from 2023-03-10 18:32:53) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 9055 bytes, from 2023-03-10 18:32:52) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2976 bytes, from 2023-03-10 18:32:52) - -Copyright (C) 2013-2022 by the following authors: -- Rob Clark <robdclark@gmail.com> (robclark) -- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) + +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113474 bytes, from Fri Jun 2 14:59:26 2023) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from Fri Jun 2 14:59:26 2023) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 85691 bytes, from Fri Feb 16 09:49:01 2024) + +Copyright (C) 2013-2024 by the following authors: +- Rob Clark <robdclark@gmail.com> Rob Clark +- Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the @@ -45,8 +37,21 @@ IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifdef __KERNEL__ +#include <linux/bug.h> +#define assert(x) BUG_ON(!(x)) +#else +#include <assert.h> +#endif + +#ifdef __cplusplus +#define __struct_cast(X) +#else +#define __struct_cast(X) (struct X) +#endif enum a4xx_color_fmt { RB4_A8_UNORM = 1, @@ -846,6 +851,7 @@ static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) { return ((val) << A4XX_CGC_HLSQ_EARLY_CYC__SHIFT) & A4XX_CGC_HLSQ_EARLY_CYC__MASK; } + #define A4XX_INT0_RBBM_GPU_IDLE 0x00000001 #define A4XX_INT0_RBBM_AHB_ERROR 0x00000002 #define A4XX_INT0_RBBM_REG_TIMEOUT 0x00000004 @@ -870,6 +876,7 @@ static inline uint32_t A4XX_CGC_HLSQ_EARLY_CYC(uint32_t val) #define A4XX_INT0_CP_AHB_ERROR_HALT 0x00200000 #define A4XX_INT0_MISC_HANG_DETECT 0x01000000 #define A4XX_INT0_UCHE_OOB_ACCESS 0x02000000 + #define REG_A4XX_RB_GMEM_BASE_ADDR 0x00000cc0 #define REG_A4XX_RB_PERFCTR_RB_SEL_0 0x00000cc7 @@ -923,13 +930,15 @@ static inline uint32_t A4XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val) #define A4XX_RB_MODE_CONTROL_WIDTH__SHIFT 0 static inline uint32_t A4XX_RB_MODE_CONTROL_WIDTH(uint32_t val) { - return ((val >> 5) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A4XX_RB_MODE_CONTROL_WIDTH__SHIFT) & A4XX_RB_MODE_CONTROL_WIDTH__MASK; } #define A4XX_RB_MODE_CONTROL_HEIGHT__MASK 0x00003f00 #define A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT 8 static inline uint32_t A4XX_RB_MODE_CONTROL_HEIGHT(uint32_t val) { - return ((val >> 5) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A4XX_RB_MODE_CONTROL_HEIGHT__SHIFT) & A4XX_RB_MODE_CONTROL_HEIGHT__MASK; } #define A4XX_RB_MODE_CONTROL_ENABLE_GMEM 0x00010000 @@ -968,7 +977,7 @@ static inline uint32_t A4XX_RB_RENDER_CONTROL2_MSAA_SAMPLES(uint32_t val) #define A4XX_RB_RENDER_CONTROL2_IJ_PERSP_SAMPLE 0x00004000 #define A4XX_RB_RENDER_CONTROL2_SIZE 0x00008000 -static inline uint32_t REG_A4XX_RB_MRT(uint32_t i0) { return 0x000020a4 + 0x5*i0; } +#define REG_A4XX_RB_MRT(i0) (0x000020a4 + 0x5*(i0)) static inline uint32_t REG_A4XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020a4 + 0x5*i0; } #define A4XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008 @@ -1018,7 +1027,8 @@ static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) #define A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 14 static inline uint32_t A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val) { - return ((val >> 4) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; + assert(!(val & 0xf)); + return (((val >> 4)) << A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A4XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK; } static inline uint32_t REG_A4XX_RB_MRT_BASE(uint32_t i0) { return 0x000020a6 + 0x5*i0; } @@ -1217,7 +1227,8 @@ static inline uint32_t A4XX_RB_FS_OUTPUT_SAMPLE_MASK(uint32_t val) #define A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT 2 static inline uint32_t A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR(uint32_t val) { - return ((val >> 2) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__SHIFT) & A4XX_RB_SAMPLE_COUNT_CONTROL_ADDR__MASK; } #define REG_A4XX_RB_RENDER_COMPONENTS 0x000020fb @@ -1293,7 +1304,8 @@ static inline uint32_t A4XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val) #define A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14 static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) { - return ((val >> 14) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK; + assert(!(val & 0x3fff)); + return (((val >> 14)) << A4XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A4XX_RB_COPY_CONTROL_GMEM_BASE__MASK; } #define REG_A4XX_RB_COPY_DEST_BASE 0x000020fd @@ -1301,7 +1313,8 @@ static inline uint32_t A4XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val) #define A4XX_RB_COPY_DEST_BASE_BASE__SHIFT 5 static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val) { - return ((val >> 5) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A4XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A4XX_RB_COPY_DEST_BASE_BASE__MASK; } #define REG_A4XX_RB_COPY_DEST_PITCH 0x000020fe @@ -1309,7 +1322,8 @@ static inline uint32_t A4XX_RB_COPY_DEST_BASE_BASE(uint32_t val) #define A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0 static inline uint32_t A4XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val) { - return ((val >> 5) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A4XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A4XX_RB_COPY_DEST_PITCH_PITCH__MASK; } #define REG_A4XX_RB_COPY_DEST_INFO 0x000020ff @@ -1387,7 +1401,8 @@ static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum a4xx_depth_format va #define A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 12 static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) { - return ((val >> 12) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A4XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A4XX_RB_DEPTH_INFO_DEPTH_BASE__MASK; } #define REG_A4XX_RB_DEPTH_PITCH 0x00002104 @@ -1395,7 +1410,8 @@ static inline uint32_t A4XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val) #define A4XX_RB_DEPTH_PITCH__SHIFT 0 static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val) { - return ((val >> 5) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A4XX_RB_DEPTH_PITCH__SHIFT) & A4XX_RB_DEPTH_PITCH__MASK; } #define REG_A4XX_RB_DEPTH_PITCH2 0x00002105 @@ -1403,7 +1419,8 @@ static inline uint32_t A4XX_RB_DEPTH_PITCH(uint32_t val) #define A4XX_RB_DEPTH_PITCH2__SHIFT 0 static inline uint32_t A4XX_RB_DEPTH_PITCH2(uint32_t val) { - return ((val >> 5) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A4XX_RB_DEPTH_PITCH2__SHIFT) & A4XX_RB_DEPTH_PITCH2__MASK; } #define REG_A4XX_RB_STENCIL_CONTROL 0x00002106 @@ -1468,7 +1485,8 @@ static inline uint32_t A4XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op v #define A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 12 static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) { - return ((val >> 12) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A4XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A4XX_RB_STENCIL_INFO_STENCIL_BASE__MASK; } #define REG_A4XX_RB_STENCIL_PITCH 0x00002109 @@ -1476,7 +1494,8 @@ static inline uint32_t A4XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val) #define A4XX_RB_STENCIL_PITCH__SHIFT 0 static inline uint32_t A4XX_RB_STENCIL_PITCH(uint32_t val) { - return ((val >> 5) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A4XX_RB_STENCIL_PITCH__SHIFT) & A4XX_RB_STENCIL_PITCH__MASK; } #define REG_A4XX_RB_STENCILREFMASK 0x0000210b @@ -1534,7 +1553,7 @@ static inline uint32_t A4XX_RB_BIN_OFFSET_Y(uint32_t val) return ((val) << A4XX_RB_BIN_OFFSET_Y__SHIFT) & A4XX_RB_BIN_OFFSET_Y__MASK; } -static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP(uint32_t i0) { return 0x00002120 + 0x2*i0; } +#define REG_A4XX_RB_VPORT_Z_CLAMP(i0) (0x00002120 + 0x2*(i0)) static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MIN(uint32_t i0) { return 0x00002120 + 0x2*i0; } @@ -1544,19 +1563,19 @@ static inline uint32_t REG_A4XX_RB_VPORT_Z_CLAMP_MAX(uint32_t i0) { return 0x000 #define REG_A4XX_RBBM_HW_CONFIGURATION 0x00000002 -static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP(uint32_t i0) { return 0x00000004 + 0x1*i0; } +#define REG_A4XX_RBBM_CLOCK_CTL_TP(i0) (0x00000004 + 0x1*(i0)) static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_TP_REG(uint32_t i0) { return 0x00000004 + 0x1*i0; } -static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP(uint32_t i0) { return 0x00000008 + 0x1*i0; } +#define REG_A4XX_RBBM_CLOCK_CTL2_TP(i0) (0x00000008 + 0x1*(i0)) static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_TP_REG(uint32_t i0) { return 0x00000008 + 0x1*i0; } -static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP(uint32_t i0) { return 0x0000000c + 0x1*i0; } +#define REG_A4XX_RBBM_CLOCK_HYST_TP(i0) (0x0000000c + 0x1*(i0)) static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_TP_REG(uint32_t i0) { return 0x0000000c + 0x1*i0; } -static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP(uint32_t i0) { return 0x00000010 + 0x1*i0; } +#define REG_A4XX_RBBM_CLOCK_DELAY_TP(i0) (0x00000010 + 0x1*(i0)) static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x00000010 + 0x1*i0; } @@ -2008,35 +2027,35 @@ static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_TP_REG(uint32_t i0) { return 0x #define REG_A4XX_RBBM_ALWAYSON_COUNTER_HI 0x0000016f -static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP(uint32_t i0) { return 0x00000068 + 0x1*i0; } +#define REG_A4XX_RBBM_CLOCK_CTL_SP(i0) (0x00000068 + 0x1*(i0)) static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_SP_REG(uint32_t i0) { return 0x00000068 + 0x1*i0; } -static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP(uint32_t i0) { return 0x0000006c + 0x1*i0; } +#define REG_A4XX_RBBM_CLOCK_CTL2_SP(i0) (0x0000006c + 0x1*(i0)) static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_SP_REG(uint32_t i0) { return 0x0000006c + 0x1*i0; } -static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP(uint32_t i0) { return 0x00000070 + 0x1*i0; } +#define REG_A4XX_RBBM_CLOCK_HYST_SP(i0) (0x00000070 + 0x1*(i0)) static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_SP_REG(uint32_t i0) { return 0x00000070 + 0x1*i0; } -static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP(uint32_t i0) { return 0x00000074 + 0x1*i0; } +#define REG_A4XX_RBBM_CLOCK_DELAY_SP(i0) (0x00000074 + 0x1*(i0)) static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_SP_REG(uint32_t i0) { return 0x00000074 + 0x1*i0; } -static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB(uint32_t i0) { return 0x00000078 + 0x1*i0; } +#define REG_A4XX_RBBM_CLOCK_CTL_RB(i0) (0x00000078 + 0x1*(i0)) static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_RB_REG(uint32_t i0) { return 0x00000078 + 0x1*i0; } -static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB(uint32_t i0) { return 0x0000007c + 0x1*i0; } +#define REG_A4XX_RBBM_CLOCK_CTL2_RB(i0) (0x0000007c + 0x1*(i0)) static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL2_RB_REG(uint32_t i0) { return 0x0000007c + 0x1*i0; } -static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(uint32_t i0) { return 0x00000082 + 0x1*i0; } +#define REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU(i0) (0x00000082 + 0x1*(i0)) static inline uint32_t REG_A4XX_RBBM_CLOCK_CTL_MARB_CCU_REG(uint32_t i0) { return 0x00000082 + 0x1*i0; } -static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(uint32_t i0) { return 0x00000086 + 0x1*i0; } +#define REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU(i0) (0x00000086 + 0x1*(i0)) static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { return 0x00000086 + 0x1*i0; } @@ -2052,7 +2071,7 @@ static inline uint32_t REG_A4XX_RBBM_CLOCK_HYST_RB_MARB_CCU_REG(uint32_t i0) { r #define REG_A4XX_RBBM_CLOCK_DELAY_COM_DCOM 0x0000008d -static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(uint32_t i0) { return 0x0000008e + 0x1*i0; } +#define REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1(i0) (0x0000008e + 0x1*(i0)) static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) { return 0x0000008e + 0x1*i0; } @@ -2192,7 +2211,7 @@ static inline uint32_t REG_A4XX_RBBM_CLOCK_DELAY_RB_MARB_CCU_L1_REG(uint32_t i0) #define REG_A4XX_CP_DRAW_STATE_ADDR 0x00000232 -static inline uint32_t REG_A4XX_CP_PROTECT(uint32_t i0) { return 0x00000240 + 0x1*i0; } +#define REG_A4XX_CP_PROTECT(i0) (0x00000240 + 0x1*(i0)) static inline uint32_t REG_A4XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000240 + 0x1*i0; } #define A4XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff @@ -2207,18 +2226,8 @@ static inline uint32_t A4XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) { return ((val) << A4XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A4XX_CP_PROTECT_REG_MASK_LEN__MASK; } -#define A4XX_CP_PROTECT_REG_TRAP_WRITE__MASK 0x20000000 -#define A4XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT 29 -static inline uint32_t A4XX_CP_PROTECT_REG_TRAP_WRITE(uint32_t val) -{ - return ((val) << A4XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT) & A4XX_CP_PROTECT_REG_TRAP_WRITE__MASK; -} -#define A4XX_CP_PROTECT_REG_TRAP_READ__MASK 0x40000000 -#define A4XX_CP_PROTECT_REG_TRAP_READ__SHIFT 30 -static inline uint32_t A4XX_CP_PROTECT_REG_TRAP_READ(uint32_t val) -{ - return ((val) << A4XX_CP_PROTECT_REG_TRAP_READ__SHIFT) & A4XX_CP_PROTECT_REG_TRAP_READ__MASK; -} +#define A4XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000 +#define A4XX_CP_PROTECT_REG_TRAP_READ 0x40000000 #define REG_A4XX_CP_PROTECT_CTRL 0x00000250 @@ -2254,7 +2263,7 @@ static inline uint32_t A4XX_CP_PROTECT_REG_TRAP_READ(uint32_t val) #define REG_A4XX_CP_PERFCOMBINER_SELECT 0x0000050b -static inline uint32_t REG_A4XX_CP_SCRATCH(uint32_t i0) { return 0x00000578 + 0x1*i0; } +#define REG_A4XX_CP_SCRATCH(i0) (0x00000578 + 0x1*(i0)) static inline uint32_t REG_A4XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000578 + 0x1*i0; } @@ -2364,7 +2373,7 @@ static inline uint32_t A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val) return ((val) << A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A4XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK; } -static inline uint32_t REG_A4XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; } +#define REG_A4XX_SP_VS_OUT(i0) (0x000022c7 + 0x1*(i0)) static inline uint32_t REG_A4XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; } #define A4XX_SP_VS_OUT_REG_A_REGID__MASK 0x000001ff @@ -2392,7 +2401,7 @@ static inline uint32_t A4XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) return ((val) << A4XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_VS_OUT_REG_B_COMPMASK__MASK; } -static inline uint32_t REG_A4XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d8 + 0x1*i0; } +#define REG_A4XX_SP_VS_VPC_DST(i0) (0x000022d8 + 0x1*(i0)) static inline uint32_t REG_A4XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d8 + 0x1*i0; } #define A4XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff @@ -2532,7 +2541,7 @@ static inline uint32_t A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID(uint32_t val) return ((val) << A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__SHIFT) & A4XX_SP_FS_OUTPUT_REG_SAMPLEMASK_REGID__MASK; } -static inline uint32_t REG_A4XX_SP_FS_MRT(uint32_t i0) { return 0x000022f1 + 0x1*i0; } +#define REG_A4XX_SP_FS_MRT(i0) (0x000022f1 + 0x1*(i0)) static inline uint32_t REG_A4XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f1 + 0x1*i0; } #define A4XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff @@ -2636,7 +2645,7 @@ static inline uint32_t A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) return ((val) << A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_DS_PARAM_REG_TOTALGSOUTVAR__MASK; } -static inline uint32_t REG_A4XX_SP_DS_OUT(uint32_t i0) { return 0x0000231b + 0x1*i0; } +#define REG_A4XX_SP_DS_OUT(i0) (0x0000231b + 0x1*(i0)) static inline uint32_t REG_A4XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000231b + 0x1*i0; } #define A4XX_SP_DS_OUT_REG_A_REGID__MASK 0x000001ff @@ -2664,7 +2673,7 @@ static inline uint32_t A4XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) return ((val) << A4XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_DS_OUT_REG_B_COMPMASK__MASK; } -static inline uint32_t REG_A4XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000232c + 0x1*i0; } +#define REG_A4XX_SP_DS_VPC_DST(i0) (0x0000232c + 0x1*(i0)) static inline uint32_t REG_A4XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000232c + 0x1*i0; } #define A4XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff @@ -2734,7 +2743,7 @@ static inline uint32_t A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR(uint32_t val) return ((val) << A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__SHIFT) & A4XX_SP_GS_PARAM_REG_TOTALGSOUTVAR__MASK; } -static inline uint32_t REG_A4XX_SP_GS_OUT(uint32_t i0) { return 0x00002342 + 0x1*i0; } +#define REG_A4XX_SP_GS_OUT(i0) (0x00002342 + 0x1*(i0)) static inline uint32_t REG_A4XX_SP_GS_OUT_REG(uint32_t i0) { return 0x00002342 + 0x1*i0; } #define A4XX_SP_GS_OUT_REG_A_REGID__MASK 0x000001ff @@ -2762,7 +2771,7 @@ static inline uint32_t A4XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val) return ((val) << A4XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A4XX_SP_GS_OUT_REG_B_COMPMASK__MASK; } -static inline uint32_t REG_A4XX_SP_GS_VPC_DST(uint32_t i0) { return 0x00002353 + 0x1*i0; } +#define REG_A4XX_SP_GS_VPC_DST(i0) (0x00002353 + 0x1*(i0)) static inline uint32_t REG_A4XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x00002353 + 0x1*i0; } #define A4XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff @@ -2862,11 +2871,11 @@ static inline uint32_t A4XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val) return ((val) << A4XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A4XX_VPC_PACK_NUMNONPOSVSVAR__MASK; } -static inline uint32_t REG_A4XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002142 + 0x1*i0; } +#define REG_A4XX_VPC_VARYING_INTERP(i0) (0x00002142 + 0x1*(i0)) static inline uint32_t REG_A4XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002142 + 0x1*i0; } -static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000214a + 0x1*i0; } +#define REG_A4XX_VPC_VARYING_PS_REPL(i0) (0x0000214a + 0x1*(i0)) static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000214a + 0x1*i0; } @@ -2877,13 +2886,15 @@ static inline uint32_t REG_A4XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0 #define A4XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 static inline uint32_t A4XX_VSC_BIN_SIZE_WIDTH(uint32_t val) { - return ((val >> 5) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A4XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A4XX_VSC_BIN_SIZE_WIDTH__MASK; } #define A4XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0 #define A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5 static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) { - return ((val >> 5) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A4XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A4XX_VSC_BIN_SIZE_HEIGHT__MASK; } #define REG_A4XX_VSC_SIZE_ADDRESS 0x00000c01 @@ -2892,7 +2903,7 @@ static inline uint32_t A4XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) #define REG_A4XX_VSC_DEBUG_ECO_CONTROL 0x00000c03 -static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } +#define REG_A4XX_VSC_PIPE_CONFIG(i0) (0x00000c08 + 0x1*(i0)) static inline uint32_t REG_A4XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c08 + 0x1*i0; } #define A4XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff @@ -2920,11 +2931,11 @@ static inline uint32_t A4XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) return ((val) << A4XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A4XX_VSC_PIPE_CONFIG_REG_H__MASK; } -static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c10 + 0x1*i0; } +#define REG_A4XX_VSC_PIPE_DATA_ADDRESS(i0) (0x00000c10 + 0x1*(i0)) static inline uint32_t REG_A4XX_VSC_PIPE_DATA_ADDRESS_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } -static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c18 + 0x1*i0; } +#define REG_A4XX_VSC_PIPE_DATA_LENGTH(i0) (0x00000c18 + 0x1*(i0)) static inline uint32_t REG_A4XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c18 + 0x1*i0; } @@ -3028,7 +3039,7 @@ static inline uint32_t A4XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) #define REG_A4XX_VFD_INDEX_OFFSET 0x00002208 -static inline uint32_t REG_A4XX_VFD_FETCH(uint32_t i0) { return 0x0000220a + 0x4*i0; } +#define REG_A4XX_VFD_FETCH(i0) (0x0000220a + 0x4*(i0)) static inline uint32_t REG_A4XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x0000220a + 0x4*i0; } #define A4XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f @@ -3064,7 +3075,7 @@ static inline uint32_t A4XX_VFD_FETCH_INSTR_3_STEPRATE(uint32_t val) return ((val) << A4XX_VFD_FETCH_INSTR_3_STEPRATE__SHIFT) & A4XX_VFD_FETCH_INSTR_3_STEPRATE__MASK; } -static inline uint32_t REG_A4XX_VFD_DECODE(uint32_t i0) { return 0x0000228a + 0x1*i0; } +#define REG_A4XX_VFD_DECODE(i0) (0x0000228a + 0x1*(i0)) static inline uint32_t REG_A4XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000228a + 0x1*i0; } #define A4XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f @@ -4262,7 +4273,8 @@ static inline uint32_t A4XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val) #define A4XX_TEX_CONST_3_LAYERSZ__SHIFT 0 static inline uint32_t A4XX_TEX_CONST_3_LAYERSZ(uint32_t val) { - return ((val >> 12) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A4XX_TEX_CONST_3_LAYERSZ__SHIFT) & A4XX_TEX_CONST_3_LAYERSZ__MASK; } #define A4XX_TEX_CONST_3_DEPTH__MASK 0x7ffc0000 #define A4XX_TEX_CONST_3_DEPTH__SHIFT 18 @@ -4276,13 +4288,15 @@ static inline uint32_t A4XX_TEX_CONST_3_DEPTH(uint32_t val) #define A4XX_TEX_CONST_4_LAYERSZ__SHIFT 0 static inline uint32_t A4XX_TEX_CONST_4_LAYERSZ(uint32_t val) { - return ((val >> 12) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A4XX_TEX_CONST_4_LAYERSZ__SHIFT) & A4XX_TEX_CONST_4_LAYERSZ__MASK; } #define A4XX_TEX_CONST_4_BASE__MASK 0xffffffe0 #define A4XX_TEX_CONST_4_BASE__SHIFT 5 static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val) { - return ((val >> 5) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A4XX_TEX_CONST_4_BASE__SHIFT) & A4XX_TEX_CONST_4_BASE__MASK; } #define REG_A4XX_TEX_CONST_5 0x00000005 @@ -4296,7 +4310,8 @@ static inline uint32_t A4XX_TEX_CONST_4_BASE(uint32_t val) #define A4XX_SSBO_0_0_BASE__SHIFT 5 static inline uint32_t A4XX_SSBO_0_0_BASE(uint32_t val) { - return ((val >> 5) << A4XX_SSBO_0_0_BASE__SHIFT) & A4XX_SSBO_0_0_BASE__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A4XX_SSBO_0_0_BASE__SHIFT) & A4XX_SSBO_0_0_BASE__MASK; } #define REG_A4XX_SSBO_0_1 0x00000001 @@ -4312,7 +4327,8 @@ static inline uint32_t A4XX_SSBO_0_1_PITCH(uint32_t val) #define A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT 12 static inline uint32_t A4XX_SSBO_0_2_ARRAY_PITCH(uint32_t val) { - return ((val >> 12) << A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A4XX_SSBO_0_2_ARRAY_PITCH__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A4XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A4XX_SSBO_0_2_ARRAY_PITCH__MASK; } #define REG_A4XX_SSBO_0_3 0x00000003 @@ -4357,5 +4373,7 @@ static inline uint32_t A4XX_SSBO_1_1_DEPTH(uint32_t val) return ((val) << A4XX_SSBO_1_1_DEPTH__SHIFT) & A4XX_SSBO_1_1_DEPTH__MASK; } +#ifdef __cplusplus +#endif #endif /* A4XX_XML */ diff --git a/drivers/gpu/drm/msm/adreno/a5xx.xml.h b/drivers/gpu/drm/msm/adreno/a5xx.xml.h index 03b7ee592b11..d66306c14986 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a5xx.xml.h @@ -3,28 +3,20 @@ /* Autogenerated file, DO NOT EDIT manually! -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://github.com/freedreno/envytools/ -git clone https://github.com/freedreno/envytools.git +This file was generated by the rules-ng-ng gen_header.py tool in this git repository: +http://gitlab.freedesktop.org/mesa/mesa/ +git clone https://gitlab.freedesktop.org/mesa/mesa.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2023-03-10 18:32:52) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 91929 bytes, from 2023-02-28 23:52:27) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from 2023-03-10 18:32:53) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 74995 bytes, from 2023-03-20 18:06:23) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113474 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149590 bytes, from 2023-02-14 19:37:12) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 198949 bytes, from 2023-03-20 18:06:23) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11404 bytes, from 2023-03-10 18:32:53) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 9055 bytes, from 2023-03-10 18:32:52) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2976 bytes, from 2023-03-10 18:32:52) - -Copyright (C) 2013-2023 by the following authors: -- Rob Clark <robdclark@gmail.com> (robclark) -- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) + +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 151693 bytes, from Wed Aug 23 10:39:39 2023) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from Fri Jun 2 14:59:26 2023) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 85691 bytes, from Fri Feb 16 09:49:01 2024) + +Copyright (C) 2013-2024 by the following authors: +- Rob Clark <robdclark@gmail.com> Rob Clark +- Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the @@ -45,8 +37,21 @@ IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifdef __KERNEL__ +#include <linux/bug.h> +#define assert(x) BUG_ON(!(x)) +#else +#include <assert.h> +#endif + +#ifdef __cplusplus +#define __struct_cast(X) +#else +#define __struct_cast(X) (struct X) +#endif enum a5xx_color_fmt { RB5_A8_UNORM = 2, @@ -907,12 +912,14 @@ enum a5xx_tex_type { #define A5XX_INT0_GPMU_FIRMWARE 0x20000000 #define A5XX_INT0_ISDB_CPU_IRQ 0x40000000 #define A5XX_INT0_ISDB_UNDER_DEBUG 0x80000000 + #define A5XX_CP_INT_CP_OPCODE_ERROR 0x00000001 #define A5XX_CP_INT_CP_RESERVED_BIT_ERROR 0x00000002 #define A5XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004 #define A5XX_CP_INT_CP_DMA_ERROR 0x00000008 #define A5XX_CP_INT_CP_REGISTER_PROTECTION_ERROR 0x00000010 #define A5XX_CP_INT_CP_AHB_ERROR 0x00000020 + #define REG_A5XX_CP_RB_BASE 0x00000800 #define REG_A5XX_CP_RB_BASE_HI 0x00000801 @@ -1031,11 +1038,11 @@ enum a5xx_tex_type { #define REG_A5XX_CP_IB2_BUFSZ 0x00000b24 -static inline uint32_t REG_A5XX_CP_SCRATCH(uint32_t i0) { return 0x00000b78 + 0x1*i0; } +#define REG_A5XX_CP_SCRATCH(i0) (0x00000b78 + 0x1*(i0)) static inline uint32_t REG_A5XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000b78 + 0x1*i0; } -static inline uint32_t REG_A5XX_CP_PROTECT(uint32_t i0) { return 0x00000880 + 0x1*i0; } +#define REG_A5XX_CP_PROTECT(i0) (0x00000880 + 0x1*(i0)) static inline uint32_t REG_A5XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000880 + 0x1*i0; } #define A5XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0001ffff @@ -1050,18 +1057,8 @@ static inline uint32_t A5XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) { return ((val) << A5XX_CP_PROTECT_REG_MASK_LEN__SHIFT) & A5XX_CP_PROTECT_REG_MASK_LEN__MASK; } -#define A5XX_CP_PROTECT_REG_TRAP_WRITE__MASK 0x20000000 -#define A5XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT 29 -static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_WRITE(uint32_t val) -{ - return ((val) << A5XX_CP_PROTECT_REG_TRAP_WRITE__SHIFT) & A5XX_CP_PROTECT_REG_TRAP_WRITE__MASK; -} -#define A5XX_CP_PROTECT_REG_TRAP_READ__MASK 0x40000000 -#define A5XX_CP_PROTECT_REG_TRAP_READ__SHIFT 30 -static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_READ(uint32_t val) -{ - return ((val) << A5XX_CP_PROTECT_REG_TRAP_READ__SHIFT) & A5XX_CP_PROTECT_REG_TRAP_READ__MASK; -} +#define A5XX_CP_PROTECT_REG_TRAP_WRITE 0x20000000 +#define A5XX_CP_PROTECT_REG_TRAP_READ 0x40000000 #define REG_A5XX_CP_PROTECT_CNTL 0x000008a0 @@ -1833,192 +1830,37 @@ static inline uint32_t A5XX_CP_PROTECT_REG_TRAP_READ(uint32_t val) #define REG_A5XX_RBBM_ALWAYSON_COUNTER_HI 0x000004d3 #define REG_A5XX_RBBM_STATUS 0x000004f5 -#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__MASK 0x80000000 -#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__SHIFT 31 -static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB__MASK; -} -#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__MASK 0x40000000 -#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__SHIFT 30 -static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP__MASK; -} -#define A5XX_RBBM_STATUS_HLSQ_BUSY__MASK 0x20000000 -#define A5XX_RBBM_STATUS_HLSQ_BUSY__SHIFT 29 -static inline uint32_t A5XX_RBBM_STATUS_HLSQ_BUSY(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_HLSQ_BUSY__SHIFT) & A5XX_RBBM_STATUS_HLSQ_BUSY__MASK; -} -#define A5XX_RBBM_STATUS_VSC_BUSY__MASK 0x10000000 -#define A5XX_RBBM_STATUS_VSC_BUSY__SHIFT 28 -static inline uint32_t A5XX_RBBM_STATUS_VSC_BUSY(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_VSC_BUSY__SHIFT) & A5XX_RBBM_STATUS_VSC_BUSY__MASK; -} -#define A5XX_RBBM_STATUS_TPL1_BUSY__MASK 0x08000000 -#define A5XX_RBBM_STATUS_TPL1_BUSY__SHIFT 27 -static inline uint32_t A5XX_RBBM_STATUS_TPL1_BUSY(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_TPL1_BUSY__SHIFT) & A5XX_RBBM_STATUS_TPL1_BUSY__MASK; -} -#define A5XX_RBBM_STATUS_SP_BUSY__MASK 0x04000000 -#define A5XX_RBBM_STATUS_SP_BUSY__SHIFT 26 -static inline uint32_t A5XX_RBBM_STATUS_SP_BUSY(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_SP_BUSY__SHIFT) & A5XX_RBBM_STATUS_SP_BUSY__MASK; -} -#define A5XX_RBBM_STATUS_UCHE_BUSY__MASK 0x02000000 -#define A5XX_RBBM_STATUS_UCHE_BUSY__SHIFT 25 -static inline uint32_t A5XX_RBBM_STATUS_UCHE_BUSY(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_UCHE_BUSY__SHIFT) & A5XX_RBBM_STATUS_UCHE_BUSY__MASK; -} -#define A5XX_RBBM_STATUS_VPC_BUSY__MASK 0x01000000 -#define A5XX_RBBM_STATUS_VPC_BUSY__SHIFT 24 -static inline uint32_t A5XX_RBBM_STATUS_VPC_BUSY(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_VPC_BUSY__SHIFT) & A5XX_RBBM_STATUS_VPC_BUSY__MASK; -} -#define A5XX_RBBM_STATUS_VFDP_BUSY__MASK 0x00800000 -#define A5XX_RBBM_STATUS_VFDP_BUSY__SHIFT 23 -static inline uint32_t A5XX_RBBM_STATUS_VFDP_BUSY(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_VFDP_BUSY__SHIFT) & A5XX_RBBM_STATUS_VFDP_BUSY__MASK; -} -#define A5XX_RBBM_STATUS_VFD_BUSY__MASK 0x00400000 -#define A5XX_RBBM_STATUS_VFD_BUSY__SHIFT 22 -static inline uint32_t A5XX_RBBM_STATUS_VFD_BUSY(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_VFD_BUSY__SHIFT) & A5XX_RBBM_STATUS_VFD_BUSY__MASK; -} -#define A5XX_RBBM_STATUS_TESS_BUSY__MASK 0x00200000 -#define A5XX_RBBM_STATUS_TESS_BUSY__SHIFT 21 -static inline uint32_t A5XX_RBBM_STATUS_TESS_BUSY(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_TESS_BUSY__SHIFT) & A5XX_RBBM_STATUS_TESS_BUSY__MASK; -} -#define A5XX_RBBM_STATUS_PC_VSD_BUSY__MASK 0x00100000 -#define A5XX_RBBM_STATUS_PC_VSD_BUSY__SHIFT 20 -static inline uint32_t A5XX_RBBM_STATUS_PC_VSD_BUSY(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_PC_VSD_BUSY__SHIFT) & A5XX_RBBM_STATUS_PC_VSD_BUSY__MASK; -} -#define A5XX_RBBM_STATUS_PC_DCALL_BUSY__MASK 0x00080000 -#define A5XX_RBBM_STATUS_PC_DCALL_BUSY__SHIFT 19 -static inline uint32_t A5XX_RBBM_STATUS_PC_DCALL_BUSY(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_PC_DCALL_BUSY__SHIFT) & A5XX_RBBM_STATUS_PC_DCALL_BUSY__MASK; -} -#define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__MASK 0x00040000 -#define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__SHIFT 18 -static inline uint32_t A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__SHIFT) & A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY__MASK; -} -#define A5XX_RBBM_STATUS_DCOM_BUSY__MASK 0x00020000 -#define A5XX_RBBM_STATUS_DCOM_BUSY__SHIFT 17 -static inline uint32_t A5XX_RBBM_STATUS_DCOM_BUSY(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_DCOM_BUSY__SHIFT) & A5XX_RBBM_STATUS_DCOM_BUSY__MASK; -} -#define A5XX_RBBM_STATUS_COM_BUSY__MASK 0x00010000 -#define A5XX_RBBM_STATUS_COM_BUSY__SHIFT 16 -static inline uint32_t A5XX_RBBM_STATUS_COM_BUSY(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_COM_BUSY__SHIFT) & A5XX_RBBM_STATUS_COM_BUSY__MASK; -} -#define A5XX_RBBM_STATUS_LRZ_BUZY__MASK 0x00008000 -#define A5XX_RBBM_STATUS_LRZ_BUZY__SHIFT 15 -static inline uint32_t A5XX_RBBM_STATUS_LRZ_BUZY(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_LRZ_BUZY__SHIFT) & A5XX_RBBM_STATUS_LRZ_BUZY__MASK; -} -#define A5XX_RBBM_STATUS_A2D_DSP_BUSY__MASK 0x00004000 -#define A5XX_RBBM_STATUS_A2D_DSP_BUSY__SHIFT 14 -static inline uint32_t A5XX_RBBM_STATUS_A2D_DSP_BUSY(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_A2D_DSP_BUSY__SHIFT) & A5XX_RBBM_STATUS_A2D_DSP_BUSY__MASK; -} -#define A5XX_RBBM_STATUS_CCUFCHE_BUSY__MASK 0x00002000 -#define A5XX_RBBM_STATUS_CCUFCHE_BUSY__SHIFT 13 -static inline uint32_t A5XX_RBBM_STATUS_CCUFCHE_BUSY(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_CCUFCHE_BUSY__SHIFT) & A5XX_RBBM_STATUS_CCUFCHE_BUSY__MASK; -} -#define A5XX_RBBM_STATUS_RB_BUSY__MASK 0x00001000 -#define A5XX_RBBM_STATUS_RB_BUSY__SHIFT 12 -static inline uint32_t A5XX_RBBM_STATUS_RB_BUSY(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_RB_BUSY__SHIFT) & A5XX_RBBM_STATUS_RB_BUSY__MASK; -} -#define A5XX_RBBM_STATUS_RAS_BUSY__MASK 0x00000800 -#define A5XX_RBBM_STATUS_RAS_BUSY__SHIFT 11 -static inline uint32_t A5XX_RBBM_STATUS_RAS_BUSY(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_RAS_BUSY__SHIFT) & A5XX_RBBM_STATUS_RAS_BUSY__MASK; -} -#define A5XX_RBBM_STATUS_TSE_BUSY__MASK 0x00000400 -#define A5XX_RBBM_STATUS_TSE_BUSY__SHIFT 10 -static inline uint32_t A5XX_RBBM_STATUS_TSE_BUSY(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_TSE_BUSY__SHIFT) & A5XX_RBBM_STATUS_TSE_BUSY__MASK; -} -#define A5XX_RBBM_STATUS_VBIF_BUSY__MASK 0x00000200 -#define A5XX_RBBM_STATUS_VBIF_BUSY__SHIFT 9 -static inline uint32_t A5XX_RBBM_STATUS_VBIF_BUSY(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_VBIF_BUSY__SHIFT) & A5XX_RBBM_STATUS_VBIF_BUSY__MASK; -} -#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__MASK 0x00000100 -#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__SHIFT 8 -static inline uint32_t A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__SHIFT) & A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST__MASK; -} -#define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__MASK 0x00000080 -#define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__SHIFT 7 -static inline uint32_t A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__SHIFT) & A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST__MASK; -} -#define A5XX_RBBM_STATUS_CP_BUSY__MASK 0x00000040 -#define A5XX_RBBM_STATUS_CP_BUSY__SHIFT 6 -static inline uint32_t A5XX_RBBM_STATUS_CP_BUSY(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_CP_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_BUSY__MASK; -} -#define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__MASK 0x00000020 -#define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__SHIFT 5 -static inline uint32_t A5XX_RBBM_STATUS_GPMU_MASTER_BUSY(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__SHIFT) & A5XX_RBBM_STATUS_GPMU_MASTER_BUSY__MASK; -} -#define A5XX_RBBM_STATUS_CP_CRASH_BUSY__MASK 0x00000010 -#define A5XX_RBBM_STATUS_CP_CRASH_BUSY__SHIFT 4 -static inline uint32_t A5XX_RBBM_STATUS_CP_CRASH_BUSY(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_CP_CRASH_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_CRASH_BUSY__MASK; -} -#define A5XX_RBBM_STATUS_CP_ETS_BUSY__MASK 0x00000008 -#define A5XX_RBBM_STATUS_CP_ETS_BUSY__SHIFT 3 -static inline uint32_t A5XX_RBBM_STATUS_CP_ETS_BUSY(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_CP_ETS_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_ETS_BUSY__MASK; -} -#define A5XX_RBBM_STATUS_CP_PFP_BUSY__MASK 0x00000004 -#define A5XX_RBBM_STATUS_CP_PFP_BUSY__SHIFT 2 -static inline uint32_t A5XX_RBBM_STATUS_CP_PFP_BUSY(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_CP_PFP_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_PFP_BUSY__MASK; -} -#define A5XX_RBBM_STATUS_CP_ME_BUSY__MASK 0x00000002 -#define A5XX_RBBM_STATUS_CP_ME_BUSY__SHIFT 1 -static inline uint32_t A5XX_RBBM_STATUS_CP_ME_BUSY(uint32_t val) -{ - return ((val) << A5XX_RBBM_STATUS_CP_ME_BUSY__SHIFT) & A5XX_RBBM_STATUS_CP_ME_BUSY__MASK; -} +#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x80000000 +#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x40000000 +#define A5XX_RBBM_STATUS_HLSQ_BUSY 0x20000000 +#define A5XX_RBBM_STATUS_VSC_BUSY 0x10000000 +#define A5XX_RBBM_STATUS_TPL1_BUSY 0x08000000 +#define A5XX_RBBM_STATUS_SP_BUSY 0x04000000 +#define A5XX_RBBM_STATUS_UCHE_BUSY 0x02000000 +#define A5XX_RBBM_STATUS_VPC_BUSY 0x01000000 +#define A5XX_RBBM_STATUS_VFDP_BUSY 0x00800000 +#define A5XX_RBBM_STATUS_VFD_BUSY 0x00400000 +#define A5XX_RBBM_STATUS_TESS_BUSY 0x00200000 +#define A5XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000 +#define A5XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000 +#define A5XX_RBBM_STATUS_GPMU_SLAVE_BUSY 0x00040000 +#define A5XX_RBBM_STATUS_DCOM_BUSY 0x00020000 +#define A5XX_RBBM_STATUS_COM_BUSY 0x00010000 +#define A5XX_RBBM_STATUS_LRZ_BUZY 0x00008000 +#define A5XX_RBBM_STATUS_A2D_DSP_BUSY 0x00004000 +#define A5XX_RBBM_STATUS_CCUFCHE_BUSY 0x00002000 +#define A5XX_RBBM_STATUS_RB_BUSY 0x00001000 +#define A5XX_RBBM_STATUS_RAS_BUSY 0x00000800 +#define A5XX_RBBM_STATUS_TSE_BUSY 0x00000400 +#define A5XX_RBBM_STATUS_VBIF_BUSY 0x00000200 +#define A5XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_HYST 0x00000100 +#define A5XX_RBBM_STATUS_CP_BUSY_IGN_HYST 0x00000080 +#define A5XX_RBBM_STATUS_CP_BUSY 0x00000040 +#define A5XX_RBBM_STATUS_GPMU_MASTER_BUSY 0x00000020 +#define A5XX_RBBM_STATUS_CP_CRASH_BUSY 0x00000010 +#define A5XX_RBBM_STATUS_CP_ETS_BUSY 0x00000008 +#define A5XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004 +#define A5XX_RBBM_STATUS_CP_ME_BUSY 0x00000002 #define A5XX_RBBM_STATUS_HI_BUSY 0x00000001 #define REG_A5XX_RBBM_STATUS3 0x00000530 @@ -2113,13 +1955,15 @@ static inline uint32_t A5XX_RBBM_STATUS_CP_ME_BUSY(uint32_t val) #define A5XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 static inline uint32_t A5XX_VSC_BIN_SIZE_WIDTH(uint32_t val) { - return ((val >> 5) << A5XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A5XX_VSC_BIN_SIZE_WIDTH__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A5XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A5XX_VSC_BIN_SIZE_WIDTH__MASK; } #define A5XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001fe00 #define A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT 9 static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) { - return ((val >> 5) << A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A5XX_VSC_BIN_SIZE_HEIGHT__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A5XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A5XX_VSC_BIN_SIZE_HEIGHT__MASK; } #define REG_A5XX_VSC_SIZE_ADDRESS_LO 0x00000bc3 @@ -2130,7 +1974,7 @@ static inline uint32_t A5XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) #define REG_A5XX_UNKNOWN_0BC6 0x00000bc6 -static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; } +#define REG_A5XX_VSC_PIPE_CONFIG(i0) (0x00000bd0 + 0x1*(i0)) static inline uint32_t REG_A5XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000bd0 + 0x1*i0; } #define A5XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff @@ -2158,13 +2002,13 @@ static inline uint32_t A5XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) return ((val) << A5XX_VSC_PIPE_CONFIG_REG_H__SHIFT) & A5XX_VSC_PIPE_CONFIG_REG_H__MASK; } -static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000be0 + 0x2*i0; } +#define REG_A5XX_VSC_PIPE_DATA_ADDRESS(i0) (0x00000be0 + 0x2*(i0)) static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_LO(uint32_t i0) { return 0x00000be0 + 0x2*i0; } static inline uint32_t REG_A5XX_VSC_PIPE_DATA_ADDRESS_HI(uint32_t i0) { return 0x00000be1 + 0x2*i0; } -static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c00 + 0x1*i0; } +#define REG_A5XX_VSC_PIPE_DATA_LENGTH(i0) (0x00000c00 + 0x1*(i0)) static inline uint32_t REG_A5XX_VSC_PIPE_DATA_LENGTH_REG(uint32_t i0) { return 0x00000c00 + 0x1*i0; } @@ -2594,36 +2438,6 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val) #define REG_A5XX_GPMU_DATA_RAM_BASE 0x00009800 -#define REG_A5XX_GPMU_SP_POWER_CNTL 0x0000a881 - -#define REG_A5XX_GPMU_RBCCU_CLOCK_CNTL 0x0000a886 - -#define REG_A5XX_GPMU_RBCCU_POWER_CNTL 0x0000a887 - -#define REG_A5XX_GPMU_SP_PWR_CLK_STATUS 0x0000a88b -#define A5XX_GPMU_SP_PWR_CLK_STATUS_PWR_ON 0x00100000 - -#define REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS 0x0000a88d -#define A5XX_GPMU_RBCCU_PWR_CLK_STATUS_PWR_ON 0x00100000 - -#define REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY 0x0000a891 - -#define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL 0x0000a892 - -#define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST 0x0000a893 - -#define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL 0x0000a894 - -#define REG_A5XX_GPMU_WFI_CONFIG 0x0000a8c1 - -#define REG_A5XX_GPMU_RBBM_INTR_INFO 0x0000a8d6 - -#define REG_A5XX_GPMU_CM3_SYSRESET 0x0000a8d8 - -#define REG_A5XX_GPMU_GENERAL_0 0x0000a8e0 - -#define REG_A5XX_GPMU_GENERAL_1 0x0000a8e1 - #define REG_A5XX_SP_POWER_COUNTER_0_LO 0x0000a840 #define REG_A5XX_SP_POWER_COUNTER_0_HI 0x0000a841 @@ -2748,10 +2562,42 @@ static inline uint32_t A5XX_VSC_RESOLVE_CNTL_Y(uint32_t val) #define REG_A5XX_GPMU_POWER_COUNTER_SELECT_1 0x0000a87d +#define REG_A5XX_GPMU_GPMU_SP_CLOCK_CONTROL 0x0000a880 + +#define REG_A5XX_GPMU_SP_POWER_CNTL 0x0000a881 + +#define REG_A5XX_GPMU_RBCCU_CLOCK_CNTL 0x0000a886 + +#define REG_A5XX_GPMU_RBCCU_POWER_CNTL 0x0000a887 + +#define REG_A5XX_GPMU_SP_PWR_CLK_STATUS 0x0000a88b +#define A5XX_GPMU_SP_PWR_CLK_STATUS_PWR_ON 0x00100000 + +#define REG_A5XX_GPMU_RBCCU_PWR_CLK_STATUS 0x0000a88d +#define A5XX_GPMU_RBCCU_PWR_CLK_STATUS_PWR_ON 0x00100000 + +#define REG_A5XX_GPMU_PWR_COL_STAGGER_DELAY 0x0000a891 + +#define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_CTRL 0x0000a892 + +#define REG_A5XX_GPMU_PWR_COL_INTER_FRAME_HYST 0x0000a893 + +#define REG_A5XX_GPMU_PWR_COL_BINNING_CTRL 0x0000a894 + #define REG_A5XX_GPMU_CLOCK_THROTTLE_CTRL 0x0000a8a3 #define REG_A5XX_GPMU_THROTTLE_UNMASK_FORCE_CTRL 0x0000a8a8 +#define REG_A5XX_GPMU_WFI_CONFIG 0x0000a8c1 + +#define REG_A5XX_GPMU_RBBM_INTR_INFO 0x0000a8d6 + +#define REG_A5XX_GPMU_CM3_SYSRESET 0x0000a8d8 + +#define REG_A5XX_GPMU_GENERAL_0 0x0000a8e0 + +#define REG_A5XX_GPMU_GENERAL_1 0x0000a8e1 + #define REG_A5XX_GPMU_TEMP_SENSOR_ID 0x0000ac00 #define REG_A5XX_GPMU_TEMP_SENSOR_CONFIG 0x0000ac01 @@ -3112,7 +2958,8 @@ static inline uint32_t A5XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) #define A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT 0 static inline uint32_t A5XX_GRAS_LRZ_BUFFER_PITCH(uint32_t val) { - return ((val >> 5) << A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT) & A5XX_GRAS_LRZ_BUFFER_PITCH__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A5XX_GRAS_LRZ_BUFFER_PITCH__SHIFT) & A5XX_GRAS_LRZ_BUFFER_PITCH__MASK; } #define REG_A5XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO 0x0000e104 @@ -3124,13 +2971,15 @@ static inline uint32_t A5XX_GRAS_LRZ_BUFFER_PITCH(uint32_t val) #define A5XX_RB_CNTL_WIDTH__SHIFT 0 static inline uint32_t A5XX_RB_CNTL_WIDTH(uint32_t val) { - return ((val >> 5) << A5XX_RB_CNTL_WIDTH__SHIFT) & A5XX_RB_CNTL_WIDTH__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A5XX_RB_CNTL_WIDTH__SHIFT) & A5XX_RB_CNTL_WIDTH__MASK; } #define A5XX_RB_CNTL_HEIGHT__MASK 0x0001fe00 #define A5XX_RB_CNTL_HEIGHT__SHIFT 9 static inline uint32_t A5XX_RB_CNTL_HEIGHT(uint32_t val) { - return ((val >> 5) << A5XX_RB_CNTL_HEIGHT__SHIFT) & A5XX_RB_CNTL_HEIGHT__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A5XX_RB_CNTL_HEIGHT__SHIFT) & A5XX_RB_CNTL_HEIGHT__MASK; } #define A5XX_RB_CNTL_BYPASS 0x00020000 @@ -3248,7 +3097,7 @@ static inline uint32_t A5XX_RB_RENDER_COMPONENTS_RT7(uint32_t val) return ((val) << A5XX_RB_RENDER_COMPONENTS_RT7__SHIFT) & A5XX_RB_RENDER_COMPONENTS_RT7__MASK; } -static inline uint32_t REG_A5XX_RB_MRT(uint32_t i0) { return 0x0000e150 + 0x7*i0; } +#define REG_A5XX_RB_MRT(i0) (0x0000e150 + 0x7*(i0)) static inline uint32_t REG_A5XX_RB_MRT_CONTROL(uint32_t i0) { return 0x0000e150 + 0x7*i0; } #define A5XX_RB_MRT_CONTROL_BLEND 0x00000001 @@ -3337,7 +3186,8 @@ static inline uint32_t REG_A5XX_RB_MRT_PITCH(uint32_t i0) { return 0x0000e153 + #define A5XX_RB_MRT_PITCH__SHIFT 0 static inline uint32_t A5XX_RB_MRT_PITCH(uint32_t val) { - return ((val >> 6) << A5XX_RB_MRT_PITCH__SHIFT) & A5XX_RB_MRT_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A5XX_RB_MRT_PITCH__SHIFT) & A5XX_RB_MRT_PITCH__MASK; } static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x0000e154 + 0x7*i0; } @@ -3345,7 +3195,8 @@ static inline uint32_t REG_A5XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x0000e #define A5XX_RB_MRT_ARRAY_PITCH__SHIFT 0 static inline uint32_t A5XX_RB_MRT_ARRAY_PITCH(uint32_t val) { - return ((val >> 6) << A5XX_RB_MRT_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_ARRAY_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A5XX_RB_MRT_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_ARRAY_PITCH__MASK; } static inline uint32_t REG_A5XX_RB_MRT_BASE_LO(uint32_t i0) { return 0x0000e155 + 0x7*i0; } @@ -3527,7 +3378,8 @@ static inline uint32_t A5XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a5xx_depth_fo #define A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0 static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) { - return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A5XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_PITCH__MASK; } #define REG_A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x0000e1b6 @@ -3535,7 +3387,8 @@ static inline uint32_t A5XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) #define A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0 static inline uint32_t A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) { - return ((val >> 6) << A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; } #define REG_A5XX_RB_STENCIL_CONTROL 0x0000e1c0 @@ -3603,7 +3456,8 @@ static inline uint32_t A5XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op v #define A5XX_RB_STENCIL_PITCH__SHIFT 0 static inline uint32_t A5XX_RB_STENCIL_PITCH(uint32_t val) { - return ((val >> 6) << A5XX_RB_STENCIL_PITCH__SHIFT) & A5XX_RB_STENCIL_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A5XX_RB_STENCIL_PITCH__SHIFT) & A5XX_RB_STENCIL_PITCH__MASK; } #define REG_A5XX_RB_STENCIL_ARRAY_PITCH 0x0000e1c5 @@ -3611,7 +3465,8 @@ static inline uint32_t A5XX_RB_STENCIL_PITCH(uint32_t val) #define A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT 0 static inline uint32_t A5XX_RB_STENCIL_ARRAY_PITCH(uint32_t val) { - return ((val >> 6) << A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT) & A5XX_RB_STENCIL_ARRAY_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A5XX_RB_STENCIL_ARRAY_PITCH__SHIFT) & A5XX_RB_STENCIL_ARRAY_PITCH__MASK; } #define REG_A5XX_RB_STENCILREFMASK 0x0000e1c6 @@ -3722,7 +3577,8 @@ static inline uint32_t A5XX_RB_RESOLVE_CNTL_2_Y(uint32_t val) #define A5XX_RB_BLIT_DST_PITCH__SHIFT 0 static inline uint32_t A5XX_RB_BLIT_DST_PITCH(uint32_t val) { - return ((val >> 6) << A5XX_RB_BLIT_DST_PITCH__SHIFT) & A5XX_RB_BLIT_DST_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A5XX_RB_BLIT_DST_PITCH__SHIFT) & A5XX_RB_BLIT_DST_PITCH__MASK; } #define REG_A5XX_RB_BLIT_DST_ARRAY_PITCH 0x0000e217 @@ -3730,7 +3586,8 @@ static inline uint32_t A5XX_RB_BLIT_DST_PITCH(uint32_t val) #define A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0 static inline uint32_t A5XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) { - return ((val >> 6) << A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A5XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_DST_ARRAY_PITCH__MASK; } #define REG_A5XX_RB_CLEAR_COLOR_DW0 0x0000e218 @@ -3757,7 +3614,7 @@ static inline uint32_t A5XX_RB_CLEAR_CNTL_MASK(uint32_t val) #define REG_A5XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x0000e242 -static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x0000e243 + 0x4*i0; } +#define REG_A5XX_RB_MRT_FLAG_BUFFER(i0) (0x0000e243 + 0x4*(i0)) static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ADDR_LO(uint32_t i0) { return 0x0000e243 + 0x4*i0; } @@ -3768,7 +3625,8 @@ static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0 #define A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT 0 static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t val) { - return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A5XX_RB_MRT_FLAG_BUFFER_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_PITCH__MASK; } static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0) { return 0x0000e246 + 0x4*i0; } @@ -3776,7 +3634,8 @@ static inline uint32_t REG_A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t i0) { re #define A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0 static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) { - return ((val >> 6) << A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH__MASK; } #define REG_A5XX_RB_BLIT_FLAG_DST_LO 0x0000e263 @@ -3788,7 +3647,8 @@ static inline uint32_t A5XX_RB_MRT_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) #define A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT 0 static inline uint32_t A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val) { - return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A5XX_RB_BLIT_FLAG_DST_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_PITCH__MASK; } #define REG_A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH 0x0000e266 @@ -3796,7 +3656,8 @@ static inline uint32_t A5XX_RB_BLIT_FLAG_DST_PITCH(uint32_t val) #define A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT 0 static inline uint32_t A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH(uint32_t val) { - return ((val >> 6) << A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__SHIFT) & A5XX_RB_BLIT_FLAG_DST_ARRAY_PITCH__MASK; } #define REG_A5XX_RB_SAMPLE_COUNT_ADDR_LO 0x0000e267 @@ -3812,11 +3673,11 @@ static inline uint32_t A5XX_VPC_CNTL_0_STRIDE_IN_VPC(uint32_t val) } #define A5XX_VPC_CNTL_0_VARYING 0x00000800 -static inline uint32_t REG_A5XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x0000e282 + 0x1*i0; } +#define REG_A5XX_VPC_VARYING_INTERP(i0) (0x0000e282 + 0x1*(i0)) static inline uint32_t REG_A5XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x0000e282 + 0x1*i0; } -static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x0000e28a + 0x1*i0; } +#define REG_A5XX_VPC_VARYING_PS_REPL(i0) (0x0000e28a + 0x1*(i0)) static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x0000e28a + 0x1*i0; } @@ -3824,7 +3685,7 @@ static inline uint32_t REG_A5XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0 #define REG_A5XX_UNKNOWN_E293 0x0000e293 -static inline uint32_t REG_A5XX_VPC_VAR(uint32_t i0) { return 0x0000e294 + 0x1*i0; } +#define REG_A5XX_VPC_VAR(i0) (0x0000e294 + 0x1*(i0)) static inline uint32_t REG_A5XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x0000e294 + 0x1*i0; } @@ -3890,7 +3751,8 @@ static inline uint32_t A5XX_VPC_SO_PROG_A_BUF(uint32_t val) #define A5XX_VPC_SO_PROG_A_OFF__SHIFT 2 static inline uint32_t A5XX_VPC_SO_PROG_A_OFF(uint32_t val) { - return ((val >> 2) << A5XX_VPC_SO_PROG_A_OFF__SHIFT) & A5XX_VPC_SO_PROG_A_OFF__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A5XX_VPC_SO_PROG_A_OFF__SHIFT) & A5XX_VPC_SO_PROG_A_OFF__MASK; } #define A5XX_VPC_SO_PROG_A_EN 0x00000800 #define A5XX_VPC_SO_PROG_B_BUF__MASK 0x00003000 @@ -3903,11 +3765,12 @@ static inline uint32_t A5XX_VPC_SO_PROG_B_BUF(uint32_t val) #define A5XX_VPC_SO_PROG_B_OFF__SHIFT 14 static inline uint32_t A5XX_VPC_SO_PROG_B_OFF(uint32_t val) { - return ((val >> 2) << A5XX_VPC_SO_PROG_B_OFF__SHIFT) & A5XX_VPC_SO_PROG_B_OFF__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A5XX_VPC_SO_PROG_B_OFF__SHIFT) & A5XX_VPC_SO_PROG_B_OFF__MASK; } #define A5XX_VPC_SO_PROG_B_EN 0x00800000 -static inline uint32_t REG_A5XX_VPC_SO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; } +#define REG_A5XX_VPC_SO(i0) (0x0000e2a7 + 0x7*(i0)) static inline uint32_t REG_A5XX_VPC_SO_BUFFER_BASE_LO(uint32_t i0) { return 0x0000e2a7 + 0x7*i0; } @@ -4066,7 +3929,7 @@ static inline uint32_t A5XX_VFD_CONTROL_3_REGID_TESSY(uint32_t val) #define REG_A5XX_VFD_INSTANCE_START_OFFSET 0x0000e409 -static inline uint32_t REG_A5XX_VFD_FETCH(uint32_t i0) { return 0x0000e40a + 0x4*i0; } +#define REG_A5XX_VFD_FETCH(i0) (0x0000e40a + 0x4*(i0)) static inline uint32_t REG_A5XX_VFD_FETCH_BASE_LO(uint32_t i0) { return 0x0000e40a + 0x4*i0; } @@ -4076,7 +3939,7 @@ static inline uint32_t REG_A5XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000e40c static inline uint32_t REG_A5XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000e40d + 0x4*i0; } -static inline uint32_t REG_A5XX_VFD_DECODE(uint32_t i0) { return 0x0000e48a + 0x2*i0; } +#define REG_A5XX_VFD_DECODE(i0) (0x0000e48a + 0x2*(i0)) static inline uint32_t REG_A5XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000e48a + 0x2*i0; } #define A5XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f @@ -4103,7 +3966,7 @@ static inline uint32_t A5XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) static inline uint32_t REG_A5XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000e48b + 0x2*i0; } -static inline uint32_t REG_A5XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000e4ca + 0x1*i0; } +#define REG_A5XX_VFD_DEST_CNTL(i0) (0x0000e4ca + 0x1*(i0)) static inline uint32_t REG_A5XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000e4ca + 0x1*i0; } #define A5XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f @@ -4254,7 +4117,7 @@ static inline uint32_t A5XX_SP_PRIMITIVE_CNTL_VSOUT(uint32_t val) return ((val) << A5XX_SP_PRIMITIVE_CNTL_VSOUT__SHIFT) & A5XX_SP_PRIMITIVE_CNTL_VSOUT__MASK; } -static inline uint32_t REG_A5XX_SP_VS_OUT(uint32_t i0) { return 0x0000e593 + 0x1*i0; } +#define REG_A5XX_SP_VS_OUT(i0) (0x0000e593 + 0x1*(i0)) static inline uint32_t REG_A5XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000e593 + 0x1*i0; } #define A5XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff @@ -4282,7 +4145,7 @@ static inline uint32_t A5XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) return ((val) << A5XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A5XX_SP_VS_OUT_REG_B_COMPMASK__MASK; } -static inline uint32_t REG_A5XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; } +#define REG_A5XX_SP_VS_VPC_DST(i0) (0x0000e5a3 + 0x1*(i0)) static inline uint32_t REG_A5XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000e5a3 + 0x1*i0; } #define A5XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff @@ -4316,6 +4179,39 @@ static inline uint32_t A5XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) #define REG_A5XX_SP_VS_OBJ_START_HI 0x0000e5ad +#define REG_A5XX_SP_VS_PVT_MEM_PARAM 0x0000e5ae +#define A5XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff +#define A5XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 +static inline uint32_t A5XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) +{ + assert(!(val & 0x1ff)); + return (((val >> 9)) << A5XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A5XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; +} +#define A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK 0x00ffff00 +#define A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT 8 +static inline uint32_t A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val) +{ + assert(!(val & 0x7ff)); + return (((val >> 11)) << A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT) & A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK; +} +#define A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 +#define A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 +static inline uint32_t A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) +{ + return ((val) << A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A5XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; +} + +#define REG_A5XX_SP_VS_PVT_MEM_ADDR 0x0000e5af + +#define REG_A5XX_SP_VS_PVT_MEM_SIZE 0x0000e5b1 +#define A5XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff +#define A5XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 +static inline uint32_t A5XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) +{ + assert(!(val & 0xfff)); + return (((val >> 12)) << A5XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A5XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; +} + #define REG_A5XX_SP_FS_CTRL_REG0 0x0000e5c0 #define A5XX_SP_FS_CTRL_REG0_BUFFER 0x00000004 #define A5XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00000008 @@ -4351,6 +4247,39 @@ static inline uint32_t A5XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) #define REG_A5XX_SP_FS_OBJ_START_HI 0x0000e5c4 +#define REG_A5XX_SP_FS_PVT_MEM_PARAM 0x0000e5c5 +#define A5XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff +#define A5XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 +static inline uint32_t A5XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) +{ + assert(!(val & 0x1ff)); + return (((val >> 9)) << A5XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A5XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; +} +#define A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK 0x00ffff00 +#define A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT 8 +static inline uint32_t A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val) +{ + assert(!(val & 0x7ff)); + return (((val >> 11)) << A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT) & A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK; +} +#define A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 +#define A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 +static inline uint32_t A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) +{ + return ((val) << A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A5XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; +} + +#define REG_A5XX_SP_FS_PVT_MEM_ADDR 0x0000e5c6 + +#define REG_A5XX_SP_FS_PVT_MEM_SIZE 0x0000e5c8 +#define A5XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff +#define A5XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 +static inline uint32_t A5XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) +{ + assert(!(val & 0xfff)); + return (((val >> 12)) << A5XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A5XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; +} + #define REG_A5XX_SP_BLEND_CNTL 0x0000e5c9 #define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__MASK 0x000000ff #define A5XX_SP_BLEND_CNTL_ENABLE_BLEND__SHIFT 0 @@ -4381,7 +4310,7 @@ static inline uint32_t A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID(uint32_t val) return ((val) << A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__SHIFT) & A5XX_SP_FS_OUTPUT_CNTL_SAMPLEMASK_REGID__MASK; } -static inline uint32_t REG_A5XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000e5cb + 0x1*i0; } +#define REG_A5XX_SP_FS_OUTPUT(i0) (0x0000e5cb + 0x1*(i0)) static inline uint32_t REG_A5XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000e5cb + 0x1*i0; } #define A5XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff @@ -4392,7 +4321,7 @@ static inline uint32_t A5XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) } #define A5XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100 -static inline uint32_t REG_A5XX_SP_FS_MRT(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; } +#define REG_A5XX_SP_FS_MRT(i0) (0x0000e5d3 + 0x1*(i0)) static inline uint32_t REG_A5XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000e5d3 + 0x1*i0; } #define A5XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff @@ -4442,6 +4371,39 @@ static inline uint32_t A5XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) #define REG_A5XX_SP_CS_OBJ_START_HI 0x0000e5f4 +#define REG_A5XX_SP_CS_PVT_MEM_PARAM 0x0000e5f5 +#define A5XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff +#define A5XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 +static inline uint32_t A5XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) +{ + assert(!(val & 0x1ff)); + return (((val >> 9)) << A5XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A5XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; +} +#define A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK 0x00ffff00 +#define A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT 8 +static inline uint32_t A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val) +{ + assert(!(val & 0x7ff)); + return (((val >> 11)) << A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT) & A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK; +} +#define A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 +#define A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 +static inline uint32_t A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) +{ + return ((val) << A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A5XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; +} + +#define REG_A5XX_SP_CS_PVT_MEM_ADDR 0x0000e5f6 + +#define REG_A5XX_SP_CS_PVT_MEM_SIZE 0x0000e5f8 +#define A5XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff +#define A5XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 +static inline uint32_t A5XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) +{ + assert(!(val & 0xfff)); + return (((val >> 12)) << A5XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A5XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; +} + #define REG_A5XX_SP_HS_CTRL_REG0 0x0000e600 #define A5XX_SP_HS_CTRL_REG0_BUFFER 0x00000004 #define A5XX_SP_HS_CTRL_REG0_THREADSIZE__MASK 0x00000008 @@ -4477,6 +4439,39 @@ static inline uint32_t A5XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) #define REG_A5XX_SP_HS_OBJ_START_HI 0x0000e604 +#define REG_A5XX_SP_HS_PVT_MEM_PARAM 0x0000e605 +#define A5XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff +#define A5XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 +static inline uint32_t A5XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) +{ + assert(!(val & 0x1ff)); + return (((val >> 9)) << A5XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A5XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; +} +#define A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK 0x00ffff00 +#define A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT 8 +static inline uint32_t A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val) +{ + assert(!(val & 0x7ff)); + return (((val >> 11)) << A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT) & A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK; +} +#define A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 +#define A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 +static inline uint32_t A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) +{ + return ((val) << A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A5XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; +} + +#define REG_A5XX_SP_HS_PVT_MEM_ADDR 0x0000e606 + +#define REG_A5XX_SP_HS_PVT_MEM_SIZE 0x0000e608 +#define A5XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff +#define A5XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 +static inline uint32_t A5XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) +{ + assert(!(val & 0xfff)); + return (((val >> 12)) << A5XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A5XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; +} + #define REG_A5XX_SP_DS_CTRL_REG0 0x0000e610 #define A5XX_SP_DS_CTRL_REG0_BUFFER 0x00000004 #define A5XX_SP_DS_CTRL_REG0_THREADSIZE__MASK 0x00000008 @@ -4512,6 +4507,39 @@ static inline uint32_t A5XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val) #define REG_A5XX_SP_DS_OBJ_START_HI 0x0000e62d +#define REG_A5XX_SP_DS_PVT_MEM_PARAM 0x0000e62e +#define A5XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff +#define A5XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 +static inline uint32_t A5XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) +{ + assert(!(val & 0x1ff)); + return (((val >> 9)) << A5XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A5XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; +} +#define A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK 0x00ffff00 +#define A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT 8 +static inline uint32_t A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val) +{ + assert(!(val & 0x7ff)); + return (((val >> 11)) << A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT) & A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK; +} +#define A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 +#define A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 +static inline uint32_t A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) +{ + return ((val) << A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A5XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; +} + +#define REG_A5XX_SP_DS_PVT_MEM_ADDR 0x0000e62f + +#define REG_A5XX_SP_DS_PVT_MEM_SIZE 0x0000e631 +#define A5XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff +#define A5XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 +static inline uint32_t A5XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) +{ + assert(!(val & 0xfff)); + return (((val >> 12)) << A5XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A5XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; +} + #define REG_A5XX_SP_GS_CTRL_REG0 0x0000e640 #define A5XX_SP_GS_CTRL_REG0_BUFFER 0x00000004 #define A5XX_SP_GS_CTRL_REG0_THREADSIZE__MASK 0x00000008 @@ -4547,6 +4575,39 @@ static inline uint32_t A5XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val) #define REG_A5XX_SP_GS_OBJ_START_HI 0x0000e65d +#define REG_A5XX_SP_GS_PVT_MEM_PARAM 0x0000e65e +#define A5XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff +#define A5XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 +static inline uint32_t A5XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) +{ + assert(!(val & 0x1ff)); + return (((val >> 9)) << A5XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A5XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; +} +#define A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK 0x00ffff00 +#define A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT 8 +static inline uint32_t A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKOFFSET(uint32_t val) +{ + assert(!(val & 0x7ff)); + return (((val >> 11)) << A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKOFFSET__SHIFT) & A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKOFFSET__MASK; +} +#define A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 +#define A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 +static inline uint32_t A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t val) +{ + return ((val) << A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT) & A5XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK; +} + +#define REG_A5XX_SP_GS_PVT_MEM_ADDR 0x0000e65f + +#define REG_A5XX_SP_GS_PVT_MEM_SIZE 0x0000e661 +#define A5XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff +#define A5XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 +static inline uint32_t A5XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) +{ + assert(!(val & 0xfff)); + return (((val >> 12)) << A5XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A5XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; +} + #define REG_A5XX_TPL1_TP_RAS_MSAA_CNTL 0x0000e704 #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 #define A5XX_TPL1_TP_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 @@ -5061,13 +5122,15 @@ static inline uint32_t A5XX_RB_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) #define A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT 0 static inline uint32_t A5XX_RB_2D_SRC_SIZE_PITCH(uint32_t val) { - return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A5XX_RB_2D_SRC_SIZE_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_PITCH__MASK; } #define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK 0xffff0000 #define A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT 16 static inline uint32_t A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH(uint32_t val) { - return ((val >> 6) << A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_SRC_SIZE_ARRAY_PITCH__MASK; } #define REG_A5XX_RB_2D_DST_INFO 0x00002110 @@ -5101,13 +5164,15 @@ static inline uint32_t A5XX_RB_2D_DST_INFO_COLOR_SWAP(enum a3xx_color_swap val) #define A5XX_RB_2D_DST_SIZE_PITCH__SHIFT 0 static inline uint32_t A5XX_RB_2D_DST_SIZE_PITCH(uint32_t val) { - return ((val >> 6) << A5XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A5XX_RB_2D_DST_SIZE_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_PITCH__MASK; } #define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK 0xffff0000 #define A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT 16 static inline uint32_t A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val) { - return ((val >> 6) << A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__SHIFT) & A5XX_RB_2D_DST_SIZE_ARRAY_PITCH__MASK; } #define REG_A5XX_RB_2D_SRC_FLAGS_LO 0x00002140 @@ -5119,7 +5184,8 @@ static inline uint32_t A5XX_RB_2D_DST_SIZE_ARRAY_PITCH(uint32_t val) #define A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT 0 static inline uint32_t A5XX_RB_2D_SRC_FLAGS_PITCH(uint32_t val) { - return ((val >> 6) << A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT) & A5XX_RB_2D_SRC_FLAGS_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A5XX_RB_2D_SRC_FLAGS_PITCH__SHIFT) & A5XX_RB_2D_SRC_FLAGS_PITCH__MASK; } #define REG_A5XX_RB_2D_DST_FLAGS_LO 0x00002143 @@ -5131,7 +5197,8 @@ static inline uint32_t A5XX_RB_2D_SRC_FLAGS_PITCH(uint32_t val) #define A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT 0 static inline uint32_t A5XX_RB_2D_DST_FLAGS_PITCH(uint32_t val) { - return ((val >> 6) << A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A5XX_RB_2D_DST_FLAGS_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A5XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A5XX_RB_2D_DST_FLAGS_PITCH__MASK; } #define REG_A5XX_GRAS_2D_BLIT_CNTL 0x00002180 @@ -5357,13 +5424,15 @@ static inline uint32_t A5XX_TEX_CONST_2_TYPE(enum a5xx_tex_type val) #define A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0 static inline uint32_t A5XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) { - return ((val >> 12) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A5XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A5XX_TEX_CONST_3_ARRAY_PITCH__MASK; } #define A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000 #define A5XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23 static inline uint32_t A5XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val) { - return ((val >> 12) << A5XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A5XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A5XX_TEX_CONST_3_MIN_LAYERSZ__MASK; } #define A5XX_TEX_CONST_3_TILE_ALL 0x08000000 #define A5XX_TEX_CONST_3_FLAG 0x10000000 @@ -5373,7 +5442,8 @@ static inline uint32_t A5XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val) #define A5XX_TEX_CONST_4_BASE_LO__SHIFT 5 static inline uint32_t A5XX_TEX_CONST_4_BASE_LO(uint32_t val) { - return ((val >> 5) << A5XX_TEX_CONST_4_BASE_LO__SHIFT) & A5XX_TEX_CONST_4_BASE_LO__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A5XX_TEX_CONST_4_BASE_LO__SHIFT) & A5XX_TEX_CONST_4_BASE_LO__MASK; } #define REG_A5XX_TEX_CONST_5 0x00000005 @@ -5407,7 +5477,8 @@ static inline uint32_t A5XX_TEX_CONST_5_DEPTH(uint32_t val) #define A5XX_SSBO_0_0_BASE_LO__SHIFT 5 static inline uint32_t A5XX_SSBO_0_0_BASE_LO(uint32_t val) { - return ((val >> 5) << A5XX_SSBO_0_0_BASE_LO__SHIFT) & A5XX_SSBO_0_0_BASE_LO__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A5XX_SSBO_0_0_BASE_LO__SHIFT) & A5XX_SSBO_0_0_BASE_LO__MASK; } #define REG_A5XX_SSBO_0_1 0x00000001 @@ -5423,7 +5494,8 @@ static inline uint32_t A5XX_SSBO_0_1_PITCH(uint32_t val) #define A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT 12 static inline uint32_t A5XX_SSBO_0_2_ARRAY_PITCH(uint32_t val) { - return ((val >> 12) << A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A5XX_SSBO_0_2_ARRAY_PITCH__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A5XX_SSBO_0_2_ARRAY_PITCH__SHIFT) & A5XX_SSBO_0_2_ARRAY_PITCH__MASK; } #define REG_A5XX_SSBO_0_3 0x00000003 @@ -5494,5 +5566,7 @@ static inline uint32_t A5XX_UBO_1_BASE_HI(uint32_t val) return ((val) << A5XX_UBO_1_BASE_HI__SHIFT) & A5XX_UBO_1_BASE_HI__MASK; } +#ifdef __cplusplus +#endif #endif /* A5XX_XML */ diff --git a/drivers/gpu/drm/msm/adreno/a6xx.xml.h b/drivers/gpu/drm/msm/adreno/a6xx.xml.h index 863b5e3b0e67..92e23bf2458d 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx.xml.h @@ -3,28 +3,20 @@ /* Autogenerated file, DO NOT EDIT manually! -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://github.com/freedreno/envytools/ -git clone https://github.com/freedreno/envytools.git +This file was generated by the rules-ng-ng gen_header.py tool in this git repository: +http://gitlab.freedesktop.org/mesa/mesa/ +git clone https://gitlab.freedesktop.org/mesa/mesa.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2023-03-10 18:32:52) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 91929 bytes, from 2023-02-28 23:52:27) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from 2023-03-10 18:32:53) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 74995 bytes, from 2023-03-20 18:06:23) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113474 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149590 bytes, from 2023-02-14 19:37:12) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 198949 bytes, from 2023-03-20 18:06:23) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11404 bytes, from 2023-03-10 18:32:53) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 9055 bytes, from 2023-03-10 18:32:52) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2976 bytes, from 2023-03-10 18:32:52) - -Copyright (C) 2013-2023 by the following authors: -- Rob Clark <robdclark@gmail.com> (robclark) -- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) + +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 243381 bytes, from Sat Feb 24 09:06:40 2024) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from Fri Jun 2 14:59:26 2023) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 85856 bytes, from Fri Feb 23 13:07:00 2024) + +Copyright (C) 2013-2024 by the following authors: +- Rob Clark <robdclark@gmail.com> Rob Clark +- Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the @@ -45,8 +37,21 @@ IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifdef __KERNEL__ +#include <linux/bug.h> +#define assert(x) BUG_ON(!(x)) +#else +#include <assert.h> +#endif + +#ifdef __cplusplus +#define __struct_cast(X) +#else +#define __struct_cast(X) (struct X) +#endif enum a6xx_tile_mode { TILE6_LINEAR = 0, @@ -246,6 +251,85 @@ enum a6xx_shader_id { A6XX_HLSQ_INST_RAM_1 = 115, }; +enum a7xx_statetype_id { + A7XX_TP0_NCTX_REG = 0, + A7XX_TP0_CTX0_3D_CVS_REG = 1, + A7XX_TP0_CTX0_3D_CPS_REG = 2, + A7XX_TP0_CTX1_3D_CVS_REG = 3, + A7XX_TP0_CTX1_3D_CPS_REG = 4, + A7XX_TP0_CTX2_3D_CPS_REG = 5, + A7XX_TP0_CTX3_3D_CPS_REG = 6, + A7XX_TP0_TMO_DATA = 9, + A7XX_TP0_SMO_DATA = 10, + A7XX_TP0_MIPMAP_BASE_DATA = 11, + A7XX_SP_NCTX_REG = 32, + A7XX_SP_CTX0_3D_CVS_REG = 33, + A7XX_SP_CTX0_3D_CPS_REG = 34, + A7XX_SP_CTX1_3D_CVS_REG = 35, + A7XX_SP_CTX1_3D_CPS_REG = 36, + A7XX_SP_CTX2_3D_CPS_REG = 37, + A7XX_SP_CTX3_3D_CPS_REG = 38, + A7XX_SP_INST_DATA = 39, + A7XX_SP_INST_DATA_1 = 40, + A7XX_SP_LB_0_DATA = 41, + A7XX_SP_LB_1_DATA = 42, + A7XX_SP_LB_2_DATA = 43, + A7XX_SP_LB_3_DATA = 44, + A7XX_SP_LB_4_DATA = 45, + A7XX_SP_LB_5_DATA = 46, + A7XX_SP_LB_6_DATA = 47, + A7XX_SP_LB_7_DATA = 48, + A7XX_SP_CB_RAM = 49, + A7XX_SP_LB_13_DATA = 50, + A7XX_SP_LB_14_DATA = 51, + A7XX_SP_INST_TAG = 52, + A7XX_SP_INST_DATA_2 = 53, + A7XX_SP_TMO_TAG = 54, + A7XX_SP_SMO_TAG = 55, + A7XX_SP_STATE_DATA = 56, + A7XX_SP_HWAVE_RAM = 57, + A7XX_SP_L0_INST_BUF = 58, + A7XX_SP_LB_8_DATA = 59, + A7XX_SP_LB_9_DATA = 60, + A7XX_SP_LB_10_DATA = 61, + A7XX_SP_LB_11_DATA = 62, + A7XX_SP_LB_12_DATA = 63, + A7XX_HLSQ_DATAPATH_DSTR_META = 64, + A7XX_HLSQ_L2STC_TAG_RAM = 67, + A7XX_HLSQ_L2STC_INFO_CMD = 68, + A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG = 69, + A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG = 70, + A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM = 71, + A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM = 72, + A7XX_HLSQ_CHUNK_CVS_RAM = 73, + A7XX_HLSQ_CHUNK_CPS_RAM = 74, + A7XX_HLSQ_CHUNK_CVS_RAM_TAG = 75, + A7XX_HLSQ_CHUNK_CPS_RAM_TAG = 76, + A7XX_HLSQ_ICB_CVS_CB_BASE_TAG = 77, + A7XX_HLSQ_ICB_CPS_CB_BASE_TAG = 78, + A7XX_HLSQ_CVS_MISC_RAM = 79, + A7XX_HLSQ_CPS_MISC_RAM = 80, + A7XX_HLSQ_CPS_MISC_RAM_1 = 81, + A7XX_HLSQ_INST_RAM = 82, + A7XX_HLSQ_GFX_CVS_CONST_RAM = 83, + A7XX_HLSQ_GFX_CPS_CONST_RAM = 84, + A7XX_HLSQ_CVS_MISC_RAM_TAG = 85, + A7XX_HLSQ_CPS_MISC_RAM_TAG = 86, + A7XX_HLSQ_INST_RAM_TAG = 87, + A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG = 88, + A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG = 89, + A7XX_HLSQ_GFX_LOCAL_MISC_RAM = 90, + A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG = 91, + A7XX_HLSQ_INST_RAM_1 = 92, + A7XX_HLSQ_STPROC_META = 93, + A7XX_HLSQ_BV_BE_META = 94, + A7XX_HLSQ_INST_RAM_2 = 95, + A7XX_HLSQ_DATAPATH_META = 96, + A7XX_HLSQ_FRONTEND_META = 97, + A7XX_HLSQ_INDIRECT_META = 98, + A7XX_HLSQ_BACKEND_META = 99, +}; + enum a6xx_debugbus_id { A6XX_DBGBUS_CP = 1, A6XX_DBGBUS_RBBM = 2, @@ -305,6 +389,140 @@ enum a6xx_debugbus_id { A6XX_DBGBUS_SPTP_5 = 93, }; +enum a7xx_state_location { + A7XX_HLSQ_STATE = 0, + A7XX_HLSQ_DP = 1, + A7XX_SP_TOP = 2, + A7XX_USPTP = 3, +}; + +enum a7xx_pipe { + A7XX_PIPE_NONE = 0, + A7XX_PIPE_BR = 1, + A7XX_PIPE_BV = 2, + A7XX_PIPE_LPAC = 3, +}; + +enum a7xx_cluster { + A7XX_CLUSTER_NONE = 0, + A7XX_CLUSTER_FE = 1, + A7XX_CLUSTER_SP_VS = 2, + A7XX_CLUSTER_PC_VS = 3, + A7XX_CLUSTER_GRAS = 4, + A7XX_CLUSTER_SP_PS = 5, + A7XX_CLUSTER_VPC_PS = 6, + A7XX_CLUSTER_PS = 7, +}; + +enum a7xx_debugbus_id { + A7XX_DBGBUS_CP_0_0 = 1, + A7XX_DBGBUS_CP_0_1 = 2, + A7XX_DBGBUS_RBBM = 3, + A7XX_DBGBUS_GBIF_GX = 5, + A7XX_DBGBUS_GBIF_CX = 6, + A7XX_DBGBUS_HLSQ = 7, + A7XX_DBGBUS_UCHE_0 = 9, + A7XX_DBGBUS_UCHE_1 = 10, + A7XX_DBGBUS_TESS_BR = 13, + A7XX_DBGBUS_TESS_BV = 14, + A7XX_DBGBUS_PC_BR = 17, + A7XX_DBGBUS_PC_BV = 18, + A7XX_DBGBUS_VFDP_BR = 21, + A7XX_DBGBUS_VFDP_BV = 22, + A7XX_DBGBUS_VPC_BR = 25, + A7XX_DBGBUS_VPC_BV = 26, + A7XX_DBGBUS_TSE_BR = 29, + A7XX_DBGBUS_TSE_BV = 30, + A7XX_DBGBUS_RAS_BR = 33, + A7XX_DBGBUS_RAS_BV = 34, + A7XX_DBGBUS_VSC = 37, + A7XX_DBGBUS_COM_0 = 39, + A7XX_DBGBUS_LRZ_BR = 43, + A7XX_DBGBUS_LRZ_BV = 44, + A7XX_DBGBUS_UFC_0 = 47, + A7XX_DBGBUS_UFC_1 = 48, + A7XX_DBGBUS_GMU_GX = 55, + A7XX_DBGBUS_DBGC = 59, + A7XX_DBGBUS_CX = 60, + A7XX_DBGBUS_GMU_CX = 61, + A7XX_DBGBUS_GPC_BR = 62, + A7XX_DBGBUS_GPC_BV = 63, + A7XX_DBGBUS_LARC = 66, + A7XX_DBGBUS_HLSQ_SPTP = 68, + A7XX_DBGBUS_RB_0 = 70, + A7XX_DBGBUS_RB_1 = 71, + A7XX_DBGBUS_RB_2 = 72, + A7XX_DBGBUS_RB_3 = 73, + A7XX_DBGBUS_RB_4 = 74, + A7XX_DBGBUS_RB_5 = 75, + A7XX_DBGBUS_UCHE_WRAPPER = 102, + A7XX_DBGBUS_CCU_0 = 106, + A7XX_DBGBUS_CCU_1 = 107, + A7XX_DBGBUS_CCU_2 = 108, + A7XX_DBGBUS_CCU_3 = 109, + A7XX_DBGBUS_CCU_4 = 110, + A7XX_DBGBUS_CCU_5 = 111, + A7XX_DBGBUS_VFD_BR_0 = 138, + A7XX_DBGBUS_VFD_BR_1 = 139, + A7XX_DBGBUS_VFD_BR_2 = 140, + A7XX_DBGBUS_VFD_BR_3 = 141, + A7XX_DBGBUS_VFD_BR_4 = 142, + A7XX_DBGBUS_VFD_BR_5 = 143, + A7XX_DBGBUS_VFD_BR_6 = 144, + A7XX_DBGBUS_VFD_BR_7 = 145, + A7XX_DBGBUS_VFD_BV_0 = 202, + A7XX_DBGBUS_VFD_BV_1 = 203, + A7XX_DBGBUS_VFD_BV_2 = 204, + A7XX_DBGBUS_VFD_BV_3 = 205, + A7XX_DBGBUS_USP_0 = 234, + A7XX_DBGBUS_USP_1 = 235, + A7XX_DBGBUS_USP_2 = 236, + A7XX_DBGBUS_USP_3 = 237, + A7XX_DBGBUS_USP_4 = 238, + A7XX_DBGBUS_USP_5 = 239, + A7XX_DBGBUS_TP_0 = 266, + A7XX_DBGBUS_TP_1 = 267, + A7XX_DBGBUS_TP_2 = 268, + A7XX_DBGBUS_TP_3 = 269, + A7XX_DBGBUS_TP_4 = 270, + A7XX_DBGBUS_TP_5 = 271, + A7XX_DBGBUS_TP_6 = 272, + A7XX_DBGBUS_TP_7 = 273, + A7XX_DBGBUS_TP_8 = 274, + A7XX_DBGBUS_TP_9 = 275, + A7XX_DBGBUS_TP_10 = 276, + A7XX_DBGBUS_TP_11 = 277, + A7XX_DBGBUS_USPTP_0 = 330, + A7XX_DBGBUS_USPTP_1 = 331, + A7XX_DBGBUS_USPTP_2 = 332, + A7XX_DBGBUS_USPTP_3 = 333, + A7XX_DBGBUS_USPTP_4 = 334, + A7XX_DBGBUS_USPTP_5 = 335, + A7XX_DBGBUS_USPTP_6 = 336, + A7XX_DBGBUS_USPTP_7 = 337, + A7XX_DBGBUS_USPTP_8 = 338, + A7XX_DBGBUS_USPTP_9 = 339, + A7XX_DBGBUS_USPTP_10 = 340, + A7XX_DBGBUS_USPTP_11 = 341, + A7XX_DBGBUS_CCHE_0 = 396, + A7XX_DBGBUS_CCHE_1 = 397, + A7XX_DBGBUS_CCHE_2 = 398, + A7XX_DBGBUS_VPC_DSTR_0 = 408, + A7XX_DBGBUS_VPC_DSTR_1 = 409, + A7XX_DBGBUS_VPC_DSTR_2 = 410, + A7XX_DBGBUS_HLSQ_DP_STR_0 = 411, + A7XX_DBGBUS_HLSQ_DP_STR_1 = 412, + A7XX_DBGBUS_HLSQ_DP_STR_2 = 413, + A7XX_DBGBUS_HLSQ_DP_STR_3 = 414, + A7XX_DBGBUS_HLSQ_DP_STR_4 = 415, + A7XX_DBGBUS_HLSQ_DP_STR_5 = 416, + A7XX_DBGBUS_UFC_DSTR_0 = 443, + A7XX_DBGBUS_UFC_DSTR_1 = 444, + A7XX_DBGBUS_UFC_DSTR_2 = 445, + A7XX_DBGBUS_CGC_SUBCORE = 446, + A7XX_DBGBUS_CGC_CORE = 447, +}; + enum a6xx_cp_perfcounter_select { PERF_CP_ALWAYS_COUNT = 0, PERF_CP_BUSY_GFX_CORE_IDLE = 1, @@ -914,6 +1132,19 @@ enum a6xx_ztest_mode { A6XX_INVALID_ZTEST = 3, }; +enum a6xx_tess_spacing { + TESS_EQUAL = 0, + TESS_FRACTIONAL_ODD = 2, + TESS_FRACTIONAL_EVEN = 3, +}; + +enum a6xx_tess_output { + TESS_POINTS = 0, + TESS_LINES = 1, + TESS_CW_TRIS = 2, + TESS_CCW_TRIS = 3, +}; + enum a6xx_sequenced_thread_dist { DIST_SCREEN_COORD = 0, DIST_ALL_TO_RB0 = 1, @@ -967,17 +1198,25 @@ enum a6xx_rotation { ROTATE_VFLIP = 5, }; -enum a6xx_tess_spacing { - TESS_EQUAL = 0, - TESS_FRACTIONAL_ODD = 2, - TESS_FRACTIONAL_EVEN = 3, +enum a6xx_ccu_cache_size { + CCU_CACHE_SIZE_FULL = 0, + CCU_CACHE_SIZE_HALF = 1, + CCU_CACHE_SIZE_QUARTER = 2, + CCU_CACHE_SIZE_EIGHTH = 3, }; -enum a6xx_tess_output { - TESS_POINTS = 0, - TESS_LINES = 1, - TESS_CW_TRIS = 2, - TESS_CCW_TRIS = 3, +enum a6xx_varying_interp_mode { + INTERP_SMOOTH = 0, + INTERP_FLAT = 1, + INTERP_ZERO = 2, + INTERP_ONE = 3, +}; + +enum a6xx_varying_ps_repl_mode { + PS_REPL_NONE = 0, + PS_REPL_S = 1, + PS_REPL_T = 2, + PS_REPL_ONE_MINUS_T = 3, }; enum a6xx_threadsize { @@ -991,9 +1230,17 @@ enum a6xx_bindless_descriptor_size { }; enum a6xx_isam_mode { + ISAMMODE_CL = 1, ISAMMODE_GL = 2, }; +enum a7xx_cs_yalign { + CS_YALIGN_1 = 8, + CS_YALIGN_2 = 4, + CS_YALIGN_4 = 2, + CS_YALIGN_8 = 1, +}; + enum a6xx_tex_filter { A6XX_TEX_NEAREST = 0, A6XX_TEX_LINEAR = 1, @@ -1069,6 +1316,7 @@ enum a6xx_tex_type { #define A6XX_RBBM_INT_0_MASK_TSBWRITEERROR 0x10000000 #define A6XX_RBBM_INT_0_MASK_ISDB_CPU_IRQ 0x40000000 #define A6XX_RBBM_INT_0_MASK_ISDB_UNDER_DEBUG 0x80000000 + #define A6XX_CP_INT_CP_OPCODE_ERROR 0x00000001 #define A6XX_CP_INT_CP_UCODE_ERROR 0x00000002 #define A6XX_CP_INT_CP_HW_FAULT_ERROR 0x00000004 @@ -1086,6 +1334,7 @@ enum a6xx_tex_type { #define A6XX_CP_INT_CP_HW_FAULT_ERROR_BV 0x00008000 #define A6XX_CP_INT_CP_REGISTER_PROTECTION_ERROR_BV 0x00010000 #define A6XX_CP_INT_CP_ILLEGAL_INSTR_ERROR_BV 0x00020000 + #define REG_A6XX_CP_RB_BASE 0x00000800 #define REG_A6XX_CP_RB_CNTL 0x00000802 @@ -1104,7 +1353,6 @@ enum a6xx_tex_type { #define REG_A6XX_CP_HW_FAULT 0x00000821 #define REG_A6XX_CP_INTERRUPT_STATUS 0x00000823 - #define REG_A6XX_CP_PROTECT_STATUS 0x00000824 #define REG_A6XX_CP_STATUS_1 0x00000825 @@ -1128,25 +1376,29 @@ enum a6xx_tex_type { #define A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT 0 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_MRB_START(uint32_t val) { - return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_MRB_START__MASK; } #define A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK 0x0000ff00 #define A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT 8 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_VSD_START(uint32_t val) { - return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_VSD_START__MASK; } #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK 0x00ff0000 #define A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT 16 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB1_START(uint32_t val) { - return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB1_START__MASK; } #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK 0xff000000 #define A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT 24 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val) { - return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_1_IB2_START__MASK; } #define REG_A6XX_CP_ROQ_THRESHOLDS_2 0x000008c2 @@ -1154,13 +1406,15 @@ static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_1_IB2_START(uint32_t val) #define A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT 0 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_SDS_START(uint32_t val) { - return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_SDS_START__MASK; } #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK 0xffff0000 #define A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT 16 static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val) { - return ((val >> 2) << A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__SHIFT) & A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE__MASK; } #define REG_A6XX_CP_MEM_POOL_SIZE 0x000008c3 @@ -1176,11 +1430,11 @@ static inline uint32_t A6XX_CP_ROQ_THRESHOLDS_2_ROQ_SIZE(uint32_t val) #define A6XX_CP_PROTECT_CNTL_ACCESS_FAULT_ON_VIOL_EN 0x00000002 #define A6XX_CP_PROTECT_CNTL_ACCESS_PROT_EN 0x00000001 -static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; } +#define REG_A6XX_CP_SCRATCH(i0) (0x00000883 + 0x1*(i0)) static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; } -static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; } +#define REG_A6XX_CP_PROTECT(i0) (0x00000850 + 0x1*(i0)) static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; } #define A6XX_CP_PROTECT_REG_BASE_ADDR__MASK 0x0003ffff @@ -1209,9 +1463,9 @@ static inline uint32_t A6XX_CP_PROTECT_REG_MASK_LEN(uint32_t val) #define REG_A7XX_CP_CONTEXT_SWITCH_LEVEL_STATUS 0x000008ab -static inline uint32_t REG_A6XX_CP_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008d0 + 0x1*i0; } +#define REG_A6XX_CP_PERFCTR_CP_SEL(i0) (0x000008d0 + 0x1*(i0)) -static inline uint32_t REG_A7XX_CP_BV_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008e0 + 0x1*i0; } +#define REG_A7XX_CP_BV_PERFCTR_CP_SEL(i0) (0x000008e0 + 0x1*(i0)) #define REG_A6XX_CP_CRASH_SCRIPT_BASE 0x00000900 @@ -1405,8 +1659,48 @@ static inline uint32_t A6XX_CP_ROQ_AVAIL_VSD_REM(uint32_t val) #define REG_A6XX_CP_APERTURE_CNTL_HOST 0x00000a00 +#define REG_A7XX_CP_APERTURE_CNTL_HOST 0x00000a00 +#define A7XX_CP_APERTURE_CNTL_HOST_PIPE__MASK 0x00003000 +#define A7XX_CP_APERTURE_CNTL_HOST_PIPE__SHIFT 12 +static inline uint32_t A7XX_CP_APERTURE_CNTL_HOST_PIPE(enum a7xx_pipe val) +{ + return ((val) << A7XX_CP_APERTURE_CNTL_HOST_PIPE__SHIFT) & A7XX_CP_APERTURE_CNTL_HOST_PIPE__MASK; +} +#define A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__MASK 0x00000700 +#define A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__SHIFT 8 +static inline uint32_t A7XX_CP_APERTURE_CNTL_HOST_CLUSTER(enum a7xx_cluster val) +{ + return ((val) << A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__SHIFT) & A7XX_CP_APERTURE_CNTL_HOST_CLUSTER__MASK; +} +#define A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__MASK 0x00000030 +#define A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__SHIFT 4 +static inline uint32_t A7XX_CP_APERTURE_CNTL_HOST_CONTEXT(uint32_t val) +{ + return ((val) << A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__SHIFT) & A7XX_CP_APERTURE_CNTL_HOST_CONTEXT__MASK; +} + #define REG_A6XX_CP_APERTURE_CNTL_CD 0x00000a03 +#define REG_A7XX_CP_APERTURE_CNTL_CD 0x00000a03 +#define A7XX_CP_APERTURE_CNTL_CD_PIPE__MASK 0x00003000 +#define A7XX_CP_APERTURE_CNTL_CD_PIPE__SHIFT 12 +static inline uint32_t A7XX_CP_APERTURE_CNTL_CD_PIPE(enum a7xx_pipe val) +{ + return ((val) << A7XX_CP_APERTURE_CNTL_CD_PIPE__SHIFT) & A7XX_CP_APERTURE_CNTL_CD_PIPE__MASK; +} +#define A7XX_CP_APERTURE_CNTL_CD_CLUSTER__MASK 0x00000700 +#define A7XX_CP_APERTURE_CNTL_CD_CLUSTER__SHIFT 8 +static inline uint32_t A7XX_CP_APERTURE_CNTL_CD_CLUSTER(enum a7xx_cluster val) +{ + return ((val) << A7XX_CP_APERTURE_CNTL_CD_CLUSTER__SHIFT) & A7XX_CP_APERTURE_CNTL_CD_CLUSTER__MASK; +} +#define A7XX_CP_APERTURE_CNTL_CD_CONTEXT__MASK 0x00000030 +#define A7XX_CP_APERTURE_CNTL_CD_CONTEXT__SHIFT 4 +static inline uint32_t A7XX_CP_APERTURE_CNTL_CD_CONTEXT(uint32_t val) +{ + return ((val) << A7XX_CP_APERTURE_CNTL_CD_CONTEXT__SHIFT) & A7XX_CP_APERTURE_CNTL_CD_CONTEXT__MASK; +} + #define REG_A7XX_CP_BV_PROTECT_STATUS 0x00000a61 #define REG_A7XX_CP_BV_HW_FAULT 0x00000a64 @@ -1472,7 +1766,6 @@ static inline uint32_t A6XX_CP_ROQ_AVAIL_VSD_REM(uint32_t val) #define REG_A6XX_RBBM_GPR0_CNTL 0x00000018 #define REG_A6XX_RBBM_INT_0_STATUS 0x00000201 - #define REG_A6XX_RBBM_STATUS 0x00000210 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB 0x00800000 #define A6XX_RBBM_STATUS_GPU_BUSY_IGN_AHB_CP 0x00400000 @@ -1520,93 +1813,93 @@ static inline uint32_t A6XX_CP_ROQ_AVAIL_VSD_REM(uint32_t val) #define REG_A7XX_RBBM_CLOCK_MODE_BV_GPC 0x00000288 -static inline uint32_t REG_A6XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000400 + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_CP(i0) (0x00000400 + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000041c + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_RBBM(i0) (0x0000041c + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000424 + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_PC(i0) (0x00000424 + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000434 + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_VFD(i0) (0x00000434 + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000444 + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_HLSQ(i0) (0x00000444 + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000450 + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_VPC(i0) (0x00000450 + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000045c + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_CCU(i0) (0x0000045c + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000466 + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_TSE(i0) (0x00000466 + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000046e + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_RAS(i0) (0x0000046e + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000476 + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_UCHE(i0) (0x00000476 + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000048e + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_TP(i0) (0x0000048e + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000004a6 + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_SP(i0) (0x000004a6 + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000004d6 + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_RB(i0) (0x000004d6 + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000004e6 + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_VSC(i0) (0x000004e6 + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000004ea + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_LRZ(i0) (0x000004ea + 0x2*(i0)) -static inline uint32_t REG_A6XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000004f2 + 0x2*i0; } +#define REG_A6XX_RBBM_PERFCTR_CMP(i0) (0x000004f2 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_CP(uint32_t i0) { return 0x00000300 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_CP(i0) (0x00000300 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_RBBM(uint32_t i0) { return 0x0000031c + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_RBBM(i0) (0x0000031c + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_PC(uint32_t i0) { return 0x00000324 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_PC(i0) (0x00000324 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_VFD(uint32_t i0) { return 0x00000334 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_VFD(i0) (0x00000334 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_HLSQ(uint32_t i0) { return 0x00000344 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_HLSQ(i0) (0x00000344 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_VPC(uint32_t i0) { return 0x00000350 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_VPC(i0) (0x00000350 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_CCU(uint32_t i0) { return 0x0000035c + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_CCU(i0) (0x0000035c + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_TSE(uint32_t i0) { return 0x00000366 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_TSE(i0) (0x00000366 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_RAS(uint32_t i0) { return 0x0000036e + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_RAS(i0) (0x0000036e + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_UCHE(uint32_t i0) { return 0x00000376 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_UCHE(i0) (0x00000376 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_TP(uint32_t i0) { return 0x0000038e + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_TP(i0) (0x0000038e + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_SP(uint32_t i0) { return 0x000003a6 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_SP(i0) (0x000003a6 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_RB(uint32_t i0) { return 0x000003d6 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_RB(i0) (0x000003d6 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_VSC(uint32_t i0) { return 0x000003e6 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_VSC(i0) (0x000003e6 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_LRZ(uint32_t i0) { return 0x000003ea + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_LRZ(i0) (0x000003ea + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_CMP(uint32_t i0) { return 0x000003f2 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_CMP(i0) (0x000003f2 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_UFC(uint32_t i0) { return 0x000003fa + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_UFC(i0) (0x000003fa + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR2_HLSQ(uint32_t i0) { return 0x00000410 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR2_HLSQ(i0) (0x00000410 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR2_CP(uint32_t i0) { return 0x0000041c + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR2_CP(i0) (0x0000041c + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR2_SP(uint32_t i0) { return 0x0000042a + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR2_SP(i0) (0x0000042a + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR2_TP(uint32_t i0) { return 0x00000442 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR2_TP(i0) (0x00000442 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR2_UFC(uint32_t i0) { return 0x0000044e + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR2_UFC(i0) (0x0000044e + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_PC(uint32_t i0) { return 0x00000460 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_BV_PC(i0) (0x00000460 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_VFD(uint32_t i0) { return 0x00000470 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_BV_VFD(i0) (0x00000470 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_VPC(uint32_t i0) { return 0x00000480 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_BV_VPC(i0) (0x00000480 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_TSE(uint32_t i0) { return 0x0000048c + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_BV_TSE(i0) (0x0000048c + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_RAS(uint32_t i0) { return 0x00000494 + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_BV_RAS(i0) (0x00000494 + 0x2*(i0)) -static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_LRZ(uint32_t i0) { return 0x0000049c + 0x2*i0; } +#define REG_A7XX_RBBM_PERFCTR_BV_LRZ(i0) (0x0000049c + 0x2*(i0)) #define REG_A6XX_RBBM_PERFCTR_CNTL 0x00000500 @@ -1622,7 +1915,7 @@ static inline uint32_t REG_A7XX_RBBM_PERFCTR_BV_LRZ(uint32_t i0) { return 0x0000 #define REG_A6XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000506 -static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00000507 + 0x1*i0; } +#define REG_A6XX_RBBM_PERFCTR_RBBM_SEL(i0) (0x00000507 + 0x1*(i0)) #define REG_A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED 0x0000050b @@ -1710,9 +2003,7 @@ static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00 #define REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL 0x0000001f #define REG_A6XX_RBBM_INT_CLEAR_CMD 0x00000037 - #define REG_A6XX_RBBM_INT_0_MASK 0x00000038 - #define REG_A7XX_RBBM_INT_2_MASK 0x0000003a #define REG_A6XX_RBBM_SP_HYST_CNT 0x00000042 @@ -1725,6 +2016,8 @@ static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00 #define REG_A6XX_RBBM_BLOCK_SW_RESET_CMD2 0x00000046 +#define REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL 0x000000ad + #define REG_A6XX_RBBM_CLOCK_CNTL 0x000000ae #define REG_A6XX_RBBM_CLOCK_CNTL_SP0 0x000000b0 @@ -1939,12 +2232,37 @@ static inline uint32_t REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) { return 0x00 #define REG_A6XX_RBBM_CLOCK_HYST_HLSQ 0x0000011d +#define REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD 0x0000011e + +#define REG_A7XX_RBBM_CGC_P2S_TRIG_CMD 0x0000011f + #define REG_A6XX_RBBM_CLOCK_CNTL_TEX_FCHE 0x00000120 #define REG_A6XX_RBBM_CLOCK_DELAY_TEX_FCHE 0x00000121 #define REG_A6XX_RBBM_CLOCK_HYST_TEX_FCHE 0x00000122 +#define REG_A7XX_RBBM_CGC_P2S_STATUS 0x00000122 +#define A7XX_RBBM_CGC_P2S_STATUS_TXDONE 0x00000001 + +#define REG_A6XX_RBBM_CLOCK_CNTL_FCHE 0x00000123 + +#define REG_A6XX_RBBM_CLOCK_DELAY_FCHE 0x00000124 + +#define REG_A6XX_RBBM_CLOCK_HYST_FCHE 0x00000125 + +#define REG_A6XX_RBBM_CLOCK_CNTL_MHUB 0x00000126 + +#define REG_A6XX_RBBM_CLOCK_DELAY_MHUB 0x00000127 + +#define REG_A6XX_RBBM_CLOCK_HYST_MHUB 0x00000128 + +#define REG_A6XX_RBBM_CLOCK_DELAY_GLC 0x00000129 + +#define REG_A6XX_RBBM_CLOCK_HYST_GLC 0x0000012a + +#define REG_A6XX_RBBM_CLOCK_CNTL_GLC 0x0000012b + #define REG_A7XX_RBBM_CLOCK_HYST2_VFD 0x0000012f #define REG_A6XX_RBBM_LPAC_GBIF_CLIENT_QOS_CNTL 0x000005ff @@ -2117,7 +2435,10 @@ static inline uint32_t A6XX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) #define REG_A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 0x00000630 -static inline uint32_t REG_A6XX_VSC_PERFCTR_VSC_SEL(uint32_t i0) { return 0x00000cd8 + 0x1*i0; } +#define REG_A6XX_VSC_PERFCTR_VSC_SEL(i0) (0x00000cd8 + 0x1*(i0)) + +#define REG_A7XX_VSC_UNKNOWN_0CD8 0x00000cd8 +#define A7XX_VSC_UNKNOWN_0CD8_BINNING 0x00000001 #define REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE 0x0000c800 @@ -2149,7 +2470,7 @@ static inline uint32_t A6XX_UCHE_CLIENT_PF_PERFSEL(uint32_t val) return ((val) << A6XX_UCHE_CLIENT_PF_PERFSEL__SHIFT) & A6XX_UCHE_CLIENT_PF_PERFSEL__MASK; } -static inline uint32_t REG_A6XX_UCHE_PERFCTR_UCHE_SEL(uint32_t i0) { return 0x00000e1c + 0x1*i0; } +#define REG_A6XX_UCHE_PERFCTR_UCHE_SEL(i0) (0x00000e1c + 0x1*(i0)) #define REG_A6XX_UCHE_GBIF_GX_CONFIG 0x00000e3a @@ -2291,13 +2612,15 @@ static inline uint32_t A6XX_VBIF_TEST_BUS2_CTRL1_DATA_SEL(uint32_t val) #define A6XX_VSC_BIN_SIZE_WIDTH__SHIFT 0 static inline uint32_t A6XX_VSC_BIN_SIZE_WIDTH(uint32_t val) { - return ((val >> 5) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A6XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A6XX_VSC_BIN_SIZE_WIDTH__MASK; } #define A6XX_VSC_BIN_SIZE_HEIGHT__MASK 0x0001ff00 #define A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT 8 static inline uint32_t A6XX_VSC_BIN_SIZE_HEIGHT(uint32_t val) { - return ((val >> 4) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK; + assert(!(val & 0xf)); + return (((val >> 4)) << A6XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A6XX_VSC_BIN_SIZE_HEIGHT__MASK; } #define REG_A6XX_VSC_DRAW_STRM_SIZE_ADDRESS 0x00000c03 @@ -2316,7 +2639,7 @@ static inline uint32_t A6XX_VSC_BIN_COUNT_NY(uint32_t val) return ((val) << A6XX_VSC_BIN_COUNT_NY__SHIFT) & A6XX_VSC_BIN_COUNT_NY__MASK; } -static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } +#define REG_A6XX_VSC_PIPE_CONFIG(i0) (0x00000c10 + 0x1*(i0)) static inline uint32_t REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) { return 0x00000c10 + 0x1*i0; } #define A6XX_VSC_PIPE_CONFIG_REG_X__MASK 0x000003ff @@ -2356,18 +2679,22 @@ static inline uint32_t A6XX_VSC_PIPE_CONFIG_REG_H(uint32_t val) #define REG_A6XX_VSC_DRAW_STRM_LIMIT 0x00000c37 -static inline uint32_t REG_A6XX_VSC_STATE(uint32_t i0) { return 0x00000c38 + 0x1*i0; } +#define REG_A6XX_VSC_STATE(i0) (0x00000c38 + 0x1*(i0)) static inline uint32_t REG_A6XX_VSC_STATE_REG(uint32_t i0) { return 0x00000c38 + 0x1*i0; } -static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE(uint32_t i0) { return 0x00000c58 + 0x1*i0; } +#define REG_A6XX_VSC_PRIM_STRM_SIZE(i0) (0x00000c58 + 0x1*(i0)) static inline uint32_t REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) { return 0x00000c58 + 0x1*i0; } -static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE(uint32_t i0) { return 0x00000c78 + 0x1*i0; } +#define REG_A6XX_VSC_DRAW_STRM_SIZE(i0) (0x00000c78 + 0x1*(i0)) static inline uint32_t REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0) { return 0x00000c78 + 0x1*i0; } +#define REG_A7XX_UCHE_UNKNOWN_0E10 0x00000e10 + +#define REG_A7XX_UCHE_UNKNOWN_0E11 0x00000e11 + #define REG_A6XX_UCHE_UNKNOWN_0E12 0x00000e12 #define REG_A6XX_GRAS_CL_CNTL 0x00008000 @@ -2437,6 +2764,8 @@ static inline uint32_t A6XX_GRAS_CNTL_COORD_MASK(uint32_t val) { return ((val) << A6XX_GRAS_CNTL_COORD_MASK__SHIFT) & A6XX_GRAS_CNTL_COORD_MASK__MASK; } +#define A6XX_GRAS_CNTL_UNK10 0x00000400 +#define A6XX_GRAS_CNTL_UNK11 0x00000800 #define REG_A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ 0x00008006 #define A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_HORZ__MASK 0x000001ff @@ -2452,7 +2781,19 @@ static inline uint32_t A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT(uint32_t val) return ((val) << A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__SHIFT) & A6XX_GRAS_CL_GUARDBAND_CLIP_ADJ_VERT__MASK; } -static inline uint32_t REG_A6XX_GRAS_CL_VPORT(uint32_t i0) { return 0x00008010 + 0x6*i0; } +#define REG_A7XX_GRAS_UNKNOWN_8007 0x00008007 + +#define REG_A7XX_GRAS_UNKNOWN_8008 0x00008008 + +#define REG_A7XX_GRAS_UNKNOWN_8009 0x00008009 + +#define REG_A7XX_GRAS_UNKNOWN_800A 0x0000800a + +#define REG_A7XX_GRAS_UNKNOWN_800B 0x0000800b + +#define REG_A7XX_GRAS_UNKNOWN_800C 0x0000800c + +#define REG_A6XX_GRAS_CL_VPORT(i0) (0x00008010 + 0x6*(i0)) static inline uint32_t REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0) { return 0x00008010 + 0x6*i0; } #define A6XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff @@ -2502,7 +2843,7 @@ static inline uint32_t A6XX_GRAS_CL_VPORT_ZSCALE(float val) return ((fui(val)) << A6XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A6XX_GRAS_CL_VPORT_ZSCALE__MASK; } -static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP(uint32_t i0) { return 0x00008070 + 0x2*i0; } +#define REG_A6XX_GRAS_CL_Z_CLAMP(i0) (0x00008070 + 0x2*(i0)) static inline uint32_t REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0) { return 0x00008070 + 0x2*i0; } #define A6XX_GRAS_CL_Z_CLAMP_MIN__MASK 0xffffffff @@ -2531,12 +2872,7 @@ static inline uint32_t A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(float val) return ((((int32_t)(val * 4.0))) << A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__SHIFT) & A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK; } #define A6XX_GRAS_SU_CNTL_POLY_OFFSET 0x00000800 -#define A6XX_GRAS_SU_CNTL_UNK12__MASK 0x00001000 -#define A6XX_GRAS_SU_CNTL_UNK12__SHIFT 12 -static inline uint32_t A6XX_GRAS_SU_CNTL_UNK12(uint32_t val) -{ - return ((val) << A6XX_GRAS_SU_CNTL_UNK12__SHIFT) & A6XX_GRAS_SU_CNTL_UNK12__MASK; -} +#define A6XX_GRAS_SU_CNTL_UNK12 0x00001000 #define A6XX_GRAS_SU_CNTL_LINE_MODE__MASK 0x00002000 #define A6XX_GRAS_SU_CNTL_LINE_MODE__SHIFT 13 static inline uint32_t A6XX_GRAS_SU_CNTL_LINE_MODE(enum a5xx_line_mode val) @@ -2549,13 +2885,14 @@ static inline uint32_t A6XX_GRAS_SU_CNTL_UNK15(uint32_t val) { return ((val) << A6XX_GRAS_SU_CNTL_UNK15__SHIFT) & A6XX_GRAS_SU_CNTL_UNK15__MASK; } -#define A6XX_GRAS_SU_CNTL_UNK17 0x00020000 -#define A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE 0x00040000 -#define A6XX_GRAS_SU_CNTL_UNK19__MASK 0x00780000 -#define A6XX_GRAS_SU_CNTL_UNK19__SHIFT 19 -static inline uint32_t A6XX_GRAS_SU_CNTL_UNK19(uint32_t val) +#define A6XX_GRAS_SU_CNTL_MULTIVIEW_ENABLE 0x00020000 +#define A6XX_GRAS_SU_CNTL_RENDERTARGETINDEXINCR 0x00040000 +#define A6XX_GRAS_SU_CNTL_VIEWPORTINDEXINCR 0x00080000 +#define A6XX_GRAS_SU_CNTL_UNK20__MASK 0x00700000 +#define A6XX_GRAS_SU_CNTL_UNK20__SHIFT 20 +static inline uint32_t A6XX_GRAS_SU_CNTL_UNK20(uint32_t val) { - return ((val) << A6XX_GRAS_SU_CNTL_UNK19__SHIFT) & A6XX_GRAS_SU_CNTL_UNK19__MASK; + return ((val) << A6XX_GRAS_SU_CNTL_UNK20__SHIFT) & A6XX_GRAS_SU_CNTL_UNK20__MASK; } #define REG_A6XX_GRAS_SU_POINT_MINMAX 0x00008091 @@ -2619,12 +2956,7 @@ static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_dep { return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; } -#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000008 -#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT 3 -static inline uint32_t A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3(uint32_t val) -{ - return ((val) << A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3__MASK; -} +#define A6XX_GRAS_SU_DEPTH_BUFFER_INFO_UNK3 0x00000008 #define REG_A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL 0x00008099 #define A6XX_GRAS_SU_CONSERVATIVE_RAS_CNTL_CONSERVATIVERASEN 0x00000001 @@ -2703,13 +3035,15 @@ static inline uint32_t A6XX_GRAS_SC_CNTL_ROTATION(uint32_t val) #define A6XX_GRAS_BIN_CONTROL_BINW__SHIFT 0 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINW(uint32_t val) { - return ((val >> 5) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A6XX_GRAS_BIN_CONTROL_BINW__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINW__MASK; } #define A6XX_GRAS_BIN_CONTROL_BINH__MASK 0x00007f00 #define A6XX_GRAS_BIN_CONTROL_BINH__SHIFT 8 static inline uint32_t A6XX_GRAS_BIN_CONTROL_BINH(uint32_t val) { - return ((val >> 4) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK; + assert(!(val & 0xf)); + return (((val >> 4)) << A6XX_GRAS_BIN_CONTROL_BINH__SHIFT) & A6XX_GRAS_BIN_CONTROL_BINH__MASK; } #define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000 #define A6XX_GRAS_BIN_CONTROL_RENDER_MODE__SHIFT 18 @@ -2730,12 +3064,7 @@ static inline uint32_t A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t va { return ((val) << A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_GRAS_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK; } -#define A6XX_GRAS_BIN_CONTROL_UNK27__MASK 0x08000000 -#define A6XX_GRAS_BIN_CONTROL_UNK27__SHIFT 27 -static inline uint32_t A6XX_GRAS_BIN_CONTROL_UNK27(uint32_t val) -{ - return ((val) << A6XX_GRAS_BIN_CONTROL_UNK27__SHIFT) & A6XX_GRAS_BIN_CONTROL_UNK27__MASK; -} +#define A6XX_GRAS_BIN_CONTROL_UNK27 0x08000000 #define REG_A6XX_GRAS_RAS_MSAA_CNTL 0x000080a2 #define A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 @@ -2744,18 +3073,8 @@ static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples va { return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES__MASK; } -#define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK 0x00000004 -#define A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT 2 -static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK2(uint32_t val) -{ - return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK2__MASK; -} -#define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK 0x00000008 -#define A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT 3 -static inline uint32_t A6XX_GRAS_RAS_MSAA_CNTL_UNK3(uint32_t val) -{ - return ((val) << A6XX_GRAS_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_GRAS_RAS_MSAA_CNTL_UNK3__MASK; -} +#define A6XX_GRAS_RAS_MSAA_CNTL_UNK2 0x00000004 +#define A6XX_GRAS_RAS_MSAA_CNTL_UNK3 0x00000008 #define REG_A6XX_GRAS_DEST_MSAA_CNTL 0x000080a3 #define A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 @@ -2775,49 +3094,49 @@ static inline uint32_t A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples v #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; } #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; } #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; } #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; } #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; } #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; } #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; } #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 #define A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; } #define REG_A6XX_GRAS_SAMPLE_LOCATION_1 0x000080a6 @@ -2825,54 +3144,56 @@ static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; } #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; } #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; } #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; } #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; } #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; } #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; } #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 #define A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 static inline uint32_t A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_GRAS_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; } +#define REG_A7XX_GRAS_UNKNOWN_80A7 0x000080a7 + #define REG_A6XX_GRAS_UNKNOWN_80AF 0x000080af -static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR(uint32_t i0) { return 0x000080b0 + 0x2*i0; } +#define REG_A6XX_GRAS_SC_SCREEN_SCISSOR(i0) (0x000080b0 + 0x2*(i0)) static inline uint32_t REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0) { return 0x000080b0 + 0x2*i0; } #define A6XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x0000ffff @@ -2902,7 +3223,7 @@ static inline uint32_t A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val) return ((val) << A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK; } -static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(uint32_t i0) { return 0x000080d0 + 0x2*i0; } +#define REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(i0) (0x000080d0 + 0x2*(i0)) static inline uint32_t REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0) { return 0x000080d0 + 0x2*i0; } #define A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL_X__MASK 0x0000ffff @@ -2960,6 +3281,18 @@ static inline uint32_t A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val) return ((val) << A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK; } +#define REG_A7XX_GRAS_UNKNOWN_80F4 0x000080f4 + +#define REG_A7XX_GRAS_UNKNOWN_80F5 0x000080f5 + +#define REG_A7XX_GRAS_UNKNOWN_80F6 0x000080f6 + +#define REG_A7XX_GRAS_UNKNOWN_80F8 0x000080f8 + +#define REG_A7XX_GRAS_UNKNOWN_80F9 0x000080f9 + +#define REG_A7XX_GRAS_UNKNOWN_80FA 0x000080fa + #define REG_A6XX_GRAS_LRZ_CNTL 0x00008100 #define A6XX_GRAS_LRZ_CNTL_ENABLE 0x00000001 #define A6XX_GRAS_LRZ_CNTL_LRZ_WRITE 0x00000002 @@ -2975,6 +3308,12 @@ static inline uint32_t A6XX_GRAS_LRZ_CNTL_DIR(enum a6xx_lrz_dir_status val) } #define A6XX_GRAS_LRZ_CNTL_DIR_WRITE 0x00000100 #define A6XX_GRAS_LRZ_CNTL_DISABLE_ON_WRONG_DIR 0x00000200 +#define A6XX_GRAS_LRZ_CNTL_Z_FUNC__MASK 0x00003800 +#define A6XX_GRAS_LRZ_CNTL_Z_FUNC__SHIFT 11 +static inline uint32_t A6XX_GRAS_LRZ_CNTL_Z_FUNC(enum adreno_compare_func val) +{ + return ((val) << A6XX_GRAS_LRZ_CNTL_Z_FUNC__SHIFT) & A6XX_GRAS_LRZ_CNTL_Z_FUNC__MASK; +} #define REG_A6XX_GRAS_LRZ_PS_INPUT_CNTL 0x00008101 #define A6XX_GRAS_LRZ_PS_INPUT_CNTL_SAMPLEID 0x00000001 @@ -2994,34 +3333,24 @@ static inline uint32_t A6XX_GRAS_LRZ_MRT_BUF_INFO_0_COLOR_FORMAT(enum a6xx_forma } #define REG_A6XX_GRAS_LRZ_BUFFER_BASE 0x00008103 -#define A6XX_GRAS_LRZ_BUFFER_BASE__MASK 0xffffffff -#define A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT 0 -static inline uint32_t A6XX_GRAS_LRZ_BUFFER_BASE(uint32_t val) -{ - return ((val) << A6XX_GRAS_LRZ_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_BUFFER_BASE__MASK; -} #define REG_A6XX_GRAS_LRZ_BUFFER_PITCH 0x00008105 #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK 0x000000ff #define A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT 0 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH(uint32_t val) { - return ((val >> 5) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_PITCH__MASK; } #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffffc00 #define A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT 10 static inline uint32_t A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) { - return ((val >> 4) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK; + assert(!(val & 0xf)); + return (((val >> 4)) << A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_GRAS_LRZ_BUFFER_PITCH_ARRAY_PITCH__MASK; } #define REG_A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE 0x00008106 -#define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK 0xffffffff -#define A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT 0 -static inline uint32_t A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(uint32_t val) -{ - return ((val) << A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__SHIFT) & A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE__MASK; -} #define REG_A6XX_GRAS_SAMPLE_CNTL 0x00008109 #define A6XX_GRAS_SAMPLE_CNTL_PER_SAMP_MODE 0x00000001 @@ -3046,8 +3375,24 @@ static inline uint32_t A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL(uint32_t val) return ((val) << A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__SHIFT) & A6XX_GRAS_LRZ_DEPTH_VIEW_BASE_MIP_LEVEL__MASK; } +#define REG_A7XX_GRAS_UNKNOWN_810B 0x0000810b + #define REG_A6XX_GRAS_UNKNOWN_8110 0x00008110 +#define REG_A7XX_GRAS_LRZ_CLEAR_DEPTH_F32 0x00008111 +#define A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__MASK 0xffffffff +#define A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__SHIFT 0 +static inline uint32_t A7XX_GRAS_LRZ_CLEAR_DEPTH_F32(float val) +{ + return ((fui(val)) << A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__SHIFT) & A7XX_GRAS_LRZ_CLEAR_DEPTH_F32__MASK; +} + +#define REG_A7XX_GRAS_UNKNOWN_8113 0x00008113 + +#define REG_A7XX_GRAS_UNKNOWN_8120 0x00008120 + +#define REG_A7XX_GRAS_UNKNOWN_8121 0x00008121 + #define REG_A6XX_GRAS_2D_BLIT_CNTL 0x00008400 #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__MASK 0x00000007 #define A6XX_GRAS_2D_BLIT_CNTL_ROTATE__SHIFT 0 @@ -3095,14 +3440,39 @@ static inline uint32_t A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode { return ((val) << A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_GRAS_2D_BLIT_CNTL_RASTER_MODE__MASK; } +#define A6XX_GRAS_2D_BLIT_CNTL_UNK30 0x40000000 #define REG_A6XX_GRAS_2D_SRC_TL_X 0x00008401 +#define A6XX_GRAS_2D_SRC_TL_X__MASK 0x01ffff00 +#define A6XX_GRAS_2D_SRC_TL_X__SHIFT 8 +static inline uint32_t A6XX_GRAS_2D_SRC_TL_X(int32_t val) +{ + return ((val) << A6XX_GRAS_2D_SRC_TL_X__SHIFT) & A6XX_GRAS_2D_SRC_TL_X__MASK; +} #define REG_A6XX_GRAS_2D_SRC_BR_X 0x00008402 +#define A6XX_GRAS_2D_SRC_BR_X__MASK 0x01ffff00 +#define A6XX_GRAS_2D_SRC_BR_X__SHIFT 8 +static inline uint32_t A6XX_GRAS_2D_SRC_BR_X(int32_t val) +{ + return ((val) << A6XX_GRAS_2D_SRC_BR_X__SHIFT) & A6XX_GRAS_2D_SRC_BR_X__MASK; +} #define REG_A6XX_GRAS_2D_SRC_TL_Y 0x00008403 +#define A6XX_GRAS_2D_SRC_TL_Y__MASK 0x01ffff00 +#define A6XX_GRAS_2D_SRC_TL_Y__SHIFT 8 +static inline uint32_t A6XX_GRAS_2D_SRC_TL_Y(int32_t val) +{ + return ((val) << A6XX_GRAS_2D_SRC_TL_Y__SHIFT) & A6XX_GRAS_2D_SRC_TL_Y__MASK; +} #define REG_A6XX_GRAS_2D_SRC_BR_Y 0x00008404 +#define A6XX_GRAS_2D_SRC_BR_Y__MASK 0x01ffff00 +#define A6XX_GRAS_2D_SRC_BR_Y__SHIFT 8 +static inline uint32_t A6XX_GRAS_2D_SRC_BR_Y(int32_t val) +{ + return ((val) << A6XX_GRAS_2D_SRC_BR_Y__SHIFT) & A6XX_GRAS_2D_SRC_BR_Y__MASK; +} #define REG_A6XX_GRAS_2D_DST_TL 0x00008405 #define A6XX_GRAS_2D_DST_TL_X__MASK 0x00003fff @@ -3174,24 +3544,26 @@ static inline uint32_t A6XX_GRAS_2D_RESOLVE_CNTL_2_Y(uint32_t val) #define REG_A7XX_GRAS_NC_MODE_CNTL 0x00008602 -static inline uint32_t REG_A6XX_GRAS_PERFCTR_TSE_SEL(uint32_t i0) { return 0x00008610 + 0x1*i0; } +#define REG_A6XX_GRAS_PERFCTR_TSE_SEL(i0) (0x00008610 + 0x1*(i0)) -static inline uint32_t REG_A6XX_GRAS_PERFCTR_RAS_SEL(uint32_t i0) { return 0x00008614 + 0x1*i0; } +#define REG_A6XX_GRAS_PERFCTR_RAS_SEL(i0) (0x00008614 + 0x1*(i0)) -static inline uint32_t REG_A6XX_GRAS_PERFCTR_LRZ_SEL(uint32_t i0) { return 0x00008618 + 0x1*i0; } +#define REG_A6XX_GRAS_PERFCTR_LRZ_SEL(i0) (0x00008618 + 0x1*(i0)) #define REG_A6XX_RB_BIN_CONTROL 0x00008800 #define A6XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f #define A6XX_RB_BIN_CONTROL_BINW__SHIFT 0 static inline uint32_t A6XX_RB_BIN_CONTROL_BINW(uint32_t val) { - return ((val >> 5) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A6XX_RB_BIN_CONTROL_BINW__SHIFT) & A6XX_RB_BIN_CONTROL_BINW__MASK; } #define A6XX_RB_BIN_CONTROL_BINH__MASK 0x00007f00 #define A6XX_RB_BIN_CONTROL_BINH__SHIFT 8 static inline uint32_t A6XX_RB_BIN_CONTROL_BINH(uint32_t val) { - return ((val >> 4) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK; + assert(!(val & 0xf)); + return (((val >> 4)) << A6XX_RB_BIN_CONTROL_BINH__SHIFT) & A6XX_RB_BIN_CONTROL_BINH__MASK; } #define A6XX_RB_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000 #define A6XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT 18 @@ -3213,6 +3585,35 @@ static inline uint32_t A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val) return ((val) << A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A6XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK; } +#define REG_A7XX_RB_BIN_CONTROL 0x00008800 +#define A7XX_RB_BIN_CONTROL_BINW__MASK 0x0000003f +#define A7XX_RB_BIN_CONTROL_BINW__SHIFT 0 +static inline uint32_t A7XX_RB_BIN_CONTROL_BINW(uint32_t val) +{ + assert(!(val & 0x1f)); + return (((val >> 5)) << A7XX_RB_BIN_CONTROL_BINW__SHIFT) & A7XX_RB_BIN_CONTROL_BINW__MASK; +} +#define A7XX_RB_BIN_CONTROL_BINH__MASK 0x00007f00 +#define A7XX_RB_BIN_CONTROL_BINH__SHIFT 8 +static inline uint32_t A7XX_RB_BIN_CONTROL_BINH(uint32_t val) +{ + assert(!(val & 0xf)); + return (((val >> 4)) << A7XX_RB_BIN_CONTROL_BINH__SHIFT) & A7XX_RB_BIN_CONTROL_BINH__MASK; +} +#define A7XX_RB_BIN_CONTROL_RENDER_MODE__MASK 0x001c0000 +#define A7XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT 18 +static inline uint32_t A7XX_RB_BIN_CONTROL_RENDER_MODE(enum a6xx_render_mode val) +{ + return ((val) << A7XX_RB_BIN_CONTROL_RENDER_MODE__SHIFT) & A7XX_RB_BIN_CONTROL_RENDER_MODE__MASK; +} +#define A7XX_RB_BIN_CONTROL_FORCE_LRZ_WRITE_DIS 0x00200000 +#define A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK 0x07000000 +#define A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT 24 +static inline uint32_t A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK(uint32_t val) +{ + return ((val) << A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__SHIFT) & A7XX_RB_BIN_CONTROL_LRZ_FEEDBACK_ZMODE_MASK__MASK; +} + #define REG_A6XX_RB_RENDER_CNTL 0x00008801 #define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__MASK 0x00000038 #define A6XX_RB_RENDER_CNTL_CCUSINGLECACHELINESIZE__SHIFT 3 @@ -3250,6 +3651,27 @@ static inline uint32_t A6XX_RB_RENDER_CNTL_FLAG_MRTS(uint32_t val) return ((val) << A6XX_RB_RENDER_CNTL_FLAG_MRTS__SHIFT) & A6XX_RB_RENDER_CNTL_FLAG_MRTS__MASK; } +#define REG_A7XX_RB_RENDER_CNTL 0x00008801 +#define A7XX_RB_RENDER_CNTL_EARLYVIZOUTEN 0x00000040 +#define A7XX_RB_RENDER_CNTL_BINNING 0x00000080 +#define A7XX_RB_RENDER_CNTL_RASTER_MODE__MASK 0x00000100 +#define A7XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT 8 +static inline uint32_t A7XX_RB_RENDER_CNTL_RASTER_MODE(enum a6xx_raster_mode val) +{ + return ((val) << A7XX_RB_RENDER_CNTL_RASTER_MODE__SHIFT) & A7XX_RB_RENDER_CNTL_RASTER_MODE__MASK; +} +#define A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK 0x00000600 +#define A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT 9 +static inline uint32_t A7XX_RB_RENDER_CNTL_RASTER_DIRECTION(enum a6xx_raster_direction val) +{ + return ((val) << A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__SHIFT) & A7XX_RB_RENDER_CNTL_RASTER_DIRECTION__MASK; +} +#define A7XX_RB_RENDER_CNTL_CONSERVATIVERASEN 0x00000800 +#define A7XX_RB_RENDER_CNTL_INNERCONSERVATIVERASEN 0x00001000 + +#define REG_A7XX_GRAS_SU_RENDER_CNTL 0x00008116 +#define A7XX_GRAS_SU_RENDER_CNTL_BINNING 0x00000080 + #define REG_A6XX_RB_RAS_MSAA_CNTL 0x00008802 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK 0x00000003 #define A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT 0 @@ -3257,18 +3679,8 @@ static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val) { return ((val) << A6XX_RB_RAS_MSAA_CNTL_SAMPLES__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_SAMPLES__MASK; } -#define A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK 0x00000004 -#define A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT 2 -static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK2(uint32_t val) -{ - return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK2__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK2__MASK; -} -#define A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK 0x00000008 -#define A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT 3 -static inline uint32_t A6XX_RB_RAS_MSAA_CNTL_UNK3(uint32_t val) -{ - return ((val) << A6XX_RB_RAS_MSAA_CNTL_UNK3__SHIFT) & A6XX_RB_RAS_MSAA_CNTL_UNK3__MASK; -} +#define A6XX_RB_RAS_MSAA_CNTL_UNK2 0x00000004 +#define A6XX_RB_RAS_MSAA_CNTL_UNK3 0x00000008 #define REG_A6XX_RB_DEST_MSAA_CNTL 0x00008803 #define A6XX_RB_DEST_MSAA_CNTL_SAMPLES__MASK 0x00000003 @@ -3288,49 +3700,49 @@ static inline uint32_t A6XX_RB_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples val #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; } #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; } #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; } #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; } #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; } #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; } #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; } #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 #define A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; } #define REG_A6XX_RB_SAMPLE_LOCATION_1 0x00008806 @@ -3338,49 +3750,49 @@ static inline uint32_t A6XX_RB_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; } #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; } #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; } #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; } #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; } #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; } #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; } #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 #define A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 static inline uint32_t A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_RB_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; } #define REG_A6XX_RB_RENDER_CONTROL0 0x00008809 @@ -3514,7 +3926,7 @@ static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5(enum adreno_rb_dithe { return ((val) << A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__SHIFT) & A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT5__MASK; } -#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK 0x00001000 +#define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__MASK 0x00003000 #define A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6__SHIFT 12 static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT6(enum adreno_rb_dither_mode val) { @@ -3542,6 +3954,8 @@ static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dithe #define REG_A6XX_RB_UNKNOWN_8811 0x00008811 +#define REG_A7XX_RB_UNKNOWN_8812 0x00008812 + #define REG_A6XX_RB_UNKNOWN_8818 0x00008818 #define REG_A6XX_RB_UNKNOWN_8819 0x00008819 @@ -3556,7 +3970,7 @@ static inline uint32_t A6XX_RB_DITHER_CNTL_DITHER_MODE_MRT7(enum adreno_rb_dithe #define REG_A6XX_RB_UNKNOWN_881E 0x0000881e -static inline uint32_t REG_A6XX_RB_MRT(uint32_t i0) { return 0x00008820 + 0x8*i0; } +#define REG_A6XX_RB_MRT(i0) (0x00008820 + 0x8*(i0)) static inline uint32_t REG_A6XX_RB_MRT_CONTROL(uint32_t i0) { return 0x00008820 + 0x8*i0; } #define A6XX_RB_MRT_CONTROL_BLEND 0x00000001 @@ -3626,12 +4040,7 @@ static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode { return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; } -#define A6XX_RB_MRT_BUF_INFO_UNK10__MASK 0x00000400 -#define A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT 10 -static inline uint32_t A6XX_RB_MRT_BUF_INFO_UNK10(uint32_t val) -{ - return ((val) << A6XX_RB_MRT_BUF_INFO_UNK10__SHIFT) & A6XX_RB_MRT_BUF_INFO_UNK10__MASK; -} +#define A6XX_RB_MRT_BUF_INFO_UNK10 0x00000400 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000 #define A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13 static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) @@ -3639,37 +4048,49 @@ static inline uint32_t A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) return ((val) << A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A6XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; } +static inline uint32_t REG_A7XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x00008822 + 0x8*i0; } +#define A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x000000ff +#define A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0 +static inline uint32_t A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a6xx_format val) +{ + return ((val) << A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A7XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK; +} +#define A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x00000300 +#define A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 8 +static inline uint32_t A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a6xx_tile_mode val) +{ + return ((val) << A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A7XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK; +} +#define A7XX_RB_MRT_BUF_INFO_UNK10 0x00000400 +#define A7XX_RB_MRT_BUF_INFO_LOSSLESSCOMPEN 0x00000800 +#define A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00006000 +#define A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 13 +static inline uint32_t A7XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val) +{ + return ((val) << A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A7XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK; +} + static inline uint32_t REG_A6XX_RB_MRT_PITCH(uint32_t i0) { return 0x00008823 + 0x8*i0; } -#define A6XX_RB_MRT_PITCH__MASK 0x0000ffff +#define A6XX_RB_MRT_PITCH__MASK 0xffffffff #define A6XX_RB_MRT_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_MRT_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_MRT_PITCH__SHIFT) & A6XX_RB_MRT_PITCH__MASK; } static inline uint32_t REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) { return 0x00008824 + 0x8*i0; } -#define A6XX_RB_MRT_ARRAY_PITCH__MASK 0x1fffffff +#define A6XX_RB_MRT_ARRAY_PITCH__MASK 0xffffffff #define A6XX_RB_MRT_ARRAY_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_MRT_ARRAY_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_MRT_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_ARRAY_PITCH__MASK; } static inline uint32_t REG_A6XX_RB_MRT_BASE(uint32_t i0) { return 0x00008825 + 0x8*i0; } -#define A6XX_RB_MRT_BASE__MASK 0xffffffff -#define A6XX_RB_MRT_BASE__SHIFT 0 -static inline uint32_t A6XX_RB_MRT_BASE(uint32_t val) -{ - return ((val) << A6XX_RB_MRT_BASE__SHIFT) & A6XX_RB_MRT_BASE__MASK; -} static inline uint32_t REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) { return 0x00008827 + 0x8*i0; } -#define A6XX_RB_MRT_BASE_GMEM__MASK 0xfffff000 -#define A6XX_RB_MRT_BASE_GMEM__SHIFT 12 -static inline uint32_t A6XX_RB_MRT_BASE_GMEM(uint32_t val) -{ - return ((val >> 12) << A6XX_RB_MRT_BASE_GMEM__SHIFT) & A6XX_RB_MRT_BASE_GMEM__MASK; -} #define REG_A6XX_RB_BLEND_RED_F32 0x00008860 #define A6XX_RB_BLEND_RED_F32__MASK 0xffffffff @@ -3757,6 +4178,9 @@ static inline uint32_t A6XX_RB_DEPTH_CNTL_ZFUNC(enum adreno_compare_func val) #define A6XX_RB_DEPTH_CNTL_Z_READ_ENABLE 0x00000040 #define A6XX_RB_DEPTH_CNTL_Z_BOUNDS_ENABLE 0x00000080 +#define REG_A6XX_GRAS_SU_DEPTH_CNTL 0x00008114 +#define A6XX_GRAS_SU_DEPTH_CNTL_Z_TEST_ENABLE 0x00000001 + #define REG_A6XX_RB_DEPTH_BUFFER_INFO 0x00008872 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 #define A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 @@ -3771,12 +4195,34 @@ static inline uint32_t A6XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val) return ((val) << A6XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A6XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK; } +#define REG_A7XX_RB_DEPTH_BUFFER_INFO 0x00008872 +#define A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK 0x00000007 +#define A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT 0 +static inline uint32_t A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(enum a6xx_depth_format val) +{ + return ((val) << A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__SHIFT) & A7XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT__MASK; +} +#define A7XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK 0x00000018 +#define A7XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT 3 +static inline uint32_t A7XX_RB_DEPTH_BUFFER_INFO_UNK3(uint32_t val) +{ + return ((val) << A7XX_RB_DEPTH_BUFFER_INFO_UNK3__SHIFT) & A7XX_RB_DEPTH_BUFFER_INFO_UNK3__MASK; +} +#define A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__MASK 0x00000060 +#define A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__SHIFT 5 +static inline uint32_t A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE(enum a6xx_tile_mode val) +{ + return ((val) << A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__SHIFT) & A7XX_RB_DEPTH_BUFFER_INFO_TILEMODE__MASK; +} +#define A7XX_RB_DEPTH_BUFFER_INFO_LOSSLESSCOMPEN 0x00000080 + #define REG_A6XX_RB_DEPTH_BUFFER_PITCH 0x00008873 #define A6XX_RB_DEPTH_BUFFER_PITCH__MASK 0x00003fff #define A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_DEPTH_BUFFER_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_PITCH__MASK; } #define REG_A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH 0x00008874 @@ -3784,24 +4230,13 @@ static inline uint32_t A6XX_RB_DEPTH_BUFFER_PITCH(uint32_t val) #define A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH__MASK; } #define REG_A6XX_RB_DEPTH_BUFFER_BASE 0x00008875 -#define A6XX_RB_DEPTH_BUFFER_BASE__MASK 0xffffffff -#define A6XX_RB_DEPTH_BUFFER_BASE__SHIFT 0 -static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE(uint32_t val) -{ - return ((val) << A6XX_RB_DEPTH_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE__MASK; -} #define REG_A6XX_RB_DEPTH_BUFFER_BASE_GMEM 0x00008877 -#define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK 0xfffff000 -#define A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT 12 -static inline uint32_t A6XX_RB_DEPTH_BUFFER_BASE_GMEM(uint32_t val) -{ - return ((val >> 12) << A6XX_RB_DEPTH_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_DEPTH_BUFFER_BASE_GMEM__MASK; -} #define REG_A6XX_RB_Z_BOUNDS_MIN 0x00008878 #define A6XX_RB_Z_BOUNDS_MIN__MASK 0xffffffff @@ -3872,16 +4307,30 @@ static inline uint32_t A6XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op v return ((val) << A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A6XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK; } +#define REG_A6XX_GRAS_SU_STENCIL_CNTL 0x00008115 +#define A6XX_GRAS_SU_STENCIL_CNTL_STENCIL_ENABLE 0x00000001 + #define REG_A6XX_RB_STENCIL_INFO 0x00008881 #define A6XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 #define A6XX_RB_STENCIL_INFO_UNK1 0x00000002 +#define REG_A7XX_RB_STENCIL_INFO 0x00008881 +#define A7XX_RB_STENCIL_INFO_SEPARATE_STENCIL 0x00000001 +#define A7XX_RB_STENCIL_INFO_UNK1 0x00000002 +#define A7XX_RB_STENCIL_INFO_TILEMODE__MASK 0x0000000c +#define A7XX_RB_STENCIL_INFO_TILEMODE__SHIFT 2 +static inline uint32_t A7XX_RB_STENCIL_INFO_TILEMODE(enum a6xx_tile_mode val) +{ + return ((val) << A7XX_RB_STENCIL_INFO_TILEMODE__SHIFT) & A7XX_RB_STENCIL_INFO_TILEMODE__MASK; +} + #define REG_A6XX_RB_STENCIL_BUFFER_PITCH 0x00008882 #define A6XX_RB_STENCIL_BUFFER_PITCH__MASK 0x00000fff #define A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_STENCIL_BUFFER_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_PITCH__MASK; } #define REG_A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH 0x00008883 @@ -3889,24 +4338,13 @@ static inline uint32_t A6XX_RB_STENCIL_BUFFER_PITCH(uint32_t val) #define A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_RB_STENCIL_BUFFER_ARRAY_PITCH__MASK; } #define REG_A6XX_RB_STENCIL_BUFFER_BASE 0x00008884 -#define A6XX_RB_STENCIL_BUFFER_BASE__MASK 0xffffffff -#define A6XX_RB_STENCIL_BUFFER_BASE__SHIFT 0 -static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE(uint32_t val) -{ - return ((val) << A6XX_RB_STENCIL_BUFFER_BASE__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE__MASK; -} #define REG_A6XX_RB_STENCIL_BUFFER_BASE_GMEM 0x00008886 -#define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK 0xfffff000 -#define A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT 12 -static inline uint32_t A6XX_RB_STENCIL_BUFFER_BASE_GMEM(uint32_t val) -{ - return ((val >> 12) << A6XX_RB_STENCIL_BUFFER_BASE_GMEM__SHIFT) & A6XX_RB_STENCIL_BUFFER_BASE_GMEM__MASK; -} #define REG_A6XX_RB_STENCILREF 0x00008887 #define A6XX_RB_STENCILREF_REF__MASK 0x000000ff @@ -3971,6 +4409,8 @@ static inline uint32_t A6XX_RB_WINDOW_OFFSET_Y(uint32_t val) #define REG_A6XX_RB_LRZ_CNTL 0x00008898 #define A6XX_RB_LRZ_CNTL_ENABLE 0x00000001 +#define REG_A7XX_RB_UNKNOWN_8899 0x00008899 + #define REG_A6XX_RB_Z_CLAMP_MIN 0x000088c0 #define A6XX_RB_Z_CLAMP_MIN__MASK 0xffffffff #define A6XX_RB_Z_CLAMP_MIN__SHIFT 0 @@ -4034,13 +4474,15 @@ static inline uint32_t A6XX_RB_BLIT_SCISSOR_BR_Y(uint32_t val) #define A6XX_RB_BIN_CONTROL2_BINW__SHIFT 0 static inline uint32_t A6XX_RB_BIN_CONTROL2_BINW(uint32_t val) { - return ((val >> 5) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A6XX_RB_BIN_CONTROL2_BINW__SHIFT) & A6XX_RB_BIN_CONTROL2_BINW__MASK; } #define A6XX_RB_BIN_CONTROL2_BINH__MASK 0x00007f00 #define A6XX_RB_BIN_CONTROL2_BINH__SHIFT 8 static inline uint32_t A6XX_RB_BIN_CONTROL2_BINH(uint32_t val) { - return ((val >> 4) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK; + assert(!(val & 0xf)); + return (((val >> 4)) << A6XX_RB_BIN_CONTROL2_BINH__SHIFT) & A6XX_RB_BIN_CONTROL2_BINH__MASK; } #define REG_A6XX_RB_WINDOW_OFFSET2 0x000088d4 @@ -4066,12 +4508,6 @@ static inline uint32_t A6XX_RB_BLIT_GMEM_MSAA_CNTL_SAMPLES(enum a3xx_msaa_sample } #define REG_A6XX_RB_BLIT_BASE_GMEM 0x000088d6 -#define A6XX_RB_BLIT_BASE_GMEM__MASK 0xfffff000 -#define A6XX_RB_BLIT_BASE_GMEM__SHIFT 12 -static inline uint32_t A6XX_RB_BLIT_BASE_GMEM(uint32_t val) -{ - return ((val >> 12) << A6XX_RB_BLIT_BASE_GMEM__SHIFT) & A6XX_RB_BLIT_BASE_GMEM__MASK; -} #define REG_A6XX_RB_BLIT_DST_INFO 0x000088d7 #define A6XX_RB_BLIT_DST_INFO_TILE_MODE__MASK 0x00000003 @@ -4102,19 +4538,14 @@ static inline uint32_t A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(enum a6xx_format val) #define A6XX_RB_BLIT_DST_INFO_UNK15 0x00008000 #define REG_A6XX_RB_BLIT_DST 0x000088d8 -#define A6XX_RB_BLIT_DST__MASK 0xffffffff -#define A6XX_RB_BLIT_DST__SHIFT 0 -static inline uint32_t A6XX_RB_BLIT_DST(uint32_t val) -{ - return ((val) << A6XX_RB_BLIT_DST__SHIFT) & A6XX_RB_BLIT_DST__MASK; -} #define REG_A6XX_RB_BLIT_DST_PITCH 0x000088da #define A6XX_RB_BLIT_DST_PITCH__MASK 0x0000ffff #define A6XX_RB_BLIT_DST_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_BLIT_DST_PITCH__SHIFT) & A6XX_RB_BLIT_DST_PITCH__MASK; } #define REG_A6XX_RB_BLIT_DST_ARRAY_PITCH 0x000088db @@ -4122,29 +4553,26 @@ static inline uint32_t A6XX_RB_BLIT_DST_PITCH(uint32_t val) #define A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_BLIT_DST_ARRAY_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_BLIT_DST_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_DST_ARRAY_PITCH__MASK; } #define REG_A6XX_RB_BLIT_FLAG_DST 0x000088dc -#define A6XX_RB_BLIT_FLAG_DST__MASK 0xffffffff -#define A6XX_RB_BLIT_FLAG_DST__SHIFT 0 -static inline uint32_t A6XX_RB_BLIT_FLAG_DST(uint32_t val) -{ - return ((val) << A6XX_RB_BLIT_FLAG_DST__SHIFT) & A6XX_RB_BLIT_FLAG_DST__MASK; -} #define REG_A6XX_RB_BLIT_FLAG_DST_PITCH 0x000088de #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK 0x000007ff #define A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_PITCH__MASK; } #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK 0x0ffff800 #define A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT 11 static inline uint32_t A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH(uint32_t val) { - return ((val >> 7) << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK; + assert(!(val & 0x7f)); + return (((val >> 7)) << A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_BLIT_FLAG_DST_PITCH_ARRAY_PITCH__MASK; } #define REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0 0x000088df @@ -4179,46 +4607,82 @@ static inline uint32_t A6XX_RB_BLIT_INFO_BUFFER_ID(uint32_t val) return ((val) << A6XX_RB_BLIT_INFO_BUFFER_ID__SHIFT) & A6XX_RB_BLIT_INFO_BUFFER_ID__MASK; } -#define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0 +#define REG_A7XX_RB_UNKNOWN_88E4 0x000088e4 +#define A7XX_RB_UNKNOWN_88E4_UNK0 0x00000001 -#define REG_A6XX_RB_UNK_FLAG_BUFFER_BASE 0x000088f1 -#define A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK 0xffffffff -#define A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT 0 -static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_BASE(uint32_t val) +#define REG_A7XX_RB_CCU_CNTL2 0x000088e5 +#define A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__MASK 0x00000001 +#define A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__SHIFT 0 +static inline uint32_t A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI(uint32_t val) +{ + return ((val) << A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__SHIFT) & A7XX_RB_CCU_CNTL2_DEPTH_OFFSET_HI__MASK; +} +#define A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__MASK 0x00000004 +#define A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__SHIFT 2 +static inline uint32_t A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI(uint32_t val) { - return ((val) << A6XX_RB_UNK_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_BASE__MASK; + return ((val) << A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__SHIFT) & A7XX_RB_CCU_CNTL2_COLOR_OFFSET_HI__MASK; +} +#define A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__MASK 0x00000c00 +#define A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__SHIFT 10 +static inline uint32_t A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE(enum a6xx_ccu_cache_size val) +{ + return ((val) << A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__SHIFT) & A7XX_RB_CCU_CNTL2_DEPTH_CACHE_SIZE__MASK; +} +#define A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__MASK 0x001ff000 +#define A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__SHIFT 12 +static inline uint32_t A7XX_RB_CCU_CNTL2_DEPTH_OFFSET(uint32_t val) +{ + assert(!(val & 0xfff)); + return (((val >> 12)) << A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__SHIFT) & A7XX_RB_CCU_CNTL2_DEPTH_OFFSET__MASK; +} +#define A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__MASK 0x00600000 +#define A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__SHIFT 21 +static inline uint32_t A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE(enum a6xx_ccu_cache_size val) +{ + return ((val) << A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__SHIFT) & A7XX_RB_CCU_CNTL2_COLOR_CACHE_SIZE__MASK; +} +#define A7XX_RB_CCU_CNTL2_COLOR_OFFSET__MASK 0xff800000 +#define A7XX_RB_CCU_CNTL2_COLOR_OFFSET__SHIFT 23 +static inline uint32_t A7XX_RB_CCU_CNTL2_COLOR_OFFSET(uint32_t val) +{ + assert(!(val & 0xfff)); + return (((val >> 12)) << A7XX_RB_CCU_CNTL2_COLOR_OFFSET__SHIFT) & A7XX_RB_CCU_CNTL2_COLOR_OFFSET__MASK; } +#define REG_A6XX_RB_UNKNOWN_88F0 0x000088f0 + +#define REG_A6XX_RB_UNK_FLAG_BUFFER_BASE 0x000088f1 + #define REG_A6XX_RB_UNK_FLAG_BUFFER_PITCH 0x000088f3 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_PITCH__MASK; } #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x00fff800 #define A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 static inline uint32_t A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) { - return ((val >> 7) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; + assert(!(val & 0x7f)); + return (((val >> 7)) << A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_UNK_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; } #define REG_A6XX_RB_UNKNOWN_88F4 0x000088f4 +#define REG_A7XX_RB_UNKNOWN_88F5 0x000088f5 + #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE 0x00008900 -#define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK 0xffffffff -#define A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT 0 -static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_BASE(uint32_t val) -{ - return ((val) << A6XX_RB_DEPTH_FLAG_BUFFER_BASE__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_BASE__MASK; -} #define REG_A6XX_RB_DEPTH_FLAG_BUFFER_PITCH 0x00008902 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK 0x0000007f #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH__MASK; } #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__MASK 0x00000700 #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8__SHIFT 8 @@ -4230,40 +4694,31 @@ static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_UNK8(uint32_t val) #define A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 static inline uint32_t A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) { - return ((val >> 7) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; + assert(!(val & 0x7f)); + return (((val >> 7)) << A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; } -static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) { return 0x00008903 + 0x3*i0; } +#define REG_A6XX_RB_MRT_FLAG_BUFFER(i0) (0x00008903 + 0x3*(i0)) static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) { return 0x00008903 + 0x3*i0; } -#define A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK 0xffffffff -#define A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT 0 -static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t val) -{ - return ((val) << A6XX_RB_MRT_FLAG_BUFFER_ADDR__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_ADDR__MASK; -} static inline uint32_t REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) { return 0x00008905 + 0x3*i0; } #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK 0x000007ff #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_PITCH__MASK; } #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK 0x1ffff800 #define A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT 11 static inline uint32_t A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH(uint32_t val) { - return ((val >> 7) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; + assert(!(val & 0x7f)); + return (((val >> 7)) << A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__SHIFT) & A6XX_RB_MRT_FLAG_BUFFER_PITCH_ARRAY_PITCH__MASK; } #define REG_A6XX_RB_SAMPLE_COUNT_ADDR 0x00008927 -#define A6XX_RB_SAMPLE_COUNT_ADDR__MASK 0xffffffff -#define A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT 0 -static inline uint32_t A6XX_RB_SAMPLE_COUNT_ADDR(uint32_t val) -{ - return ((val) << A6XX_RB_SAMPLE_COUNT_ADDR__SHIFT) & A6XX_RB_SAMPLE_COUNT_ADDR__MASK; -} #define REG_A6XX_RB_UNKNOWN_8A00 0x00008a00 @@ -4320,6 +4775,7 @@ static inline uint32_t A6XX_RB_2D_BLIT_CNTL_RASTER_MODE(enum a6xx_raster_mode va { return ((val) << A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__SHIFT) & A6XX_RB_2D_BLIT_CNTL_RASTER_MODE__MASK; } +#define A6XX_RB_2D_BLIT_CNTL_UNK30 0x40000000 #define REG_A6XX_RB_2D_UNKNOWN_8C01 0x00008c01 @@ -4366,75 +4822,49 @@ static inline uint32_t A6XX_RB_2D_DST_INFO_UNK23(uint32_t val) #define A6XX_RB_2D_DST_INFO_UNK28 0x10000000 #define REG_A6XX_RB_2D_DST 0x00008c18 -#define A6XX_RB_2D_DST__MASK 0xffffffff -#define A6XX_RB_2D_DST__SHIFT 0 -static inline uint32_t A6XX_RB_2D_DST(uint32_t val) -{ - return ((val) << A6XX_RB_2D_DST__SHIFT) & A6XX_RB_2D_DST__MASK; -} #define REG_A6XX_RB_2D_DST_PITCH 0x00008c1a #define A6XX_RB_2D_DST_PITCH__MASK 0x0000ffff #define A6XX_RB_2D_DST_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_2D_DST_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_2D_DST_PITCH__SHIFT) & A6XX_RB_2D_DST_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_2D_DST_PITCH__SHIFT) & A6XX_RB_2D_DST_PITCH__MASK; } #define REG_A6XX_RB_2D_DST_PLANE1 0x00008c1b -#define A6XX_RB_2D_DST_PLANE1__MASK 0xffffffff -#define A6XX_RB_2D_DST_PLANE1__SHIFT 0 -static inline uint32_t A6XX_RB_2D_DST_PLANE1(uint32_t val) -{ - return ((val) << A6XX_RB_2D_DST_PLANE1__SHIFT) & A6XX_RB_2D_DST_PLANE1__MASK; -} #define REG_A6XX_RB_2D_DST_PLANE_PITCH 0x00008c1d #define A6XX_RB_2D_DST_PLANE_PITCH__MASK 0x0000ffff #define A6XX_RB_2D_DST_PLANE_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_2D_DST_PLANE_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_2D_DST_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_PLANE_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_2D_DST_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_PLANE_PITCH__MASK; } #define REG_A6XX_RB_2D_DST_PLANE2 0x00008c1e -#define A6XX_RB_2D_DST_PLANE2__MASK 0xffffffff -#define A6XX_RB_2D_DST_PLANE2__SHIFT 0 -static inline uint32_t A6XX_RB_2D_DST_PLANE2(uint32_t val) -{ - return ((val) << A6XX_RB_2D_DST_PLANE2__SHIFT) & A6XX_RB_2D_DST_PLANE2__MASK; -} #define REG_A6XX_RB_2D_DST_FLAGS 0x00008c20 -#define A6XX_RB_2D_DST_FLAGS__MASK 0xffffffff -#define A6XX_RB_2D_DST_FLAGS__SHIFT 0 -static inline uint32_t A6XX_RB_2D_DST_FLAGS(uint32_t val) -{ - return ((val) << A6XX_RB_2D_DST_FLAGS__SHIFT) & A6XX_RB_2D_DST_FLAGS__MASK; -} #define REG_A6XX_RB_2D_DST_FLAGS_PITCH 0x00008c22 #define A6XX_RB_2D_DST_FLAGS_PITCH__MASK 0x000000ff #define A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_2D_DST_FLAGS_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_2D_DST_FLAGS_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PITCH__MASK; } #define REG_A6XX_RB_2D_DST_FLAGS_PLANE 0x00008c23 -#define A6XX_RB_2D_DST_FLAGS_PLANE__MASK 0xffffffff -#define A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT 0 -static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE(uint32_t val) -{ - return ((val) << A6XX_RB_2D_DST_FLAGS_PLANE__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE__MASK; -} #define REG_A6XX_RB_2D_DST_FLAGS_PLANE_PITCH 0x00008c25 #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK 0x000000ff #define A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT 0 static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__SHIFT) & A6XX_RB_2D_DST_FLAGS_PLANE_PITCH__MASK; } #define REG_A6XX_RB_2D_SRC_SOLID_C0 0x00008c2c @@ -4451,7 +4881,10 @@ static inline uint32_t A6XX_RB_2D_DST_FLAGS_PLANE_PITCH(uint32_t val) #define REG_A6XX_RB_ADDR_MODE_CNTL 0x00008e05 +#define REG_A7XX_RB_UNKNOWN_8E06 0x00008e06 + #define REG_A6XX_RB_CCU_CNTL 0x00008e07 +#define A6XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE 0x00000001 #define A6XX_RB_CCU_CNTL_CONCURRENT_RESOLVE 0x00000004 #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__MASK 0x00000080 #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET_HI__SHIFT 7 @@ -4465,20 +4898,37 @@ static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI(uint32_t val) { return ((val) << A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET_HI__MASK; } +#define A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__MASK 0x00000c00 +#define A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__SHIFT 10 +static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE(enum a6xx_ccu_cache_size val) +{ + return ((val) << A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_CACHE_SIZE__MASK; +} #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK 0x001ff000 #define A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT 12 static inline uint32_t A6XX_RB_CCU_CNTL_DEPTH_OFFSET(uint32_t val) { - return ((val >> 12) << A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A6XX_RB_CCU_CNTL_DEPTH_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_DEPTH_OFFSET__MASK; +} +#define A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__MASK 0x00600000 +#define A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__SHIFT 21 +static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE(enum a6xx_ccu_cache_size val) +{ + return ((val) << A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_CACHE_SIZE__MASK; } -#define A6XX_RB_CCU_CNTL_GMEM 0x00400000 #define A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK 0xff800000 #define A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT 23 static inline uint32_t A6XX_RB_CCU_CNTL_COLOR_OFFSET(uint32_t val) { - return ((val >> 12) << A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A6XX_RB_CCU_CNTL_COLOR_OFFSET__SHIFT) & A6XX_RB_CCU_CNTL_COLOR_OFFSET__MASK; } +#define REG_A7XX_RB_CCU_CNTL 0x00008e07 +#define A7XX_RB_CCU_CNTL_GMEM_FAST_CLEAR_DISABLE 0x00000001 +#define A7XX_RB_CCU_CNTL_CONCURRENT_RESOLVE 0x00000004 + #define REG_A6XX_RB_NC_MODE_CNTL 0x00008e08 #define A6XX_RB_NC_MODE_CNTL_MODE 0x00000001 #define A6XX_RB_NC_MODE_CNTL_LOWER_BIT__MASK 0x00000006 @@ -4503,15 +4953,17 @@ static inline uint32_t A6XX_RB_NC_MODE_CNTL_UNK12(uint32_t val) return ((val) << A6XX_RB_NC_MODE_CNTL_UNK12__SHIFT) & A6XX_RB_NC_MODE_CNTL_UNK12__MASK; } -static inline uint32_t REG_A6XX_RB_PERFCTR_RB_SEL(uint32_t i0) { return 0x00008e10 + 0x1*i0; } +#define REG_A7XX_RB_UNKNOWN_8E09 0x00008e09 + +#define REG_A6XX_RB_PERFCTR_RB_SEL(i0) (0x00008e10 + 0x1*(i0)) -static inline uint32_t REG_A6XX_RB_PERFCTR_CCU_SEL(uint32_t i0) { return 0x00008e18 + 0x1*i0; } +#define REG_A6XX_RB_PERFCTR_CCU_SEL(i0) (0x00008e18 + 0x1*(i0)) #define REG_A6XX_RB_UNKNOWN_8E28 0x00008e28 -static inline uint32_t REG_A6XX_RB_PERFCTR_CMP_SEL(uint32_t i0) { return 0x00008e2c + 0x1*i0; } +#define REG_A6XX_RB_PERFCTR_CMP_SEL(i0) (0x00008e2c + 0x1*(i0)) -static inline uint32_t REG_A7XX_RB_PERFCTR_UFC_SEL(uint32_t i0) { return 0x00008e30 + 0x1*i0; } +#define REG_A7XX_RB_PERFCTR_UFC_SEL(i0) (0x00008e30 + 0x1*(i0)) #define REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST 0x00008e3b @@ -4520,12 +4972,8 @@ static inline uint32_t REG_A7XX_RB_PERFCTR_UFC_SEL(uint32_t i0) { return 0x00008 #define REG_A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE 0x00008e50 #define REG_A6XX_RB_UNKNOWN_8E51 0x00008e51 -#define A6XX_RB_UNKNOWN_8E51__MASK 0xffffffff -#define A6XX_RB_UNKNOWN_8E51__SHIFT 0 -static inline uint32_t A6XX_RB_UNKNOWN_8E51(uint32_t val) -{ - return ((val) << A6XX_RB_UNKNOWN_8E51__SHIFT) & A6XX_RB_UNKNOWN_8E51__MASK; -} + +#define REG_A7XX_RB_UNKNOWN_8E79 0x00008e79 #define REG_A6XX_VPC_GS_PARAM 0x00009100 #define A6XX_VPC_GS_PARAM_LINELENGTHLOC__MASK 0x000000ff @@ -4595,6 +5043,66 @@ static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC(uint32_t val) return ((val) << A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_CLIP_DIST_47_LOC__MASK; } +#define REG_A6XX_VPC_VS_CLIP_CNTL_V2 0x00009311 +#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__MASK 0x000000ff +#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__SHIFT 0 +static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK(uint32_t val) +{ + return ((val) << A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_MASK__MASK; +} +#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK 0x0000ff00 +#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT 8 +static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(uint32_t val) +{ + return ((val) << A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK; +} +#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK 0x00ff0000 +#define A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT 16 +static inline uint32_t A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(uint32_t val) +{ + return ((val) << A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_VS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK; +} + +#define REG_A6XX_VPC_GS_CLIP_CNTL_V2 0x00009312 +#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__MASK 0x000000ff +#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__SHIFT 0 +static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK(uint32_t val) +{ + return ((val) << A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_MASK__MASK; +} +#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK 0x0000ff00 +#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT 8 +static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(uint32_t val) +{ + return ((val) << A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK; +} +#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK 0x00ff0000 +#define A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT 16 +static inline uint32_t A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(uint32_t val) +{ + return ((val) << A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_GS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK; +} + +#define REG_A6XX_VPC_DS_CLIP_CNTL_V2 0x00009313 +#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__MASK 0x000000ff +#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__SHIFT 0 +static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK(uint32_t val) +{ + return ((val) << A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_MASK__MASK; +} +#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK 0x0000ff00 +#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT 8 +static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC(uint32_t val) +{ + return ((val) << A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_03_LOC__MASK; +} +#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK 0x00ff0000 +#define A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT 16 +static inline uint32_t A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC(uint32_t val) +{ + return ((val) << A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__SHIFT) & A6XX_VPC_DS_CLIP_CNTL_V2_CLIP_DIST_47_LOC__MASK; +} + #define REG_A6XX_VPC_VS_LAYER_CNTL 0x00009104 #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff #define A6XX_VPC_VS_LAYER_CNTL_LAYERLOC__SHIFT 0 @@ -4608,6 +5116,12 @@ static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_VIEWLOC(uint32_t val) { return ((val) << A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_VIEWLOC__MASK; } +#define A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__MASK 0x00ff0000 +#define A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__SHIFT 16 +static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC(uint32_t val) +{ + return ((val) << A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_SHADINGRATELOC__MASK; +} #define REG_A6XX_VPC_GS_LAYER_CNTL 0x00009105 #define A6XX_VPC_GS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff @@ -4622,6 +5136,12 @@ static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_VIEWLOC(uint32_t val) { return ((val) << A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_VIEWLOC__MASK; } +#define A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__MASK 0x00ff0000 +#define A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__SHIFT 16 +static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC(uint32_t val) +{ + return ((val) << A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_SHADINGRATELOC__MASK; +} #define REG_A6XX_VPC_DS_LAYER_CNTL 0x00009106 #define A6XX_VPC_DS_LAYER_CNTL_LAYERLOC__MASK 0x000000ff @@ -4636,6 +5156,72 @@ static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_VIEWLOC(uint32_t val) { return ((val) << A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_VIEWLOC__MASK; } +#define A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__MASK 0x00ff0000 +#define A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__SHIFT 16 +static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC(uint32_t val) +{ + return ((val) << A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_SHADINGRATELOC__MASK; +} + +#define REG_A6XX_VPC_VS_LAYER_CNTL_V2 0x00009314 +#define A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__MASK 0x000000ff +#define A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__SHIFT 0 +static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC(uint32_t val) +{ + return ((val) << A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_V2_LAYERLOC__MASK; +} +#define A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__MASK 0x0000ff00 +#define A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__SHIFT 8 +static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC(uint32_t val) +{ + return ((val) << A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_V2_VIEWLOC__MASK; +} +#define A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__MASK 0x00ff0000 +#define A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT 16 +static inline uint32_t A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC(uint32_t val) +{ + return ((val) << A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT) & A6XX_VPC_VS_LAYER_CNTL_V2_SHADINGRATELOC__MASK; +} + +#define REG_A6XX_VPC_GS_LAYER_CNTL_V2 0x00009315 +#define A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__MASK 0x000000ff +#define A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__SHIFT 0 +static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC(uint32_t val) +{ + return ((val) << A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_V2_LAYERLOC__MASK; +} +#define A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__MASK 0x0000ff00 +#define A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__SHIFT 8 +static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC(uint32_t val) +{ + return ((val) << A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_V2_VIEWLOC__MASK; +} +#define A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__MASK 0x00ff0000 +#define A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT 16 +static inline uint32_t A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC(uint32_t val) +{ + return ((val) << A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT) & A6XX_VPC_GS_LAYER_CNTL_V2_SHADINGRATELOC__MASK; +} + +#define REG_A6XX_VPC_DS_LAYER_CNTL_V2 0x00009316 +#define A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__MASK 0x000000ff +#define A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__SHIFT 0 +static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC(uint32_t val) +{ + return ((val) << A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_V2_LAYERLOC__MASK; +} +#define A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__MASK 0x0000ff00 +#define A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__SHIFT 8 +static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC(uint32_t val) +{ + return ((val) << A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_V2_VIEWLOC__MASK; +} +#define A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__MASK 0x00ff0000 +#define A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT 16 +static inline uint32_t A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC(uint32_t val) +{ + return ((val) << A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__SHIFT) & A6XX_VPC_DS_LAYER_CNTL_V2_SHADINGRATELOC__MASK; +} #define REG_A6XX_VPC_UNKNOWN_9107 0x00009107 #define A6XX_VPC_UNKNOWN_9107_RASTER_DISCARD 0x00000001 @@ -4649,11 +5235,51 @@ static inline uint32_t A6XX_VPC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) return ((val) << A6XX_VPC_POLYGON_MODE_MODE__SHIFT) & A6XX_VPC_POLYGON_MODE_MODE__MASK; } -static inline uint32_t REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00009200 + 0x1*i0; } +#define REG_A7XX_VPC_PRIMITIVE_CNTL_0 0x00009109 +#define A7XX_VPC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001 +#define A7XX_VPC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002 +#define A7XX_VPC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING 0x00000004 +#define A7XX_VPC_PRIMITIVE_CNTL_0_UNK3 0x00000008 + +#define REG_A7XX_VPC_PRIMITIVE_CNTL_5 0x0000910a +#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK 0x000000ff +#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT 0 +static inline uint32_t A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT(uint32_t val) +{ + return ((val) << A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__SHIFT) & A7XX_VPC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK; +} +#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK 0x00007c00 +#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT 10 +static inline uint32_t A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS(uint32_t val) +{ + return ((val) << A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__SHIFT) & A7XX_VPC_PRIMITIVE_CNTL_5_GS_INVOCATIONS__MASK; +} +#define A7XX_VPC_PRIMITIVE_CNTL_5_LINELENGTHEN 0x00008000 +#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK 0x00030000 +#define A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT 16 +static inline uint32_t A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output val) +{ + return ((val) << A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A7XX_VPC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK; +} +#define A7XX_VPC_PRIMITIVE_CNTL_5_UNK18 0x00040000 + +#define REG_A7XX_VPC_MULTIVIEW_MASK 0x0000910b + +#define REG_A7XX_VPC_MULTIVIEW_CNTL 0x0000910c +#define A7XX_VPC_MULTIVIEW_CNTL_ENABLE 0x00000001 +#define A7XX_VPC_MULTIVIEW_CNTL_DISABLEMULTIPOS 0x00000002 +#define A7XX_VPC_MULTIVIEW_CNTL_VIEWS__MASK 0x0000007c +#define A7XX_VPC_MULTIVIEW_CNTL_VIEWS__SHIFT 2 +static inline uint32_t A7XX_VPC_MULTIVIEW_CNTL_VIEWS(uint32_t val) +{ + return ((val) << A7XX_VPC_MULTIVIEW_CNTL_VIEWS__SHIFT) & A7XX_VPC_MULTIVIEW_CNTL_VIEWS__MASK; +} + +#define REG_A6XX_VPC_VARYING_INTERP(i0) (0x00009200 + 0x1*(i0)) static inline uint32_t REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00009200 + 0x1*i0; } -static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00009208 + 0x1*i0; } +#define REG_A6XX_VPC_VARYING_PS_REPL(i0) (0x00009208 + 0x1*(i0)) static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00009208 + 0x1*i0; } @@ -4661,7 +5287,7 @@ static inline uint32_t REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0 #define REG_A6XX_VPC_UNKNOWN_9211 0x00009211 -static inline uint32_t REG_A6XX_VPC_VAR(uint32_t i0) { return 0x00009212 + 0x1*i0; } +#define REG_A6XX_VPC_VAR(i0) (0x00009212 + 0x1*(i0)) static inline uint32_t REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) { return 0x00009212 + 0x1*i0; } @@ -4685,7 +5311,8 @@ static inline uint32_t A6XX_VPC_SO_PROG_A_BUF(uint32_t val) #define A6XX_VPC_SO_PROG_A_OFF__SHIFT 2 static inline uint32_t A6XX_VPC_SO_PROG_A_OFF(uint32_t val) { - return ((val >> 2) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_VPC_SO_PROG_A_OFF__SHIFT) & A6XX_VPC_SO_PROG_A_OFF__MASK; } #define A6XX_VPC_SO_PROG_A_EN 0x00000800 #define A6XX_VPC_SO_PROG_B_BUF__MASK 0x00003000 @@ -4698,59 +5325,24 @@ static inline uint32_t A6XX_VPC_SO_PROG_B_BUF(uint32_t val) #define A6XX_VPC_SO_PROG_B_OFF__SHIFT 14 static inline uint32_t A6XX_VPC_SO_PROG_B_OFF(uint32_t val) { - return ((val >> 2) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_VPC_SO_PROG_B_OFF__SHIFT) & A6XX_VPC_SO_PROG_B_OFF__MASK; } #define A6XX_VPC_SO_PROG_B_EN 0x00800000 #define REG_A6XX_VPC_SO_STREAM_COUNTS 0x00009218 -#define A6XX_VPC_SO_STREAM_COUNTS__MASK 0xffffffff -#define A6XX_VPC_SO_STREAM_COUNTS__SHIFT 0 -static inline uint32_t A6XX_VPC_SO_STREAM_COUNTS(uint32_t val) -{ - return ((val) << A6XX_VPC_SO_STREAM_COUNTS__SHIFT) & A6XX_VPC_SO_STREAM_COUNTS__MASK; -} -static inline uint32_t REG_A6XX_VPC_SO(uint32_t i0) { return 0x0000921a + 0x7*i0; } +#define REG_A6XX_VPC_SO(i0) (0x0000921a + 0x7*(i0)) static inline uint32_t REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) { return 0x0000921a + 0x7*i0; } -#define A6XX_VPC_SO_BUFFER_BASE__MASK 0xffffffff -#define A6XX_VPC_SO_BUFFER_BASE__SHIFT 0 -static inline uint32_t A6XX_VPC_SO_BUFFER_BASE(uint32_t val) -{ - return ((val) << A6XX_VPC_SO_BUFFER_BASE__SHIFT) & A6XX_VPC_SO_BUFFER_BASE__MASK; -} static inline uint32_t REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) { return 0x0000921c + 0x7*i0; } -#define A6XX_VPC_SO_BUFFER_SIZE__MASK 0xfffffffc -#define A6XX_VPC_SO_BUFFER_SIZE__SHIFT 2 -static inline uint32_t A6XX_VPC_SO_BUFFER_SIZE(uint32_t val) -{ - return ((val >> 2) << A6XX_VPC_SO_BUFFER_SIZE__SHIFT) & A6XX_VPC_SO_BUFFER_SIZE__MASK; -} static inline uint32_t REG_A6XX_VPC_SO_BUFFER_STRIDE(uint32_t i0) { return 0x0000921d + 0x7*i0; } -#define A6XX_VPC_SO_BUFFER_STRIDE__MASK 0x000003ff -#define A6XX_VPC_SO_BUFFER_STRIDE__SHIFT 0 -static inline uint32_t A6XX_VPC_SO_BUFFER_STRIDE(uint32_t val) -{ - return ((val >> 2) << A6XX_VPC_SO_BUFFER_STRIDE__SHIFT) & A6XX_VPC_SO_BUFFER_STRIDE__MASK; -} static inline uint32_t REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) { return 0x0000921e + 0x7*i0; } -#define A6XX_VPC_SO_BUFFER_OFFSET__MASK 0xfffffffc -#define A6XX_VPC_SO_BUFFER_OFFSET__SHIFT 2 -static inline uint32_t A6XX_VPC_SO_BUFFER_OFFSET(uint32_t val) -{ - return ((val >> 2) << A6XX_VPC_SO_BUFFER_OFFSET__SHIFT) & A6XX_VPC_SO_BUFFER_OFFSET__MASK; -} static inline uint32_t REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) { return 0x0000921f + 0x7*i0; } -#define A6XX_VPC_SO_FLUSH_BASE__MASK 0xffffffff -#define A6XX_VPC_SO_FLUSH_BASE__SHIFT 0 -static inline uint32_t A6XX_VPC_SO_FLUSH_BASE(uint32_t val) -{ - return ((val) << A6XX_VPC_SO_FLUSH_BASE__SHIFT) & A6XX_VPC_SO_FLUSH_BASE__MASK; -} #define REG_A6XX_VPC_POINT_COORD_INVERT 0x00009236 #define A6XX_VPC_POINT_COORD_INVERT_INVERT 0x00000001 @@ -4891,6 +5483,38 @@ static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val) #define REG_A6XX_VPC_SO_DISABLE 0x00009306 #define A6XX_VPC_SO_DISABLE_DISABLE 0x00000001 +#define REG_A7XX_VPC_POLYGON_MODE2 0x00009307 +#define A7XX_VPC_POLYGON_MODE2_MODE__MASK 0x00000003 +#define A7XX_VPC_POLYGON_MODE2_MODE__SHIFT 0 +static inline uint32_t A7XX_VPC_POLYGON_MODE2_MODE(enum a6xx_polygon_mode val) +{ + return ((val) << A7XX_VPC_POLYGON_MODE2_MODE__SHIFT) & A7XX_VPC_POLYGON_MODE2_MODE__MASK; +} + +#define REG_A7XX_VPC_ATTR_BUF_SIZE_GMEM 0x00009308 +#define A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK 0xffffffff +#define A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT 0 +static inline uint32_t A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM(uint32_t val) +{ + return ((val) << A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT) & A7XX_VPC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK; +} + +#define REG_A7XX_VPC_ATTR_BUF_BASE_GMEM 0x00009309 +#define A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__MASK 0xffffffff +#define A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__SHIFT 0 +static inline uint32_t A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM(uint32_t val) +{ + return ((val) << A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__SHIFT) & A7XX_VPC_ATTR_BUF_BASE_GMEM_BASE_GMEM__MASK; +} + +#define REG_A7XX_PC_ATTR_BUF_SIZE_GMEM 0x00009b09 +#define A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK 0xffffffff +#define A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT 0 +static inline uint32_t A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM(uint32_t val) +{ + return ((val) << A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__SHIFT) & A7XX_PC_ATTR_BUF_SIZE_GMEM_SIZE_GMEM__MASK; +} + #define REG_A6XX_VPC_DBG_ECO_CNTL 0x00009600 #define REG_A6XX_VPC_ADDR_MODE_CNTL 0x00009601 @@ -4899,9 +5523,9 @@ static inline uint32_t A6XX_VPC_SO_STREAM_CNTL_STREAM_ENABLE(uint32_t val) #define REG_A6XX_VPC_UNKNOWN_9603 0x00009603 -static inline uint32_t REG_A6XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x00009604 + 0x1*i0; } +#define REG_A6XX_VPC_PERFCTR_VPC_SEL(i0) (0x00009604 + 0x1*(i0)) -static inline uint32_t REG_A7XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) { return 0x0000960b + 0x1*i0; } +#define REG_A7XX_VPC_PERFCTR_VPC_SEL(i0) (0x0000960b + 0x1*(i0)) #define REG_A6XX_PC_TESS_NUM_VERTEX 0x00009800 @@ -4912,12 +5536,7 @@ static inline uint32_t A6XX_PC_HS_INPUT_SIZE_SIZE(uint32_t val) { return ((val) << A6XX_PC_HS_INPUT_SIZE_SIZE__SHIFT) & A6XX_PC_HS_INPUT_SIZE_SIZE__MASK; } -#define A6XX_PC_HS_INPUT_SIZE_UNK13__MASK 0x00002000 -#define A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT 13 -static inline uint32_t A6XX_PC_HS_INPUT_SIZE_UNK13(uint32_t val) -{ - return ((val) << A6XX_PC_HS_INPUT_SIZE_UNK13__SHIFT) & A6XX_PC_HS_INPUT_SIZE_UNK13__MASK; -} +#define A6XX_PC_HS_INPUT_SIZE_UNK13 0x00002000 #define REG_A6XX_PC_TESS_CNTL 0x00009802 #define A6XX_PC_TESS_CNTL_SPACING__MASK 0x00000003 @@ -4939,7 +5558,8 @@ static inline uint32_t A6XX_PC_TESS_CNTL_OUTPUT(enum a6xx_tess_output val) #define REG_A6XX_PC_POWER_CNTL 0x00009805 -#define REG_A6XX_PC_PRIMID_PASSTHRU 0x00009806 +#define REG_A6XX_PC_PS_CNTL 0x00009806 +#define A6XX_PC_PS_CNTL_PRIMITIVEIDEN 0x00000001 #define REG_A6XX_PC_SO_STREAM_CNTL 0x00009808 #define A6XX_PC_SO_STREAM_CNTL_STREAM_ENABLE__MASK 0x00078000 @@ -4992,6 +5612,14 @@ static inline uint32_t A6XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) return ((val) << A6XX_PC_POLYGON_MODE_MODE__SHIFT) & A6XX_PC_POLYGON_MODE_MODE__MASK; } +#define REG_A7XX_PC_POLYGON_MODE 0x00009809 +#define A7XX_PC_POLYGON_MODE_MODE__MASK 0x00000003 +#define A7XX_PC_POLYGON_MODE_MODE__SHIFT 0 +static inline uint32_t A7XX_PC_POLYGON_MODE_MODE(enum a6xx_polygon_mode val) +{ + return ((val) << A7XX_PC_POLYGON_MODE_MODE__SHIFT) & A7XX_PC_POLYGON_MODE_MODE__MASK; +} + #define REG_A6XX_PC_RASTER_CNTL 0x00009980 #define A6XX_PC_RASTER_CNTL_STREAM__MASK 0x00000003 #define A6XX_PC_RASTER_CNTL_STREAM__SHIFT 0 @@ -5001,10 +5629,28 @@ static inline uint32_t A6XX_PC_RASTER_CNTL_STREAM(uint32_t val) } #define A6XX_PC_RASTER_CNTL_DISCARD 0x00000004 +#define REG_A7XX_PC_RASTER_CNTL 0x00009107 +#define A7XX_PC_RASTER_CNTL_STREAM__MASK 0x00000003 +#define A7XX_PC_RASTER_CNTL_STREAM__SHIFT 0 +static inline uint32_t A7XX_PC_RASTER_CNTL_STREAM(uint32_t val) +{ + return ((val) << A7XX_PC_RASTER_CNTL_STREAM__SHIFT) & A7XX_PC_RASTER_CNTL_STREAM__MASK; +} +#define A7XX_PC_RASTER_CNTL_DISCARD 0x00000004 + +#define REG_A7XX_PC_RASTER_CNTL_V2 0x00009317 +#define A7XX_PC_RASTER_CNTL_V2_STREAM__MASK 0x00000003 +#define A7XX_PC_RASTER_CNTL_V2_STREAM__SHIFT 0 +static inline uint32_t A7XX_PC_RASTER_CNTL_V2_STREAM(uint32_t val) +{ + return ((val) << A7XX_PC_RASTER_CNTL_V2_STREAM__SHIFT) & A7XX_PC_RASTER_CNTL_V2_STREAM__MASK; +} +#define A7XX_PC_RASTER_CNTL_V2_DISCARD 0x00000004 + #define REG_A6XX_PC_PRIMITIVE_CNTL_0 0x00009b00 #define A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART 0x00000001 #define A6XX_PC_PRIMITIVE_CNTL_0_PROVOKING_VTX_LAST 0x00000002 -#define A6XX_PC_PRIMITIVE_CNTL_0_TESS_UPPER_LEFT_DOMAIN_ORIGIN 0x00000004 +#define A6XX_PC_PRIMITIVE_CNTL_0_D3D_VERTEX_ORDERING 0x00000004 #define A6XX_PC_PRIMITIVE_CNTL_0_UNK3 0x00000008 #define REG_A6XX_PC_VS_OUT_CNTL 0x00009b01 @@ -5024,6 +5670,7 @@ static inline uint32_t A6XX_PC_VS_OUT_CNTL_CLIP_MASK(uint32_t val) { return ((val) << A6XX_PC_VS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_VS_OUT_CNTL_CLIP_MASK__MASK; } +#define A6XX_PC_VS_OUT_CNTL_SHADINGRATE 0x01000000 #define REG_A6XX_PC_GS_OUT_CNTL 0x00009b02 #define A6XX_PC_GS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff @@ -5042,6 +5689,7 @@ static inline uint32_t A6XX_PC_GS_OUT_CNTL_CLIP_MASK(uint32_t val) { return ((val) << A6XX_PC_GS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_GS_OUT_CNTL_CLIP_MASK__MASK; } +#define A6XX_PC_GS_OUT_CNTL_SHADINGRATE 0x01000000 #define REG_A6XX_PC_HS_OUT_CNTL 0x00009b03 #define A6XX_PC_HS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff @@ -5060,6 +5708,7 @@ static inline uint32_t A6XX_PC_HS_OUT_CNTL_CLIP_MASK(uint32_t val) { return ((val) << A6XX_PC_HS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_HS_OUT_CNTL_CLIP_MASK__MASK; } +#define A6XX_PC_HS_OUT_CNTL_SHADINGRATE 0x01000000 #define REG_A6XX_PC_DS_OUT_CNTL 0x00009b04 #define A6XX_PC_DS_OUT_CNTL_STRIDE_IN_VPC__MASK 0x000000ff @@ -5078,6 +5727,7 @@ static inline uint32_t A6XX_PC_DS_OUT_CNTL_CLIP_MASK(uint32_t val) { return ((val) << A6XX_PC_DS_OUT_CNTL_CLIP_MASK__SHIFT) & A6XX_PC_DS_OUT_CNTL_CLIP_MASK__MASK; } +#define A6XX_PC_DS_OUT_CNTL_SHADINGRATE 0x01000000 #define REG_A6XX_PC_PRIMITIVE_CNTL_5 0x00009b05 #define A6XX_PC_PRIMITIVE_CNTL_5_GS_VERTICES_OUT__MASK 0x000000ff @@ -5099,12 +5749,7 @@ static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT(enum a6xx_tess_output { return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_GS_OUTPUT__MASK; } -#define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK 0x00040000 -#define A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT 18 -static inline uint32_t A6XX_PC_PRIMITIVE_CNTL_5_UNK18(uint32_t val) -{ - return ((val) << A6XX_PC_PRIMITIVE_CNTL_5_UNK18__SHIFT) & A6XX_PC_PRIMITIVE_CNTL_5_UNK18__MASK; -} +#define A6XX_PC_PRIMITIVE_CNTL_5_UNK18 0x00040000 #define REG_A6XX_PC_PRIMITIVE_CNTL_6 0x00009b06 #define A6XX_PC_PRIMITIVE_CNTL_6_STRIDE_IN_VPC__MASK 0x000007ff @@ -5151,12 +5796,8 @@ static inline uint32_t A6XX_PC_2D_EVENT_CMD_STATE_ID(uint32_t val) #define REG_A6XX_PC_DRAW_MAX_INDICES 0x00009e07 #define REG_A6XX_PC_TESSFACTOR_ADDR 0x00009e08 -#define A6XX_PC_TESSFACTOR_ADDR__MASK 0xffffffff -#define A6XX_PC_TESSFACTOR_ADDR__SHIFT 0 -static inline uint32_t A6XX_PC_TESSFACTOR_ADDR(uint32_t val) -{ - return ((val) << A6XX_PC_TESSFACTOR_ADDR__SHIFT) & A6XX_PC_TESSFACTOR_ADDR__MASK; -} + +#define REG_A7XX_PC_TESSFACTOR_ADDR 0x00009810 #define REG_A6XX_PC_DRAW_INITIATOR 0x00009e0b #define A6XX_PC_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f @@ -5217,27 +5858,17 @@ static inline uint32_t A6XX_PC_VSTREAM_CONTROL_VSC_N(uint32_t val) } #define REG_A6XX_PC_BIN_PRIM_STRM 0x00009e12 -#define A6XX_PC_BIN_PRIM_STRM__MASK 0xffffffff -#define A6XX_PC_BIN_PRIM_STRM__SHIFT 0 -static inline uint32_t A6XX_PC_BIN_PRIM_STRM(uint32_t val) -{ - return ((val) << A6XX_PC_BIN_PRIM_STRM__SHIFT) & A6XX_PC_BIN_PRIM_STRM__MASK; -} #define REG_A6XX_PC_BIN_DRAW_STRM 0x00009e14 -#define A6XX_PC_BIN_DRAW_STRM__MASK 0xffffffff -#define A6XX_PC_BIN_DRAW_STRM__SHIFT 0 -static inline uint32_t A6XX_PC_BIN_DRAW_STRM(uint32_t val) -{ - return ((val) << A6XX_PC_BIN_DRAW_STRM__SHIFT) & A6XX_PC_BIN_DRAW_STRM__MASK; -} #define REG_A6XX_PC_VISIBILITY_OVERRIDE 0x00009e1c #define A6XX_PC_VISIBILITY_OVERRIDE_OVERRIDE 0x00000001 -static inline uint32_t REG_A6XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e34 + 0x1*i0; } +#define REG_A7XX_PC_UNKNOWN_9E24 0x00009e24 + +#define REG_A6XX_PC_PERFCTR_PC_SEL(i0) (0x00009e34 + 0x1*(i0)) -static inline uint32_t REG_A7XX_PC_PERFCTR_PC_SEL(uint32_t i0) { return 0x00009e42 + 0x1*i0; } +#define REG_A7XX_PC_PERFCTR_PC_SEL(i0) (0x00009e42 + 0x1*(i0)) #define REG_A6XX_PC_UNKNOWN_9E72 0x00009e72 @@ -5344,7 +5975,7 @@ static inline uint32_t A6XX_VFD_CONTROL_5_UNK8(uint32_t val) } #define REG_A6XX_VFD_CONTROL_6 0x0000a006 -#define A6XX_VFD_CONTROL_6_PRIMID_PASSTHRU 0x00000001 +#define A6XX_VFD_CONTROL_6_PRIMID4PSEN 0x00000001 #define REG_A6XX_VFD_MODE_CNTL 0x0000a007 #define A6XX_VFD_MODE_CNTL_RENDER_MODE__MASK 0x00000007 @@ -5372,21 +6003,15 @@ static inline uint32_t A6XX_VFD_MULTIVIEW_CNTL_VIEWS(uint32_t val) #define REG_A6XX_VFD_INSTANCE_START_OFFSET 0x0000a00f -static inline uint32_t REG_A6XX_VFD_FETCH(uint32_t i0) { return 0x0000a010 + 0x4*i0; } +#define REG_A6XX_VFD_FETCH(i0) (0x0000a010 + 0x4*(i0)) static inline uint32_t REG_A6XX_VFD_FETCH_BASE(uint32_t i0) { return 0x0000a010 + 0x4*i0; } -#define A6XX_VFD_FETCH_BASE__MASK 0xffffffff -#define A6XX_VFD_FETCH_BASE__SHIFT 0 -static inline uint32_t A6XX_VFD_FETCH_BASE(uint32_t val) -{ - return ((val) << A6XX_VFD_FETCH_BASE__SHIFT) & A6XX_VFD_FETCH_BASE__MASK; -} static inline uint32_t REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) { return 0x0000a012 + 0x4*i0; } static inline uint32_t REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) { return 0x0000a013 + 0x4*i0; } -static inline uint32_t REG_A6XX_VFD_DECODE(uint32_t i0) { return 0x0000a090 + 0x2*i0; } +#define REG_A6XX_VFD_DECODE(i0) (0x0000a090 + 0x2*(i0)) static inline uint32_t REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x0000a090 + 0x2*i0; } #define A6XX_VFD_DECODE_INSTR_IDX__MASK 0x0000001f @@ -5419,7 +6044,7 @@ static inline uint32_t A6XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val) static inline uint32_t REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) { return 0x0000a091 + 0x2*i0; } -static inline uint32_t REG_A6XX_VFD_DEST_CNTL(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } +#define REG_A6XX_VFD_DEST_CNTL(i0) (0x0000a0d0 + 0x1*(i0)) static inline uint32_t REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) { return 0x0000a0d0 + 0x1*i0; } #define A6XX_VFD_DEST_CNTL_INSTR_WRITEMASK__MASK 0x0000000f @@ -5437,15 +6062,15 @@ static inline uint32_t A6XX_VFD_DEST_CNTL_INSTR_REGID(uint32_t val) #define REG_A6XX_VFD_POWER_CNTL 0x0000a0f8 +#define REG_A7XX_VFD_UNKNOWN_A600 0x0000a600 + #define REG_A6XX_VFD_ADDR_MODE_CNTL 0x0000a601 -static inline uint32_t REG_A6XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; } +#define REG_A6XX_VFD_PERFCTR_VFD_SEL(i0) (0x0000a610 + 0x1*(i0)) -static inline uint32_t REG_A7XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) { return 0x0000a610 + 0x1*i0; } +#define REG_A7XX_VFD_PERFCTR_VFD_SEL(i0) (0x0000a610 + 0x1*(i0)) #define REG_A6XX_SP_VS_CTRL_REG0 0x0000a800 -#define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x00100000 -#define A6XX_SP_VS_CTRL_REG0_EARLYPREAMBLE 0x00200000 #define A6XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001 #define A6XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0 static inline uint32_t A6XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) @@ -5471,6 +6096,8 @@ static inline uint32_t A6XX_SP_VS_CTRL_REG0_BRANCHSTACK(uint32_t val) { return ((val) << A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_VS_CTRL_REG0_BRANCHSTACK__MASK; } +#define A6XX_SP_VS_CTRL_REG0_MERGEDREGS 0x00100000 +#define A6XX_SP_VS_CTRL_REG0_EARLYPREAMBLE 0x00200000 #define REG_A6XX_SP_VS_BRANCH_COND 0x0000a801 @@ -5488,7 +6115,7 @@ static inline uint32_t A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) return ((val) << A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_VS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; } -static inline uint32_t REG_A6XX_SP_VS_OUT(uint32_t i0) { return 0x0000a803 + 0x1*i0; } +#define REG_A6XX_SP_VS_OUT(i0) (0x0000a803 + 0x1*(i0)) static inline uint32_t REG_A6XX_SP_VS_OUT_REG(uint32_t i0) { return 0x0000a803 + 0x1*i0; } #define A6XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff @@ -5516,7 +6143,7 @@ static inline uint32_t A6XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val) return ((val) << A6XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_VS_OUT_REG_B_COMPMASK__MASK; } -static inline uint32_t REG_A6XX_SP_VS_VPC_DST(uint32_t i0) { return 0x0000a813 + 0x1*i0; } +#define REG_A6XX_SP_VS_VPC_DST(i0) (0x0000a813 + 0x1*(i0)) static inline uint32_t REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x0000a813 + 0x1*i0; } #define A6XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff @@ -5547,19 +6174,14 @@ static inline uint32_t A6XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val) #define REG_A6XX_SP_VS_OBJ_FIRST_EXEC_OFFSET 0x0000a81b #define REG_A6XX_SP_VS_OBJ_START 0x0000a81c -#define A6XX_SP_VS_OBJ_START__MASK 0xffffffff -#define A6XX_SP_VS_OBJ_START__SHIFT 0 -static inline uint32_t A6XX_SP_VS_OBJ_START(uint32_t val) -{ - return ((val) << A6XX_SP_VS_OBJ_START__SHIFT) & A6XX_SP_VS_OBJ_START__MASK; -} #define REG_A6XX_SP_VS_PVT_MEM_PARAM 0x0000a81e #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff #define A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) { - return ((val >> 9) << A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; + assert(!(val & 0x1ff)); + return (((val >> 9)) << A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_VS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; } #define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 #define A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 @@ -5569,19 +6191,14 @@ static inline uint32_t A6XX_SP_VS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t va } #define REG_A6XX_SP_VS_PVT_MEM_ADDR 0x0000a81f -#define A6XX_SP_VS_PVT_MEM_ADDR__MASK 0xffffffff -#define A6XX_SP_VS_PVT_MEM_ADDR__SHIFT 0 -static inline uint32_t A6XX_SP_VS_PVT_MEM_ADDR(uint32_t val) -{ - return ((val) << A6XX_SP_VS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_VS_PVT_MEM_ADDR__MASK; -} #define REG_A6XX_SP_VS_PVT_MEM_SIZE 0x0000a821 #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff #define A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 static inline uint32_t A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) { - return ((val >> 12) << A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_VS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; } #define A6XX_SP_VS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 @@ -5619,11 +6236,13 @@ static inline uint32_t A6XX_SP_VS_CONFIG_NIBO(uint32_t val) #define A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 static inline uint32_t A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) { - return ((val >> 11) << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; + assert(!(val & 0x7ff)); + return (((val >> 11)) << A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_VS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; } +#define REG_A7XX_SP_VS_VGPR_CONFIG 0x0000a82d + #define REG_A6XX_SP_HS_CTRL_REG0 0x0000a830 -#define A6XX_SP_HS_CTRL_REG0_EARLYPREAMBLE 0x00100000 #define A6XX_SP_HS_CTRL_REG0_THREADMODE__MASK 0x00000001 #define A6XX_SP_HS_CTRL_REG0_THREADMODE__SHIFT 0 static inline uint32_t A6XX_SP_HS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) @@ -5649,6 +6268,7 @@ static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) { return ((val) << A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_HS_CTRL_REG0_BRANCHSTACK__MASK; } +#define A6XX_SP_HS_CTRL_REG0_EARLYPREAMBLE 0x00100000 #define REG_A6XX_SP_HS_WAVE_INPUT_SIZE 0x0000a831 @@ -5657,19 +6277,14 @@ static inline uint32_t A6XX_SP_HS_CTRL_REG0_BRANCHSTACK(uint32_t val) #define REG_A6XX_SP_HS_OBJ_FIRST_EXEC_OFFSET 0x0000a833 #define REG_A6XX_SP_HS_OBJ_START 0x0000a834 -#define A6XX_SP_HS_OBJ_START__MASK 0xffffffff -#define A6XX_SP_HS_OBJ_START__SHIFT 0 -static inline uint32_t A6XX_SP_HS_OBJ_START(uint32_t val) -{ - return ((val) << A6XX_SP_HS_OBJ_START__SHIFT) & A6XX_SP_HS_OBJ_START__MASK; -} #define REG_A6XX_SP_HS_PVT_MEM_PARAM 0x0000a836 #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff #define A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) { - return ((val >> 9) << A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; + assert(!(val & 0x1ff)); + return (((val >> 9)) << A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_HS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; } #define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 #define A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 @@ -5679,19 +6294,14 @@ static inline uint32_t A6XX_SP_HS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t va } #define REG_A6XX_SP_HS_PVT_MEM_ADDR 0x0000a837 -#define A6XX_SP_HS_PVT_MEM_ADDR__MASK 0xffffffff -#define A6XX_SP_HS_PVT_MEM_ADDR__SHIFT 0 -static inline uint32_t A6XX_SP_HS_PVT_MEM_ADDR(uint32_t val) -{ - return ((val) << A6XX_SP_HS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_HS_PVT_MEM_ADDR__MASK; -} #define REG_A6XX_SP_HS_PVT_MEM_SIZE 0x0000a839 #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff #define A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 static inline uint32_t A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) { - return ((val >> 12) << A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_HS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; } #define A6XX_SP_HS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 @@ -5729,11 +6339,13 @@ static inline uint32_t A6XX_SP_HS_CONFIG_NIBO(uint32_t val) #define A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 static inline uint32_t A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) { - return ((val >> 11) << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; + assert(!(val & 0x7ff)); + return (((val >> 11)) << A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_HS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; } +#define REG_A7XX_SP_HS_VGPR_CONFIG 0x0000a82f + #define REG_A6XX_SP_DS_CTRL_REG0 0x0000a840 -#define A6XX_SP_DS_CTRL_REG0_EARLYPREAMBLE 0x00100000 #define A6XX_SP_DS_CTRL_REG0_THREADMODE__MASK 0x00000001 #define A6XX_SP_DS_CTRL_REG0_THREADMODE__SHIFT 0 static inline uint32_t A6XX_SP_DS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) @@ -5759,6 +6371,7 @@ static inline uint32_t A6XX_SP_DS_CTRL_REG0_BRANCHSTACK(uint32_t val) { return ((val) << A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_DS_CTRL_REG0_BRANCHSTACK__MASK; } +#define A6XX_SP_DS_CTRL_REG0_EARLYPREAMBLE 0x00100000 #define REG_A6XX_SP_DS_BRANCH_COND 0x0000a841 @@ -5776,7 +6389,7 @@ static inline uint32_t A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) return ((val) << A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_DS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; } -static inline uint32_t REG_A6XX_SP_DS_OUT(uint32_t i0) { return 0x0000a843 + 0x1*i0; } +#define REG_A6XX_SP_DS_OUT(i0) (0x0000a843 + 0x1*(i0)) static inline uint32_t REG_A6XX_SP_DS_OUT_REG(uint32_t i0) { return 0x0000a843 + 0x1*i0; } #define A6XX_SP_DS_OUT_REG_A_REGID__MASK 0x000000ff @@ -5804,7 +6417,7 @@ static inline uint32_t A6XX_SP_DS_OUT_REG_B_COMPMASK(uint32_t val) return ((val) << A6XX_SP_DS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_DS_OUT_REG_B_COMPMASK__MASK; } -static inline uint32_t REG_A6XX_SP_DS_VPC_DST(uint32_t i0) { return 0x0000a853 + 0x1*i0; } +#define REG_A6XX_SP_DS_VPC_DST(i0) (0x0000a853 + 0x1*(i0)) static inline uint32_t REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) { return 0x0000a853 + 0x1*i0; } #define A6XX_SP_DS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff @@ -5835,19 +6448,14 @@ static inline uint32_t A6XX_SP_DS_VPC_DST_REG_OUTLOC3(uint32_t val) #define REG_A6XX_SP_DS_OBJ_FIRST_EXEC_OFFSET 0x0000a85b #define REG_A6XX_SP_DS_OBJ_START 0x0000a85c -#define A6XX_SP_DS_OBJ_START__MASK 0xffffffff -#define A6XX_SP_DS_OBJ_START__SHIFT 0 -static inline uint32_t A6XX_SP_DS_OBJ_START(uint32_t val) -{ - return ((val) << A6XX_SP_DS_OBJ_START__SHIFT) & A6XX_SP_DS_OBJ_START__MASK; -} #define REG_A6XX_SP_DS_PVT_MEM_PARAM 0x0000a85e #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff #define A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) { - return ((val >> 9) << A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; + assert(!(val & 0x1ff)); + return (((val >> 9)) << A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_DS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; } #define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 #define A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 @@ -5857,19 +6465,14 @@ static inline uint32_t A6XX_SP_DS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t va } #define REG_A6XX_SP_DS_PVT_MEM_ADDR 0x0000a85f -#define A6XX_SP_DS_PVT_MEM_ADDR__MASK 0xffffffff -#define A6XX_SP_DS_PVT_MEM_ADDR__SHIFT 0 -static inline uint32_t A6XX_SP_DS_PVT_MEM_ADDR(uint32_t val) -{ - return ((val) << A6XX_SP_DS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_DS_PVT_MEM_ADDR__MASK; -} #define REG_A6XX_SP_DS_PVT_MEM_SIZE 0x0000a861 #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff #define A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 static inline uint32_t A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) { - return ((val >> 12) << A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_DS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; } #define A6XX_SP_DS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 @@ -5907,11 +6510,13 @@ static inline uint32_t A6XX_SP_DS_CONFIG_NIBO(uint32_t val) #define A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 static inline uint32_t A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) { - return ((val >> 11) << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; + assert(!(val & 0x7ff)); + return (((val >> 11)) << A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_DS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; } +#define REG_A7XX_SP_DS_VGPR_CONFIG 0x0000a868 + #define REG_A6XX_SP_GS_CTRL_REG0 0x0000a870 -#define A6XX_SP_GS_CTRL_REG0_EARLYPREAMBLE 0x00100000 #define A6XX_SP_GS_CTRL_REG0_THREADMODE__MASK 0x00000001 #define A6XX_SP_GS_CTRL_REG0_THREADMODE__SHIFT 0 static inline uint32_t A6XX_SP_GS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) @@ -5937,6 +6542,7 @@ static inline uint32_t A6XX_SP_GS_CTRL_REG0_BRANCHSTACK(uint32_t val) { return ((val) << A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_GS_CTRL_REG0_BRANCHSTACK__MASK; } +#define A6XX_SP_GS_CTRL_REG0_EARLYPREAMBLE 0x00100000 #define REG_A6XX_SP_GS_PRIM_SIZE 0x0000a871 @@ -5956,7 +6562,7 @@ static inline uint32_t A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID(uint32_t val) return ((val) << A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__SHIFT) & A6XX_SP_GS_PRIMITIVE_CNTL_FLAGS_REGID__MASK; } -static inline uint32_t REG_A6XX_SP_GS_OUT(uint32_t i0) { return 0x0000a874 + 0x1*i0; } +#define REG_A6XX_SP_GS_OUT(i0) (0x0000a874 + 0x1*(i0)) static inline uint32_t REG_A6XX_SP_GS_OUT_REG(uint32_t i0) { return 0x0000a874 + 0x1*i0; } #define A6XX_SP_GS_OUT_REG_A_REGID__MASK 0x000000ff @@ -5984,7 +6590,7 @@ static inline uint32_t A6XX_SP_GS_OUT_REG_B_COMPMASK(uint32_t val) return ((val) << A6XX_SP_GS_OUT_REG_B_COMPMASK__SHIFT) & A6XX_SP_GS_OUT_REG_B_COMPMASK__MASK; } -static inline uint32_t REG_A6XX_SP_GS_VPC_DST(uint32_t i0) { return 0x0000a884 + 0x1*i0; } +#define REG_A6XX_SP_GS_VPC_DST(i0) (0x0000a884 + 0x1*(i0)) static inline uint32_t REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0) { return 0x0000a884 + 0x1*i0; } #define A6XX_SP_GS_VPC_DST_REG_OUTLOC0__MASK 0x000000ff @@ -6015,19 +6621,14 @@ static inline uint32_t A6XX_SP_GS_VPC_DST_REG_OUTLOC3(uint32_t val) #define REG_A6XX_SP_GS_OBJ_FIRST_EXEC_OFFSET 0x0000a88c #define REG_A6XX_SP_GS_OBJ_START 0x0000a88d -#define A6XX_SP_GS_OBJ_START__MASK 0xffffffff -#define A6XX_SP_GS_OBJ_START__SHIFT 0 -static inline uint32_t A6XX_SP_GS_OBJ_START(uint32_t val) -{ - return ((val) << A6XX_SP_GS_OBJ_START__SHIFT) & A6XX_SP_GS_OBJ_START__MASK; -} #define REG_A6XX_SP_GS_PVT_MEM_PARAM 0x0000a88f #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff #define A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) { - return ((val >> 9) << A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; + assert(!(val & 0x1ff)); + return (((val >> 9)) << A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_GS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; } #define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 #define A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 @@ -6037,19 +6638,14 @@ static inline uint32_t A6XX_SP_GS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t va } #define REG_A6XX_SP_GS_PVT_MEM_ADDR 0x0000a890 -#define A6XX_SP_GS_PVT_MEM_ADDR__MASK 0xffffffff -#define A6XX_SP_GS_PVT_MEM_ADDR__SHIFT 0 -static inline uint32_t A6XX_SP_GS_PVT_MEM_ADDR(uint32_t val) -{ - return ((val) << A6XX_SP_GS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_GS_PVT_MEM_ADDR__MASK; -} #define REG_A6XX_SP_GS_PVT_MEM_SIZE 0x0000a892 #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff #define A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 static inline uint32_t A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) { - return ((val >> 12) << A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_GS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; } #define A6XX_SP_GS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 @@ -6087,89 +6683,29 @@ static inline uint32_t A6XX_SP_GS_CONFIG_NIBO(uint32_t val) #define A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 static inline uint32_t A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) { - return ((val >> 11) << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; + assert(!(val & 0x7ff)); + return (((val >> 11)) << A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_GS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; } +#define REG_A7XX_SP_GS_VGPR_CONFIG 0x0000a899 + #define REG_A6XX_SP_VS_TEX_SAMP 0x0000a8a0 -#define A6XX_SP_VS_TEX_SAMP__MASK 0xffffffff -#define A6XX_SP_VS_TEX_SAMP__SHIFT 0 -static inline uint32_t A6XX_SP_VS_TEX_SAMP(uint32_t val) -{ - return ((val) << A6XX_SP_VS_TEX_SAMP__SHIFT) & A6XX_SP_VS_TEX_SAMP__MASK; -} #define REG_A6XX_SP_HS_TEX_SAMP 0x0000a8a2 -#define A6XX_SP_HS_TEX_SAMP__MASK 0xffffffff -#define A6XX_SP_HS_TEX_SAMP__SHIFT 0 -static inline uint32_t A6XX_SP_HS_TEX_SAMP(uint32_t val) -{ - return ((val) << A6XX_SP_HS_TEX_SAMP__SHIFT) & A6XX_SP_HS_TEX_SAMP__MASK; -} #define REG_A6XX_SP_DS_TEX_SAMP 0x0000a8a4 -#define A6XX_SP_DS_TEX_SAMP__MASK 0xffffffff -#define A6XX_SP_DS_TEX_SAMP__SHIFT 0 -static inline uint32_t A6XX_SP_DS_TEX_SAMP(uint32_t val) -{ - return ((val) << A6XX_SP_DS_TEX_SAMP__SHIFT) & A6XX_SP_DS_TEX_SAMP__MASK; -} #define REG_A6XX_SP_GS_TEX_SAMP 0x0000a8a6 -#define A6XX_SP_GS_TEX_SAMP__MASK 0xffffffff -#define A6XX_SP_GS_TEX_SAMP__SHIFT 0 -static inline uint32_t A6XX_SP_GS_TEX_SAMP(uint32_t val) -{ - return ((val) << A6XX_SP_GS_TEX_SAMP__SHIFT) & A6XX_SP_GS_TEX_SAMP__MASK; -} #define REG_A6XX_SP_VS_TEX_CONST 0x0000a8a8 -#define A6XX_SP_VS_TEX_CONST__MASK 0xffffffff -#define A6XX_SP_VS_TEX_CONST__SHIFT 0 -static inline uint32_t A6XX_SP_VS_TEX_CONST(uint32_t val) -{ - return ((val) << A6XX_SP_VS_TEX_CONST__SHIFT) & A6XX_SP_VS_TEX_CONST__MASK; -} #define REG_A6XX_SP_HS_TEX_CONST 0x0000a8aa -#define A6XX_SP_HS_TEX_CONST__MASK 0xffffffff -#define A6XX_SP_HS_TEX_CONST__SHIFT 0 -static inline uint32_t A6XX_SP_HS_TEX_CONST(uint32_t val) -{ - return ((val) << A6XX_SP_HS_TEX_CONST__SHIFT) & A6XX_SP_HS_TEX_CONST__MASK; -} #define REG_A6XX_SP_DS_TEX_CONST 0x0000a8ac -#define A6XX_SP_DS_TEX_CONST__MASK 0xffffffff -#define A6XX_SP_DS_TEX_CONST__SHIFT 0 -static inline uint32_t A6XX_SP_DS_TEX_CONST(uint32_t val) -{ - return ((val) << A6XX_SP_DS_TEX_CONST__SHIFT) & A6XX_SP_DS_TEX_CONST__MASK; -} #define REG_A6XX_SP_GS_TEX_CONST 0x0000a8ae -#define A6XX_SP_GS_TEX_CONST__MASK 0xffffffff -#define A6XX_SP_GS_TEX_CONST__SHIFT 0 -static inline uint32_t A6XX_SP_GS_TEX_CONST(uint32_t val) -{ - return ((val) << A6XX_SP_GS_TEX_CONST__SHIFT) & A6XX_SP_GS_TEX_CONST__MASK; -} #define REG_A6XX_SP_FS_CTRL_REG0 0x0000a980 -#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 -#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 -static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) -{ - return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; -} -#define A6XX_SP_FS_CTRL_REG0_UNK21 0x00200000 -#define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000 -#define A6XX_SP_FS_CTRL_REG0_DIFF_FINE 0x00800000 -#define A6XX_SP_FS_CTRL_REG0_UNK24 0x01000000 -#define A6XX_SP_FS_CTRL_REG0_UNK25 0x02000000 -#define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000 -#define A6XX_SP_FS_CTRL_REG0_UNK27 0x08000000 -#define A6XX_SP_FS_CTRL_REG0_EARLYPREAMBLE 0x10000000 -#define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000 #define A6XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001 #define A6XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0 static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) @@ -6195,25 +6731,35 @@ static inline uint32_t A6XX_SP_FS_CTRL_REG0_BRANCHSTACK(uint32_t val) { return ((val) << A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_FS_CTRL_REG0_BRANCHSTACK__MASK; } +#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000 +#define A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20 +static inline uint32_t A6XX_SP_FS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) +{ + return ((val) << A6XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_FS_CTRL_REG0_THREADSIZE__MASK; +} +#define A6XX_SP_FS_CTRL_REG0_UNK21 0x00200000 +#define A6XX_SP_FS_CTRL_REG0_VARYING 0x00400000 +#define A6XX_SP_FS_CTRL_REG0_LODPIXMASK 0x00800000 +#define A6XX_SP_FS_CTRL_REG0_UNK24 0x01000000 +#define A6XX_SP_FS_CTRL_REG0_UNK25 0x02000000 +#define A6XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x04000000 +#define A6XX_SP_FS_CTRL_REG0_UNK27 0x08000000 +#define A6XX_SP_FS_CTRL_REG0_EARLYPREAMBLE 0x10000000 +#define A6XX_SP_FS_CTRL_REG0_MERGEDREGS 0x80000000 #define REG_A6XX_SP_FS_BRANCH_COND 0x0000a981 #define REG_A6XX_SP_FS_OBJ_FIRST_EXEC_OFFSET 0x0000a982 #define REG_A6XX_SP_FS_OBJ_START 0x0000a983 -#define A6XX_SP_FS_OBJ_START__MASK 0xffffffff -#define A6XX_SP_FS_OBJ_START__SHIFT 0 -static inline uint32_t A6XX_SP_FS_OBJ_START(uint32_t val) -{ - return ((val) << A6XX_SP_FS_OBJ_START__SHIFT) & A6XX_SP_FS_OBJ_START__MASK; -} #define REG_A6XX_SP_FS_PVT_MEM_PARAM 0x0000a985 #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff #define A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) { - return ((val >> 9) << A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; + assert(!(val & 0x1ff)); + return (((val >> 9)) << A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_FS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; } #define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 #define A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 @@ -6223,19 +6769,14 @@ static inline uint32_t A6XX_SP_FS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t va } #define REG_A6XX_SP_FS_PVT_MEM_ADDR 0x0000a986 -#define A6XX_SP_FS_PVT_MEM_ADDR__MASK 0xffffffff -#define A6XX_SP_FS_PVT_MEM_ADDR__SHIFT 0 -static inline uint32_t A6XX_SP_FS_PVT_MEM_ADDR(uint32_t val) -{ - return ((val) << A6XX_SP_FS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_FS_PVT_MEM_ADDR__MASK; -} #define REG_A6XX_SP_FS_PVT_MEM_SIZE 0x0000a988 #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff #define A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 static inline uint32_t A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) { - return ((val >> 12) << A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_FS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; } #define A6XX_SP_FS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 @@ -6339,7 +6880,7 @@ static inline uint32_t A6XX_SP_FS_OUTPUT_CNTL1_MRT(uint32_t val) return ((val) << A6XX_SP_FS_OUTPUT_CNTL1_MRT__SHIFT) & A6XX_SP_FS_OUTPUT_CNTL1_MRT__MASK; } -static inline uint32_t REG_A6XX_SP_FS_OUTPUT(uint32_t i0) { return 0x0000a98e + 0x1*i0; } +#define REG_A6XX_SP_FS_OUTPUT(i0) (0x0000a98e + 0x1*(i0)) static inline uint32_t REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) { return 0x0000a98e + 0x1*i0; } #define A6XX_SP_FS_OUTPUT_REG_REGID__MASK 0x000000ff @@ -6350,7 +6891,7 @@ static inline uint32_t A6XX_SP_FS_OUTPUT_REG_REGID(uint32_t val) } #define A6XX_SP_FS_OUTPUT_REG_HALF_PRECISION 0x00000100 -static inline uint32_t REG_A6XX_SP_FS_MRT(uint32_t i0) { return 0x0000a996 + 0x1*i0; } +#define REG_A6XX_SP_FS_MRT(i0) (0x0000a996 + 0x1*(i0)) static inline uint32_t REG_A6XX_SP_FS_MRT_REG(uint32_t i0) { return 0x0000a996 + 0x1*i0; } #define A6XX_SP_FS_MRT_REG_COLOR_FORMAT__MASK 0x000000ff @@ -6371,16 +6912,22 @@ static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_COUNT(uint32_t val) return ((val) << A6XX_SP_FS_PREFETCH_CNTL_COUNT__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_COUNT__MASK; } #define A6XX_SP_FS_PREFETCH_CNTL_IJ_WRITE_DISABLE 0x00000008 -#define A6XX_SP_FS_PREFETCH_CNTL_UNK4 0x00000010 +#define A6XX_SP_FS_PREFETCH_CNTL_ENDOFQUAD 0x00000010 #define A6XX_SP_FS_PREFETCH_CNTL_WRITE_COLOR_TO_OUTPUT 0x00000020 -#define A6XX_SP_FS_PREFETCH_CNTL_UNK6__MASK 0x00007fc0 -#define A6XX_SP_FS_PREFETCH_CNTL_UNK6__SHIFT 6 -static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_UNK6(uint32_t val) +#define A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__MASK 0x00007fc0 +#define A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__SHIFT 6 +static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID(uint32_t val) +{ + return ((val) << A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID__MASK; +} +#define A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__MASK 0x01ff0000 +#define A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__SHIFT 16 +static inline uint32_t A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD(uint32_t val) { - return ((val) << A6XX_SP_FS_PREFETCH_CNTL_UNK6__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_UNK6__MASK; + return ((val) << A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__SHIFT) & A6XX_SP_FS_PREFETCH_CNTL_CONSTSLOTID4COORD__MASK; } -static inline uint32_t REG_A6XX_SP_FS_PREFETCH(uint32_t i0) { return 0x0000a99f + 0x1*i0; } +#define REG_A6XX_SP_FS_PREFETCH(i0) (0x0000a99f + 0x1*(i0)) static inline uint32_t REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; } #define A6XX_SP_FS_PREFETCH_CMD_SRC__MASK 0x0000007f @@ -6423,7 +6970,49 @@ static inline uint32_t A6XX_SP_FS_PREFETCH_CMD_CMD(enum a6xx_tex_prefetch_cmd va return ((val) << A6XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A6XX_SP_FS_PREFETCH_CMD_CMD__MASK; } -static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; } +#define REG_A7XX_SP_FS_PREFETCH(i0) (0x0000a99f + 0x1*(i0)) + +static inline uint32_t REG_A7XX_SP_FS_PREFETCH_CMD(uint32_t i0) { return 0x0000a99f + 0x1*i0; } +#define A7XX_SP_FS_PREFETCH_CMD_SRC__MASK 0x0000007f +#define A7XX_SP_FS_PREFETCH_CMD_SRC__SHIFT 0 +static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_SRC(uint32_t val) +{ + return ((val) << A7XX_SP_FS_PREFETCH_CMD_SRC__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_SRC__MASK; +} +#define A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK 0x00000380 +#define A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT 7 +static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_SAMP_ID(uint32_t val) +{ + return ((val) << A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_SAMP_ID__MASK; +} +#define A7XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK 0x00001c00 +#define A7XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT 10 +static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_TEX_ID(uint32_t val) +{ + return ((val) << A7XX_SP_FS_PREFETCH_CMD_TEX_ID__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_TEX_ID__MASK; +} +#define A7XX_SP_FS_PREFETCH_CMD_DST__MASK 0x0007e000 +#define A7XX_SP_FS_PREFETCH_CMD_DST__SHIFT 13 +static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_DST(uint32_t val) +{ + return ((val) << A7XX_SP_FS_PREFETCH_CMD_DST__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_DST__MASK; +} +#define A7XX_SP_FS_PREFETCH_CMD_WRMASK__MASK 0x00780000 +#define A7XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT 19 +static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_WRMASK(uint32_t val) +{ + return ((val) << A7XX_SP_FS_PREFETCH_CMD_WRMASK__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_WRMASK__MASK; +} +#define A7XX_SP_FS_PREFETCH_CMD_HALF 0x00800000 +#define A7XX_SP_FS_PREFETCH_CMD_BINDLESS 0x02000000 +#define A7XX_SP_FS_PREFETCH_CMD_CMD__MASK 0x3c000000 +#define A7XX_SP_FS_PREFETCH_CMD_CMD__SHIFT 26 +static inline uint32_t A7XX_SP_FS_PREFETCH_CMD_CMD(enum a6xx_tex_prefetch_cmd val) +{ + return ((val) << A7XX_SP_FS_PREFETCH_CMD_CMD__SHIFT) & A7XX_SP_FS_PREFETCH_CMD_CMD__MASK; +} + +#define REG_A6XX_SP_FS_BINDLESS_PREFETCH(i0) (0x0000a9a3 + 0x1*(i0)) static inline uint32_t REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) { return 0x0000a9a3 + 0x1*i0; } #define A6XX_SP_FS_BINDLESS_PREFETCH_CMD_SAMP_ID__MASK 0x0000ffff @@ -6448,20 +7037,11 @@ static inline uint32_t A6XX_SP_FS_BINDLESS_PREFETCH_CMD_TEX_ID(uint32_t val) #define A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 static inline uint32_t A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) { - return ((val >> 11) << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; + assert(!(val & 0x7ff)); + return (((val >> 11)) << A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_FS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; } #define REG_A6XX_SP_CS_CTRL_REG0 0x0000a9b0 -#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000 -#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20 -static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) -{ - return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK; -} -#define A6XX_SP_CS_CTRL_REG0_UNK21 0x00200000 -#define A6XX_SP_CS_CTRL_REG0_UNK22 0x00400000 -#define A6XX_SP_CS_CTRL_REG0_EARLYPREAMBLE 0x00800000 -#define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000 #define A6XX_SP_CS_CTRL_REG0_THREADMODE__MASK 0x00000001 #define A6XX_SP_CS_CTRL_REG0_THREADMODE__SHIFT 0 static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val) @@ -6487,6 +7067,16 @@ static inline uint32_t A6XX_SP_CS_CTRL_REG0_BRANCHSTACK(uint32_t val) { return ((val) << A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__SHIFT) & A6XX_SP_CS_CTRL_REG0_BRANCHSTACK__MASK; } +#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK 0x00100000 +#define A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT 20 +static inline uint32_t A6XX_SP_CS_CTRL_REG0_THREADSIZE(enum a6xx_threadsize val) +{ + return ((val) << A6XX_SP_CS_CTRL_REG0_THREADSIZE__SHIFT) & A6XX_SP_CS_CTRL_REG0_THREADSIZE__MASK; +} +#define A6XX_SP_CS_CTRL_REG0_UNK21 0x00200000 +#define A6XX_SP_CS_CTRL_REG0_UNK22 0x00400000 +#define A6XX_SP_CS_CTRL_REG0_EARLYPREAMBLE 0x00800000 +#define A6XX_SP_CS_CTRL_REG0_MERGEDREGS 0x80000000 #define REG_A6XX_SP_CS_UNKNOWN_A9B1 0x0000a9b1 #define A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE__MASK 0x0000001f @@ -6503,19 +7093,14 @@ static inline uint32_t A6XX_SP_CS_UNKNOWN_A9B1_SHARED_SIZE(uint32_t val) #define REG_A6XX_SP_CS_OBJ_FIRST_EXEC_OFFSET 0x0000a9b3 #define REG_A6XX_SP_CS_OBJ_START 0x0000a9b4 -#define A6XX_SP_CS_OBJ_START__MASK 0xffffffff -#define A6XX_SP_CS_OBJ_START__SHIFT 0 -static inline uint32_t A6XX_SP_CS_OBJ_START(uint32_t val) -{ - return ((val) << A6XX_SP_CS_OBJ_START__SHIFT) & A6XX_SP_CS_OBJ_START__MASK; -} #define REG_A6XX_SP_CS_PVT_MEM_PARAM 0x0000a9b6 #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK 0x000000ff #define A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT 0 static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM(uint32_t val) { - return ((val >> 9) << A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; + assert(!(val & 0x1ff)); + return (((val >> 9)) << A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__SHIFT) & A6XX_SP_CS_PVT_MEM_PARAM_MEMSIZEPERITEM__MASK; } #define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__MASK 0xff000000 #define A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD__SHIFT 24 @@ -6525,19 +7110,14 @@ static inline uint32_t A6XX_SP_CS_PVT_MEM_PARAM_HWSTACKSIZEPERTHREAD(uint32_t va } #define REG_A6XX_SP_CS_PVT_MEM_ADDR 0x0000a9b7 -#define A6XX_SP_CS_PVT_MEM_ADDR__MASK 0xffffffff -#define A6XX_SP_CS_PVT_MEM_ADDR__SHIFT 0 -static inline uint32_t A6XX_SP_CS_PVT_MEM_ADDR(uint32_t val) -{ - return ((val) << A6XX_SP_CS_PVT_MEM_ADDR__SHIFT) & A6XX_SP_CS_PVT_MEM_ADDR__MASK; -} #define REG_A6XX_SP_CS_PVT_MEM_SIZE 0x0000a9b9 #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK 0x0003ffff #define A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT 0 static inline uint32_t A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE(uint32_t val) { - return ((val >> 12) << A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__SHIFT) & A6XX_SP_CS_PVT_MEM_SIZE_TOTALPVTMEMSIZE__MASK; } #define A6XX_SP_CS_PVT_MEM_SIZE_PERWAVEMEMLAYOUT 0x80000000 @@ -6575,9 +7155,14 @@ static inline uint32_t A6XX_SP_CS_CONFIG_NIBO(uint32_t val) #define A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT 0 static inline uint32_t A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET(uint32_t val) { - return ((val >> 11) << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; + assert(!(val & 0x7ff)); + return (((val >> 11)) << A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__SHIFT) & A6XX_SP_CS_PVT_MEM_HW_STACK_OFFSET_OFFSET__MASK; } +#define REG_A7XX_SP_CS_UNKNOWN_A9BE 0x0000a9be + +#define REG_A7XX_SP_CS_VGPR_CONFIG 0x0000a9c5 + #define REG_A6XX_SP_CS_CNTL_0 0x0000a9c2 #define A6XX_SP_CS_CNTL_0_WGIDCONSTID__MASK 0x000000ff #define A6XX_SP_CS_CNTL_0_WGIDCONSTID__SHIFT 0 @@ -6620,39 +7205,31 @@ static inline uint32_t A6XX_SP_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) } #define A6XX_SP_CS_CNTL_1_THREADSIZE_SCALAR 0x00000400 -#define REG_A6XX_SP_FS_TEX_SAMP 0x0000a9e0 -#define A6XX_SP_FS_TEX_SAMP__MASK 0xffffffff -#define A6XX_SP_FS_TEX_SAMP__SHIFT 0 -static inline uint32_t A6XX_SP_FS_TEX_SAMP(uint32_t val) +#define REG_A7XX_SP_CS_CNTL_1 0x0000a9c3 +#define A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff +#define A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0 +static inline uint32_t A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) { - return ((val) << A6XX_SP_FS_TEX_SAMP__SHIFT) & A6XX_SP_FS_TEX_SAMP__MASK; + return ((val) << A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A7XX_SP_CS_CNTL_1_LINEARLOCALIDREGID__MASK; } - -#define REG_A6XX_SP_CS_TEX_SAMP 0x0000a9e2 -#define A6XX_SP_CS_TEX_SAMP__MASK 0xffffffff -#define A6XX_SP_CS_TEX_SAMP__SHIFT 0 -static inline uint32_t A6XX_SP_CS_TEX_SAMP(uint32_t val) +#define A7XX_SP_CS_CNTL_1_THREADSIZE__MASK 0x00000100 +#define A7XX_SP_CS_CNTL_1_THREADSIZE__SHIFT 8 +static inline uint32_t A7XX_SP_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) { - return ((val) << A6XX_SP_CS_TEX_SAMP__SHIFT) & A6XX_SP_CS_TEX_SAMP__MASK; + return ((val) << A7XX_SP_CS_CNTL_1_THREADSIZE__SHIFT) & A7XX_SP_CS_CNTL_1_THREADSIZE__MASK; } +#define A7XX_SP_CS_CNTL_1_THREADSIZE_SCALAR 0x00000200 +#define A7XX_SP_CS_CNTL_1_UNK15 0x00008000 + +#define REG_A6XX_SP_FS_TEX_SAMP 0x0000a9e0 + +#define REG_A6XX_SP_CS_TEX_SAMP 0x0000a9e2 #define REG_A6XX_SP_FS_TEX_CONST 0x0000a9e4 -#define A6XX_SP_FS_TEX_CONST__MASK 0xffffffff -#define A6XX_SP_FS_TEX_CONST__SHIFT 0 -static inline uint32_t A6XX_SP_FS_TEX_CONST(uint32_t val) -{ - return ((val) << A6XX_SP_FS_TEX_CONST__SHIFT) & A6XX_SP_FS_TEX_CONST__MASK; -} #define REG_A6XX_SP_CS_TEX_CONST 0x0000a9e6 -#define A6XX_SP_CS_TEX_CONST__MASK 0xffffffff -#define A6XX_SP_CS_TEX_CONST__SHIFT 0 -static inline uint32_t A6XX_SP_CS_TEX_CONST(uint32_t val) -{ - return ((val) << A6XX_SP_CS_TEX_CONST__SHIFT) & A6XX_SP_CS_TEX_CONST__MASK; -} -static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; } +#define REG_A6XX_SP_CS_BINDLESS_BASE(i0) (0x0000a9e8 + 0x2*(i0)) static inline uint32_t REG_A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; } #define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 @@ -6661,23 +7238,92 @@ static inline uint32_t A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_b { return ((val) << A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; } -#define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffc +#define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc #define A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 -static inline uint32_t A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val) +static inline uint32_t A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) { - return ((val >> 2) << A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; } -#define REG_A6XX_SP_CS_IBO 0x0000a9f2 -#define A6XX_SP_CS_IBO__MASK 0xffffffff -#define A6XX_SP_CS_IBO__SHIFT 0 -static inline uint32_t A6XX_SP_CS_IBO(uint32_t val) +#define REG_A7XX_SP_CS_BINDLESS_BASE(i0) (0x0000a9e8 + 0x2*(i0)) + +static inline uint32_t REG_A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000a9e8 + 0x2*i0; } +#define A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 +#define A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0 +static inline uint32_t A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) +{ + return ((val) << A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; +} +#define A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc +#define A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 +static inline uint32_t A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) { - return ((val) << A6XX_SP_CS_IBO__SHIFT) & A6XX_SP_CS_IBO__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A7XX_SP_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; } +#define REG_A6XX_SP_CS_IBO 0x0000a9f2 + #define REG_A6XX_SP_CS_IBO_COUNT 0x0000aa00 +#define REG_A7XX_SP_FS_VGPR_CONFIG 0x0000aa01 + +#define REG_A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL 0x0000aa02 +#define A7XX_SP_PS_ALIASED_COMPONENTS_CONTROL_ENABLED 0x00000001 + +#define REG_A7XX_SP_PS_ALIASED_COMPONENTS 0x0000aa03 +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT0__MASK 0x0000000f +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT0__SHIFT 0 +static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT0(uint32_t val) +{ + return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT0__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT0__MASK; +} +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT1__MASK 0x000000f0 +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT1__SHIFT 4 +static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT1(uint32_t val) +{ + return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT1__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT1__MASK; +} +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT2__MASK 0x00000f00 +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT2__SHIFT 8 +static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT2(uint32_t val) +{ + return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT2__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT2__MASK; +} +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT3__MASK 0x0000f000 +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT3__SHIFT 12 +static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT3(uint32_t val) +{ + return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT3__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT3__MASK; +} +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT4__MASK 0x000f0000 +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT4__SHIFT 16 +static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT4(uint32_t val) +{ + return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT4__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT4__MASK; +} +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT5__MASK 0x00f00000 +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT5__SHIFT 20 +static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT5(uint32_t val) +{ + return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT5__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT5__MASK; +} +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT6__MASK 0x0f000000 +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT6__SHIFT 24 +static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT6(uint32_t val) +{ + return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT6__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT6__MASK; +} +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT7__MASK 0xf0000000 +#define A7XX_SP_PS_ALIASED_COMPONENTS_RT7__SHIFT 28 +static inline uint32_t A7XX_SP_PS_ALIASED_COMPONENTS_RT7(uint32_t val) +{ + return ((val) << A7XX_SP_PS_ALIASED_COMPONENTS_RT7__SHIFT) & A7XX_SP_PS_ALIASED_COMPONENTS_RT7__MASK; +} + +#define REG_A6XX_SP_UNKNOWN_AAF2 0x0000aaf2 + #define REG_A6XX_SP_MODE_CONTROL 0x0000ab00 #define A6XX_SP_MODE_CONTROL_CONSTANT_DEMOTION_ENABLE 0x00000001 #define A6XX_SP_MODE_CONTROL_ISAMMODE__MASK 0x00000006 @@ -6688,6 +7334,10 @@ static inline uint32_t A6XX_SP_MODE_CONTROL_ISAMMODE(enum a6xx_isam_mode val) } #define A6XX_SP_MODE_CONTROL_SHARED_CONSTS_ENABLE 0x00000008 +#define REG_A7XX_SP_UNKNOWN_AB01 0x0000ab01 + +#define REG_A7XX_SP_UNKNOWN_AB02 0x0000ab02 + #define REG_A6XX_SP_FS_CONFIG 0x0000ab04 #define A6XX_SP_FS_CONFIG_BINDLESS_TEX 0x00000001 #define A6XX_SP_FS_CONFIG_BINDLESS_SAMP 0x00000002 @@ -6715,7 +7365,7 @@ static inline uint32_t A6XX_SP_FS_CONFIG_NIBO(uint32_t val) #define REG_A6XX_SP_FS_INSTRLEN 0x0000ab05 -static inline uint32_t REG_A6XX_SP_BINDLESS_BASE(uint32_t i0) { return 0x0000ab10 + 0x2*i0; } +#define REG_A6XX_SP_BINDLESS_BASE(i0) (0x0000ab10 + 0x2*(i0)) static inline uint32_t REG_A6XX_SP_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000ab10 + 0x2*i0; } #define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 @@ -6724,23 +7374,37 @@ static inline uint32_t A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bind { return ((val) << A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; } -#define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffc +#define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc #define A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 -static inline uint32_t A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val) +static inline uint32_t A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) { - return ((val >> 2) << A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; } -#define REG_A6XX_SP_IBO 0x0000ab1a -#define A6XX_SP_IBO__MASK 0xffffffff -#define A6XX_SP_IBO__SHIFT 0 -static inline uint32_t A6XX_SP_IBO(uint32_t val) +#define REG_A7XX_SP_BINDLESS_BASE(i0) (0x0000ab0a + 0x2*(i0)) + +static inline uint32_t REG_A7XX_SP_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000ab0a + 0x2*i0; } +#define A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 +#define A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT 0 +static inline uint32_t A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bindless_descriptor_size val) { - return ((val) << A6XX_SP_IBO__SHIFT) & A6XX_SP_IBO__MASK; + return ((val) << A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A7XX_SP_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; +} +#define A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc +#define A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 +static inline uint32_t A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) +{ + assert(!(val & 0x3)); + return (((val >> 2)) << A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A7XX_SP_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; } +#define REG_A6XX_SP_IBO 0x0000ab1a + #define REG_A6XX_SP_IBO_COUNT 0x0000ab20 +#define REG_A7XX_SP_UNKNOWN_AB22 0x0000ab22 + #define REG_A6XX_SP_2D_DST_FORMAT 0x0000acc0 #define A6XX_SP_2D_DST_FORMAT_NORM 0x00000001 #define A6XX_SP_2D_DST_FORMAT_SINT 0x00000002 @@ -6759,6 +7423,24 @@ static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val) return ((val) << A6XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A6XX_SP_2D_DST_FORMAT_MASK__MASK; } +#define REG_A7XX_SP_2D_DST_FORMAT 0x0000a9bf +#define A7XX_SP_2D_DST_FORMAT_NORM 0x00000001 +#define A7XX_SP_2D_DST_FORMAT_SINT 0x00000002 +#define A7XX_SP_2D_DST_FORMAT_UINT 0x00000004 +#define A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK 0x000007f8 +#define A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT 3 +static inline uint32_t A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT(enum a6xx_format val) +{ + return ((val) << A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__SHIFT) & A7XX_SP_2D_DST_FORMAT_COLOR_FORMAT__MASK; +} +#define A7XX_SP_2D_DST_FORMAT_SRGB 0x00000800 +#define A7XX_SP_2D_DST_FORMAT_MASK__MASK 0x0000f000 +#define A7XX_SP_2D_DST_FORMAT_MASK__SHIFT 12 +static inline uint32_t A7XX_SP_2D_DST_FORMAT_MASK(uint32_t val) +{ + return ((val) << A7XX_SP_2D_DST_FORMAT_MASK__SHIFT) & A7XX_SP_2D_DST_FORMAT_MASK__MASK; +} + #define REG_A6XX_SP_DBG_ECO_CNTL 0x0000ae00 #define REG_A6XX_SP_ADDR_MODE_CNTL 0x0000ae01 @@ -6770,6 +7452,14 @@ static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val) #define REG_A6XX_SP_FLOAT_CNTL 0x0000ae04 #define A6XX_SP_FLOAT_CNTL_F16_NO_INF 0x00000008 +#define REG_A7XX_SP_UNKNOWN_AE06 0x0000ae06 + +#define REG_A7XX_SP_UNKNOWN_AE08 0x0000ae08 + +#define REG_A7XX_SP_UNKNOWN_AE09 0x0000ae09 + +#define REG_A7XX_SP_UNKNOWN_AE0A 0x0000ae0a + #define REG_A6XX_SP_PERFCTR_ENABLE 0x0000ae0f #define A6XX_SP_PERFCTR_ENABLE_VS 0x00000001 #define A6XX_SP_PERFCTR_ENABLE_HS 0x00000002 @@ -6778,23 +7468,57 @@ static inline uint32_t A6XX_SP_2D_DST_FORMAT_MASK(uint32_t val) #define A6XX_SP_PERFCTR_ENABLE_FS 0x00000010 #define A6XX_SP_PERFCTR_ENABLE_CS 0x00000020 -static inline uint32_t REG_A6XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae10 + 0x1*i0; } +#define REG_A6XX_SP_PERFCTR_SP_SEL(i0) (0x0000ae10 + 0x1*(i0)) + +#define REG_A7XX_SP_PERFCTR_HLSQ_SEL(i0) (0x0000ae60 + 0x1*(i0)) -static inline uint32_t REG_A7XX_SP_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000ae60 + 0x1*i0; } +#define REG_A7XX_SP_UNKNOWN_AE6A 0x0000ae6a + +#define REG_A7XX_SP_UNKNOWN_AE6B 0x0000ae6b + +#define REG_A7XX_SP_UNKNOWN_AE6C 0x0000ae6c #define REG_A7XX_SP_READ_SEL 0x0000ae6d +#define A7XX_SP_READ_SEL_LOCATION__MASK 0x000c0000 +#define A7XX_SP_READ_SEL_LOCATION__SHIFT 18 +static inline uint32_t A7XX_SP_READ_SEL_LOCATION(enum a7xx_state_location val) +{ + return ((val) << A7XX_SP_READ_SEL_LOCATION__SHIFT) & A7XX_SP_READ_SEL_LOCATION__MASK; +} +#define A7XX_SP_READ_SEL_PIPE__MASK 0x00030000 +#define A7XX_SP_READ_SEL_PIPE__SHIFT 16 +static inline uint32_t A7XX_SP_READ_SEL_PIPE(enum a7xx_pipe val) +{ + return ((val) << A7XX_SP_READ_SEL_PIPE__SHIFT) & A7XX_SP_READ_SEL_PIPE__MASK; +} +#define A7XX_SP_READ_SEL_STATETYPE__MASK 0x0000ff00 +#define A7XX_SP_READ_SEL_STATETYPE__SHIFT 8 +static inline uint32_t A7XX_SP_READ_SEL_STATETYPE(enum a7xx_statetype_id val) +{ + return ((val) << A7XX_SP_READ_SEL_STATETYPE__SHIFT) & A7XX_SP_READ_SEL_STATETYPE__MASK; +} +#define A7XX_SP_READ_SEL_USPTP__MASK 0x000000f0 +#define A7XX_SP_READ_SEL_USPTP__SHIFT 4 +static inline uint32_t A7XX_SP_READ_SEL_USPTP(uint32_t val) +{ + return ((val) << A7XX_SP_READ_SEL_USPTP__SHIFT) & A7XX_SP_READ_SEL_USPTP__MASK; +} +#define A7XX_SP_READ_SEL_SPTP__MASK 0x0000000f +#define A7XX_SP_READ_SEL_SPTP__SHIFT 0 +static inline uint32_t A7XX_SP_READ_SEL_SPTP(uint32_t val) +{ + return ((val) << A7XX_SP_READ_SEL_SPTP__SHIFT) & A7XX_SP_READ_SEL_SPTP__MASK; +} + +#define REG_A7XX_SP_DBG_CNTL 0x0000ae71 -static inline uint32_t REG_A7XX_SP_PERFCTR_SP_SEL(uint32_t i0) { return 0x0000ae80 + 0x1*i0; } +#define REG_A7XX_SP_UNKNOWN_AE73 0x0000ae73 + +#define REG_A7XX_SP_PERFCTR_SP_SEL(i0) (0x0000ae80 + 0x1*(i0)) #define REG_A6XX_SP_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22 #define REG_A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR 0x0000b180 -#define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff -#define A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0 -static inline uint32_t A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(uint32_t val) -{ - return ((val) << A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR__MASK; -} #define REG_A6XX_SP_UNKNOWN_B182 0x0000b182 @@ -6828,12 +7552,6 @@ static inline uint32_t A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(enum a3xx_msaa_samples #define A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE 0x00000004 #define REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR 0x0000b302 -#define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK 0xffffffff -#define A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT 0 -static inline uint32_t A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(uint32_t val) -{ - return ((val) << A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__SHIFT) & A6XX_SP_TP_BORDER_COLOR_BASE_ADDR__MASK; -} #define REG_A6XX_SP_TP_SAMPLE_CONFIG 0x0000b304 #define A6XX_SP_TP_SAMPLE_CONFIG_UNK0 0x00000001 @@ -6844,49 +7562,49 @@ static inline uint32_t A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(uint32_t val) #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT 0 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_X__MASK; } #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK 0x000000f0 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT 4 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_0_Y__MASK; } #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK 0x00000f00 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT 8 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_X__MASK; } #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK 0x0000f000 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT 12 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_1_Y__MASK; } #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK 0x000f0000 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT 16 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_X__MASK; } #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK 0x00f00000 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT 20 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_2_Y__MASK; } #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK 0x0f000000 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT 24 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_X__MASK; } #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK 0xf0000000 #define A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT 28 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y__MASK; } #define REG_A6XX_SP_TP_SAMPLE_LOCATION_1 0x0000b306 @@ -6894,49 +7612,49 @@ static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_0_SAMPLE_3_Y(float val) #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT 0 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_X__MASK; } #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK 0x000000f0 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT 4 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_0_Y__MASK; } #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK 0x00000f00 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT 8 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_X__MASK; } #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK 0x0000f000 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT 12 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_1_Y__MASK; } #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK 0x000f0000 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT 16 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_X__MASK; } #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK 0x00f00000 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT 20 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_2_Y__MASK; } #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK 0x0f000000 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT 24 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_X__MASK; } #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK 0xf0000000 #define A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT 28 static inline uint32_t A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y(float val) { - return ((((int32_t)(val * 1.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; + return ((((int32_t)(val * 16.0))) << A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__SHIFT) & A6XX_SP_TP_SAMPLE_LOCATION_1_SAMPLE_3_Y__MASK; } #define REG_A6XX_SP_TP_WINDOW_OFFSET 0x0000b307 @@ -6967,6 +7685,8 @@ static inline uint32_t A6XX_SP_TP_MODE_CNTL_UNK3(uint32_t val) return ((val) << A6XX_SP_TP_MODE_CNTL_UNK3__SHIFT) & A6XX_SP_TP_MODE_CNTL_UNK3__MASK; } +#define REG_A7XX_SP_UNKNOWN_B310 0x0000b310 + #define REG_A6XX_SP_PS_2D_SRC_INFO 0x0000b4c0 #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff #define A6XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 @@ -7024,12 +7744,6 @@ static inline uint32_t A6XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val) } #define REG_A6XX_SP_PS_2D_SRC 0x0000b4c2 -#define A6XX_SP_PS_2D_SRC__MASK 0xffffffff -#define A6XX_SP_PS_2D_SRC__SHIFT 0 -static inline uint32_t A6XX_SP_PS_2D_SRC(uint32_t val) -{ - return ((val) << A6XX_SP_PS_2D_SRC__SHIFT) & A6XX_SP_PS_2D_SRC__MASK; -} #define REG_A6XX_SP_PS_2D_SRC_PITCH 0x0000b4c4 #define A6XX_SP_PS_2D_SRC_PITCH_UNK0__MASK 0x000001ff @@ -7042,47 +7756,129 @@ static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val) #define A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9 static inline uint32_t A6XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PITCH_PITCH__MASK; } -#define REG_A6XX_SP_PS_2D_SRC_PLANE1 0x0000b4c5 -#define A6XX_SP_PS_2D_SRC_PLANE1__MASK 0xffffffff -#define A6XX_SP_PS_2D_SRC_PLANE1__SHIFT 0 -static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE1(uint32_t val) +#define REG_A7XX_SP_PS_2D_SRC_INFO 0x0000b2c0 +#define A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK 0x000000ff +#define A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT 0 +static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT(enum a6xx_format val) +{ + return ((val) << A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_COLOR_FORMAT__MASK; +} +#define A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK 0x00000300 +#define A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT 8 +static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_TILE_MODE(enum a6xx_tile_mode val) +{ + return ((val) << A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_TILE_MODE__MASK; +} +#define A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK 0x00000c00 +#define A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT 10 +static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP(enum a3xx_color_swap val) { - return ((val) << A6XX_SP_PS_2D_SRC_PLANE1__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE1__MASK; + return ((val) << A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_COLOR_SWAP__MASK; } +#define A7XX_SP_PS_2D_SRC_INFO_FLAGS 0x00001000 +#define A7XX_SP_PS_2D_SRC_INFO_SRGB 0x00002000 +#define A7XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK 0x0000c000 +#define A7XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT 14 +static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_SAMPLES(enum a3xx_msaa_samples val) +{ + return ((val) << A7XX_SP_PS_2D_SRC_INFO_SAMPLES__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_SAMPLES__MASK; +} +#define A7XX_SP_PS_2D_SRC_INFO_FILTER 0x00010000 +#define A7XX_SP_PS_2D_SRC_INFO_UNK17 0x00020000 +#define A7XX_SP_PS_2D_SRC_INFO_SAMPLES_AVERAGE 0x00040000 +#define A7XX_SP_PS_2D_SRC_INFO_UNK19 0x00080000 +#define A7XX_SP_PS_2D_SRC_INFO_UNK20 0x00100000 +#define A7XX_SP_PS_2D_SRC_INFO_UNK21 0x00200000 +#define A7XX_SP_PS_2D_SRC_INFO_UNK22 0x00400000 +#define A7XX_SP_PS_2D_SRC_INFO_UNK23__MASK 0x07800000 +#define A7XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT 23 +static inline uint32_t A7XX_SP_PS_2D_SRC_INFO_UNK23(uint32_t val) +{ + return ((val) << A7XX_SP_PS_2D_SRC_INFO_UNK23__SHIFT) & A7XX_SP_PS_2D_SRC_INFO_UNK23__MASK; +} +#define A7XX_SP_PS_2D_SRC_INFO_UNK28 0x10000000 + +#define REG_A7XX_SP_PS_2D_SRC_SIZE 0x0000b2c1 +#define A7XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK 0x00007fff +#define A7XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT 0 +static inline uint32_t A7XX_SP_PS_2D_SRC_SIZE_WIDTH(uint32_t val) +{ + return ((val) << A7XX_SP_PS_2D_SRC_SIZE_WIDTH__SHIFT) & A7XX_SP_PS_2D_SRC_SIZE_WIDTH__MASK; +} +#define A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK 0x3fff8000 +#define A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT 15 +static inline uint32_t A7XX_SP_PS_2D_SRC_SIZE_HEIGHT(uint32_t val) +{ + return ((val) << A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__SHIFT) & A7XX_SP_PS_2D_SRC_SIZE_HEIGHT__MASK; +} + +#define REG_A7XX_SP_PS_2D_SRC 0x0000b2c2 + +#define REG_A7XX_SP_PS_2D_SRC_PITCH 0x0000b2c4 +#define A7XX_SP_PS_2D_SRC_PITCH_UNK0__MASK 0x000001ff +#define A7XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT 0 +static inline uint32_t A7XX_SP_PS_2D_SRC_PITCH_UNK0(uint32_t val) +{ + return ((val) << A7XX_SP_PS_2D_SRC_PITCH_UNK0__SHIFT) & A7XX_SP_PS_2D_SRC_PITCH_UNK0__MASK; +} +#define A7XX_SP_PS_2D_SRC_PITCH_PITCH__MASK 0x00fffe00 +#define A7XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT 9 +static inline uint32_t A7XX_SP_PS_2D_SRC_PITCH_PITCH(uint32_t val) +{ + assert(!(val & 0x3f)); + return (((val >> 6)) << A7XX_SP_PS_2D_SRC_PITCH_PITCH__SHIFT) & A7XX_SP_PS_2D_SRC_PITCH_PITCH__MASK; +} + +#define REG_A6XX_SP_PS_2D_SRC_PLANE1 0x0000b4c5 #define REG_A6XX_SP_PS_2D_SRC_PLANE_PITCH 0x0000b4c7 #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK 0x00000fff #define A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT 0 static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE_PITCH__MASK; } #define REG_A6XX_SP_PS_2D_SRC_PLANE2 0x0000b4c8 -#define A6XX_SP_PS_2D_SRC_PLANE2__MASK 0xffffffff -#define A6XX_SP_PS_2D_SRC_PLANE2__SHIFT 0 -static inline uint32_t A6XX_SP_PS_2D_SRC_PLANE2(uint32_t val) + +#define REG_A7XX_SP_PS_2D_SRC_PLANE1 0x0000b2c5 + +#define REG_A7XX_SP_PS_2D_SRC_PLANE_PITCH 0x0000b2c7 +#define A7XX_SP_PS_2D_SRC_PLANE_PITCH__MASK 0x00000fff +#define A7XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT 0 +static inline uint32_t A7XX_SP_PS_2D_SRC_PLANE_PITCH(uint32_t val) { - return ((val) << A6XX_SP_PS_2D_SRC_PLANE2__SHIFT) & A6XX_SP_PS_2D_SRC_PLANE2__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A7XX_SP_PS_2D_SRC_PLANE_PITCH__SHIFT) & A7XX_SP_PS_2D_SRC_PLANE_PITCH__MASK; } +#define REG_A7XX_SP_PS_2D_SRC_PLANE2 0x0000b2c8 + #define REG_A6XX_SP_PS_2D_SRC_FLAGS 0x0000b4ca -#define A6XX_SP_PS_2D_SRC_FLAGS__MASK 0xffffffff -#define A6XX_SP_PS_2D_SRC_FLAGS__SHIFT 0 -static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS(uint32_t val) -{ - return ((val) << A6XX_SP_PS_2D_SRC_FLAGS__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS__MASK; -} #define REG_A6XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b4cc #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK 0x000000ff #define A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT 0 static inline uint32_t A6XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A6XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK; +} + +#define REG_A7XX_SP_PS_2D_SRC_FLAGS 0x0000b2ca + +#define REG_A7XX_SP_PS_2D_SRC_FLAGS_PITCH 0x0000b2cc +#define A7XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK 0x000000ff +#define A7XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT 0 +static inline uint32_t A7XX_SP_PS_2D_SRC_FLAGS_PITCH(uint32_t val) +{ + assert(!(val & 0x3f)); + return (((val >> 6)) << A7XX_SP_PS_2D_SRC_FLAGS_PITCH__SHIFT) & A7XX_SP_PS_2D_SRC_FLAGS_PITCH__MASK; } #define REG_A6XX_SP_PS_UNKNOWN_B4CD 0x0000b4cd @@ -7107,6 +7903,44 @@ static inline uint32_t A6XX_SP_WINDOW_OFFSET_Y(uint32_t val) return ((val) << A6XX_SP_WINDOW_OFFSET_Y__SHIFT) & A6XX_SP_WINDOW_OFFSET_Y__MASK; } +#define REG_A7XX_SP_PS_UNKNOWN_B4CD 0x0000b2cd + +#define REG_A7XX_SP_PS_UNKNOWN_B4CE 0x0000b2ce + +#define REG_A7XX_SP_PS_UNKNOWN_B4CF 0x0000b2cf + +#define REG_A7XX_SP_PS_UNKNOWN_B4D0 0x0000b2d0 + +#define REG_A7XX_SP_PS_2D_WINDOW_OFFSET 0x0000b2d1 +#define A7XX_SP_PS_2D_WINDOW_OFFSET_X__MASK 0x00003fff +#define A7XX_SP_PS_2D_WINDOW_OFFSET_X__SHIFT 0 +static inline uint32_t A7XX_SP_PS_2D_WINDOW_OFFSET_X(uint32_t val) +{ + return ((val) << A7XX_SP_PS_2D_WINDOW_OFFSET_X__SHIFT) & A7XX_SP_PS_2D_WINDOW_OFFSET_X__MASK; +} +#define A7XX_SP_PS_2D_WINDOW_OFFSET_Y__MASK 0x3fff0000 +#define A7XX_SP_PS_2D_WINDOW_OFFSET_Y__SHIFT 16 +static inline uint32_t A7XX_SP_PS_2D_WINDOW_OFFSET_Y(uint32_t val) +{ + return ((val) << A7XX_SP_PS_2D_WINDOW_OFFSET_Y__SHIFT) & A7XX_SP_PS_2D_WINDOW_OFFSET_Y__MASK; +} + +#define REG_A7XX_SP_PS_UNKNOWN_B2D2 0x0000b2d2 + +#define REG_A7XX_SP_WINDOW_OFFSET 0x0000ab21 +#define A7XX_SP_WINDOW_OFFSET_X__MASK 0x00003fff +#define A7XX_SP_WINDOW_OFFSET_X__SHIFT 0 +static inline uint32_t A7XX_SP_WINDOW_OFFSET_X(uint32_t val) +{ + return ((val) << A7XX_SP_WINDOW_OFFSET_X__SHIFT) & A7XX_SP_WINDOW_OFFSET_X__MASK; +} +#define A7XX_SP_WINDOW_OFFSET_Y__MASK 0x3fff0000 +#define A7XX_SP_WINDOW_OFFSET_Y__SHIFT 16 +static inline uint32_t A7XX_SP_WINDOW_OFFSET_Y(uint32_t val) +{ + return ((val) << A7XX_SP_WINDOW_OFFSET_Y__SHIFT) & A7XX_SP_WINDOW_OFFSET_Y__MASK; +} + #define REG_A6XX_TPL1_DBG_ECO_CNTL 0x0000b600 #define REG_A6XX_TPL1_ADDR_MODE_CNTL 0x0000b601 @@ -7147,53 +7981,126 @@ static inline uint32_t A6XX_TPL1_NC_MODE_CNTL_UNK6(uint32_t val) #define REG_A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c -static inline uint32_t REG_A6XX_TPL1_PERFCTR_TP_SEL(uint32_t i0) { return 0x0000b610 + 0x1*i0; } +#define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_0 0x0000b608 + +#define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_1 0x0000b609 + +#define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_2 0x0000b60a + +#define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_3 0x0000b60b + +#define REG_A7XX_TPL1_BICUBIC_WEIGHTS_TABLE_4 0x0000b60c + +#define REG_A6XX_TPL1_PERFCTR_TP_SEL(i0) (0x0000b610 + 0x1*(i0)) #define REG_A6XX_HLSQ_VS_CNTL 0x0000b800 #define A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff #define A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0 static inline uint32_t A6XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val) { - return ((val >> 2) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_VS_CNTL_CONSTLEN__MASK; } #define A6XX_HLSQ_VS_CNTL_ENABLED 0x00000100 +#define A6XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 #define REG_A6XX_HLSQ_HS_CNTL 0x0000b801 #define A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff #define A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0 static inline uint32_t A6XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val) { - return ((val >> 2) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_HS_CNTL_CONSTLEN__MASK; } #define A6XX_HLSQ_HS_CNTL_ENABLED 0x00000100 +#define A6XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 #define REG_A6XX_HLSQ_DS_CNTL 0x0000b802 #define A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff #define A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0 static inline uint32_t A6XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val) { - return ((val >> 2) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_DS_CNTL_CONSTLEN__MASK; } #define A6XX_HLSQ_DS_CNTL_ENABLED 0x00000100 +#define A6XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 #define REG_A6XX_HLSQ_GS_CNTL 0x0000b803 #define A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff #define A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0 static inline uint32_t A6XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val) { - return ((val >> 2) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_GS_CNTL_CONSTLEN__MASK; } #define A6XX_HLSQ_GS_CNTL_ENABLED 0x00000100 +#define A6XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 -#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD 0x0000b820 +#define REG_A7XX_HLSQ_VS_CNTL 0x0000a827 +#define A7XX_HLSQ_VS_CNTL_CONSTLEN__MASK 0x000000ff +#define A7XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT 0 +static inline uint32_t A7XX_HLSQ_VS_CNTL_CONSTLEN(uint32_t val) +{ + assert(!(val & 0x3)); + return (((val >> 2)) << A7XX_HLSQ_VS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_VS_CNTL_CONSTLEN__MASK; +} +#define A7XX_HLSQ_VS_CNTL_ENABLED 0x00000100 +#define A7XX_HLSQ_VS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 -#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR 0x0000b821 -#define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK 0xffffffff -#define A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT 0 -static inline uint32_t A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR(uint32_t val) +#define REG_A7XX_HLSQ_HS_CNTL 0x0000a83f +#define A7XX_HLSQ_HS_CNTL_CONSTLEN__MASK 0x000000ff +#define A7XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT 0 +static inline uint32_t A7XX_HLSQ_HS_CNTL_CONSTLEN(uint32_t val) { - return ((val) << A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A7XX_HLSQ_HS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_HS_CNTL_CONSTLEN__MASK; } +#define A7XX_HLSQ_HS_CNTL_ENABLED 0x00000100 +#define A7XX_HLSQ_HS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 + +#define REG_A7XX_HLSQ_DS_CNTL 0x0000a867 +#define A7XX_HLSQ_DS_CNTL_CONSTLEN__MASK 0x000000ff +#define A7XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT 0 +static inline uint32_t A7XX_HLSQ_DS_CNTL_CONSTLEN(uint32_t val) +{ + assert(!(val & 0x3)); + return (((val >> 2)) << A7XX_HLSQ_DS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_DS_CNTL_CONSTLEN__MASK; +} +#define A7XX_HLSQ_DS_CNTL_ENABLED 0x00000100 +#define A7XX_HLSQ_DS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 + +#define REG_A7XX_HLSQ_GS_CNTL 0x0000a898 +#define A7XX_HLSQ_GS_CNTL_CONSTLEN__MASK 0x000000ff +#define A7XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT 0 +static inline uint32_t A7XX_HLSQ_GS_CNTL_CONSTLEN(uint32_t val) +{ + assert(!(val & 0x3)); + return (((val >> 2)) << A7XX_HLSQ_GS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_GS_CNTL_CONSTLEN__MASK; +} +#define A7XX_HLSQ_GS_CNTL_ENABLED 0x00000100 +#define A7XX_HLSQ_GS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 + +#define REG_A7XX_HLSQ_FS_UNKNOWN_A9AA 0x0000a9aa +#define A7XX_HLSQ_FS_UNKNOWN_A9AA_CONSTS_LOAD_DISABLE 0x00000001 + +#define REG_A7XX_HLSQ_UNKNOWN_A9AC 0x0000a9ac + +#define REG_A7XX_HLSQ_UNKNOWN_A9AD 0x0000a9ad + +#define REG_A7XX_HLSQ_UNKNOWN_A9AE 0x0000a9ae +#define A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__MASK 0x000000ff +#define A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__SHIFT 0 +static inline uint32_t A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT(uint32_t val) +{ + return ((val) << A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__SHIFT) & A7XX_HLSQ_UNKNOWN_A9AE_SYSVAL_REGS_COUNT__MASK; +} +#define A7XX_HLSQ_UNKNOWN_A9AE_UNK8 0x00000100 +#define A7XX_HLSQ_UNKNOWN_A9AE_UNK9 0x00000200 + +#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_CMD 0x0000b820 + +#define REG_A6XX_HLSQ_LOAD_STATE_GEOM_EXT_SRC_ADDR 0x0000b821 #define REG_A6XX_HLSQ_LOAD_STATE_GEOM_DATA 0x0000b823 @@ -7215,8 +8122,12 @@ static inline uint32_t A6XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val) #define REG_A6XX_HLSQ_UNKNOWN_B981 0x0000b981 #define REG_A6XX_HLSQ_CONTROL_1_REG 0x0000b982 - -#define REG_A7XX_HLSQ_CONTROL_1_REG 0x0000a9c7 +#define A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x00000007 +#define A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0 +static inline uint32_t A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val) +{ + return ((val) << A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A6XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK; +} #define REG_A6XX_HLSQ_CONTROL_2_REG 0x0000b983 #define A6XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff @@ -7244,32 +8155,6 @@ static inline uint32_t A6XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val) return ((val) << A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A6XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK; } -#define REG_A7XX_HLSQ_CONTROL_2_REG 0x0000a9c8 -#define A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff -#define A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0 -static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) -{ - return ((val) << A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; -} -#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00 -#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8 -static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) -{ - return ((val) << A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK; -} -#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000 -#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16 -static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) -{ - return ((val) << A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK; -} -#define A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK 0xff000000 -#define A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT 24 -static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val) -{ - return ((val) << A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK; -} - #define REG_A6XX_HLSQ_CONTROL_3_REG 0x0000b984 #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff #define A6XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0 @@ -7296,32 +8181,6 @@ static inline uint32_t A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) return ((val) << A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A6XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK; } -#define REG_A7XX_HLSQ_CONTROL_3_REG 0x0000a9c9 -#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff -#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0 -static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val) -{ - return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK; -} -#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00 -#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8 -static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val) -{ - return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK; -} -#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000 -#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16 -static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val) -{ - return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK; -} -#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000 -#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24 -static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) -{ - return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK; -} - #define REG_A6XX_HLSQ_CONTROL_4_REG 0x0000b985 #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff #define A6XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0 @@ -7348,6 +8207,106 @@ static inline uint32_t A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) return ((val) << A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A6XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; } +#define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986 +#define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK 0x000000ff +#define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT 0 +static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val) +{ + return ((val) << A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK; +} +#define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK 0x0000ff00 +#define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT 8 +static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val) +{ + return ((val) << A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK; +} + +#define REG_A6XX_HLSQ_CS_CNTL 0x0000b987 +#define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff +#define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0 +static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val) +{ + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK; +} +#define A6XX_HLSQ_CS_CNTL_ENABLED 0x00000100 +#define A6XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 + +#define REG_A7XX_HLSQ_FS_CNTL_0 0x0000a9c6 +#define A7XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK 0x00000001 +#define A7XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT 0 +static inline uint32_t A7XX_HLSQ_FS_CNTL_0_THREADSIZE(enum a6xx_threadsize val) +{ + return ((val) << A7XX_HLSQ_FS_CNTL_0_THREADSIZE__SHIFT) & A7XX_HLSQ_FS_CNTL_0_THREADSIZE__MASK; +} +#define A7XX_HLSQ_FS_CNTL_0_VARYINGS 0x00000002 +#define A7XX_HLSQ_FS_CNTL_0_UNK2__MASK 0x00000ffc +#define A7XX_HLSQ_FS_CNTL_0_UNK2__SHIFT 2 +static inline uint32_t A7XX_HLSQ_FS_CNTL_0_UNK2(uint32_t val) +{ + return ((val) << A7XX_HLSQ_FS_CNTL_0_UNK2__SHIFT) & A7XX_HLSQ_FS_CNTL_0_UNK2__MASK; +} + +#define REG_A7XX_HLSQ_CONTROL_1_REG 0x0000a9c7 +#define A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK 0x00000007 +#define A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT 0 +static inline uint32_t A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__SHIFT) & A7XX_HLSQ_CONTROL_1_REG_PRIMALLOCTHRESHOLD__MASK; +} + +#define REG_A7XX_HLSQ_CONTROL_2_REG 0x0000a9c8 +#define A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK 0x000000ff +#define A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT 0 +static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_FACEREGID(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CONTROL_2_REG_FACEREGID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_FACEREGID__MASK; +} +#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK 0x0000ff00 +#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT 8 +static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_SAMPLEID(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEID__MASK; +} +#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK 0x00ff0000 +#define A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT 16 +static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_SAMPLEMASK__MASK; +} +#define A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK 0xff000000 +#define A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT 24 +static inline uint32_t A7XX_HLSQ_CONTROL_2_REG_CENTERRHW(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__SHIFT) & A7XX_HLSQ_CONTROL_2_REG_CENTERRHW__MASK; +} + +#define REG_A7XX_HLSQ_CONTROL_3_REG 0x0000a9c9 +#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK 0x000000ff +#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT 0 +static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_PIXEL__MASK; +} +#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK 0x0000ff00 +#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT 8 +static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_PIXEL__MASK; +} +#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK 0x00ff0000 +#define A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT 16 +static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_PERSP_CENTROID__MASK; +} +#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK 0xff000000 +#define A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT 24 +static inline uint32_t A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__SHIFT) & A7XX_HLSQ_CONTROL_3_REG_IJ_LINEAR_CENTROID__MASK; +} + #define REG_A7XX_HLSQ_CONTROL_4_REG 0x0000a9ca #define A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__MASK 0x000000ff #define A7XX_HLSQ_CONTROL_4_REG_IJ_PERSP_SAMPLE__SHIFT 0 @@ -7374,20 +8333,6 @@ static inline uint32_t A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID(uint32_t val) return ((val) << A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__SHIFT) & A7XX_HLSQ_CONTROL_4_REG_ZWCOORDREGID__MASK; } -#define REG_A6XX_HLSQ_CONTROL_5_REG 0x0000b986 -#define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK 0x000000ff -#define A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT 0 -static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID(uint32_t val) -{ - return ((val) << A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK; -} -#define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK 0x0000ff00 -#define A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT 8 -static inline uint32_t A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t val) -{ - return ((val) << A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A6XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK; -} - #define REG_A7XX_HLSQ_CONTROL_5_REG 0x0000a9cb #define A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__MASK 0x000000ff #define A7XX_HLSQ_CONTROL_5_REG_LINELENGTHREGID__SHIFT 0 @@ -7402,14 +8347,16 @@ static inline uint32_t A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID(uint32_t va return ((val) << A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__SHIFT) & A7XX_HLSQ_CONTROL_5_REG_FOVEATIONQUALITYREGID__MASK; } -#define REG_A6XX_HLSQ_CS_CNTL 0x0000b987 -#define A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff -#define A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0 -static inline uint32_t A6XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val) +#define REG_A7XX_HLSQ_CS_CNTL 0x0000a9cd +#define A7XX_HLSQ_CS_CNTL_CONSTLEN__MASK 0x000000ff +#define A7XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT 0 +static inline uint32_t A7XX_HLSQ_CS_CNTL_CONSTLEN(uint32_t val) { - return ((val >> 2) << A6XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_CS_CNTL_CONSTLEN__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A7XX_HLSQ_CS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_CS_CNTL_CONSTLEN__MASK; } -#define A6XX_HLSQ_CS_CNTL_ENABLED 0x00000100 +#define A7XX_HLSQ_CS_CNTL_ENABLED 0x00000100 +#define A7XX_HLSQ_CS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 #define REG_A6XX_HLSQ_CS_NDRANGE_0 0x0000b990 #define A6XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003 @@ -7533,19 +8480,136 @@ static inline uint32_t A6XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) #define REG_A6XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000b99b -#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD 0x0000b9a0 +#define REG_A7XX_HLSQ_CS_NDRANGE_0 0x0000a9d4 +#define A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK 0x00000003 +#define A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT 0 +static inline uint32_t A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_KERNELDIM__MASK; +} +#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK 0x00000ffc +#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT 2 +static inline uint32_t A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEX__MASK; +} +#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK 0x003ff000 +#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT 12 +static inline uint32_t A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEY__MASK; +} +#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK 0xffc00000 +#define A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT 22 +static inline uint32_t A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__SHIFT) & A7XX_HLSQ_CS_NDRANGE_0_LOCALSIZEZ__MASK; +} -#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR 0x0000b9a1 -#define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK 0xffffffff -#define A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT 0 -static inline uint32_t A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR(uint32_t val) +#define REG_A7XX_HLSQ_CS_NDRANGE_1 0x0000a9d5 +#define A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK 0xffffffff +#define A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT 0 +static inline uint32_t A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__SHIFT) & A7XX_HLSQ_CS_NDRANGE_1_GLOBALSIZE_X__MASK; +} + +#define REG_A7XX_HLSQ_CS_NDRANGE_2 0x0000a9d6 +#define A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK 0xffffffff +#define A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT 0 +static inline uint32_t A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__SHIFT) & A7XX_HLSQ_CS_NDRANGE_2_GLOBALOFF_X__MASK; +} + +#define REG_A7XX_HLSQ_CS_NDRANGE_3 0x0000a9d7 +#define A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK 0xffffffff +#define A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT 0 +static inline uint32_t A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__SHIFT) & A7XX_HLSQ_CS_NDRANGE_3_GLOBALSIZE_Y__MASK; +} + +#define REG_A7XX_HLSQ_CS_NDRANGE_4 0x0000a9d8 +#define A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK 0xffffffff +#define A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT 0 +static inline uint32_t A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__SHIFT) & A7XX_HLSQ_CS_NDRANGE_4_GLOBALOFF_Y__MASK; +} + +#define REG_A7XX_HLSQ_CS_NDRANGE_5 0x0000a9d9 +#define A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK 0xffffffff +#define A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT 0 +static inline uint32_t A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__SHIFT) & A7XX_HLSQ_CS_NDRANGE_5_GLOBALSIZE_Z__MASK; +} + +#define REG_A7XX_HLSQ_CS_NDRANGE_6 0x0000a9da +#define A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK 0xffffffff +#define A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT 0 +static inline uint32_t A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z(uint32_t val) { - return ((val) << A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__SHIFT) & A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR__MASK; + return ((val) << A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__SHIFT) & A7XX_HLSQ_CS_NDRANGE_6_GLOBALOFF_Z__MASK; } +#define REG_A7XX_HLSQ_CS_KERNEL_GROUP_X 0x0000a9dc + +#define REG_A7XX_HLSQ_CS_KERNEL_GROUP_Y 0x0000a9dd + +#define REG_A7XX_HLSQ_CS_KERNEL_GROUP_Z 0x0000a9de + +#define REG_A7XX_HLSQ_CS_CNTL_1 0x0000a9db +#define A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK 0x000000ff +#define A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT 0 +static inline uint32_t A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__SHIFT) & A7XX_HLSQ_CS_CNTL_1_LINEARLOCALIDREGID__MASK; +} +#define A7XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK 0x00000200 +#define A7XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT 9 +static inline uint32_t A7XX_HLSQ_CS_CNTL_1_THREADSIZE(enum a6xx_threadsize val) +{ + return ((val) << A7XX_HLSQ_CS_CNTL_1_THREADSIZE__SHIFT) & A7XX_HLSQ_CS_CNTL_1_THREADSIZE__MASK; +} +#define A7XX_HLSQ_CS_CNTL_1_UNK11 0x00000800 +#define A7XX_HLSQ_CS_CNTL_1_UNK22 0x00400000 +#define A7XX_HLSQ_CS_CNTL_1_UNK26 0x04000000 +#define A7XX_HLSQ_CS_CNTL_1_YALIGN__MASK 0x78000000 +#define A7XX_HLSQ_CS_CNTL_1_YALIGN__SHIFT 27 +static inline uint32_t A7XX_HLSQ_CS_CNTL_1_YALIGN(enum a7xx_cs_yalign val) +{ + return ((val) << A7XX_HLSQ_CS_CNTL_1_YALIGN__SHIFT) & A7XX_HLSQ_CS_CNTL_1_YALIGN__MASK; +} + +#define REG_A7XX_HLSQ_CS_LOCAL_SIZE 0x0000a9df +#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__MASK 0x00000ffc +#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__SHIFT 2 +static inline uint32_t A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__SHIFT) & A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEX__MASK; +} +#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__MASK 0x003ff000 +#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__SHIFT 12 +static inline uint32_t A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__SHIFT) & A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEY__MASK; +} +#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__MASK 0xffc00000 +#define A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__SHIFT 22 +static inline uint32_t A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ(uint32_t val) +{ + return ((val) << A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__SHIFT) & A7XX_HLSQ_CS_LOCAL_SIZE_LOCALSIZEZ__MASK; +} + +#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_CMD 0x0000b9a0 + +#define REG_A6XX_HLSQ_LOAD_STATE_FRAG_EXT_SRC_ADDR 0x0000b9a1 + #define REG_A6XX_HLSQ_LOAD_STATE_FRAG_DATA 0x0000b9a3 -static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; } +#define REG_A6XX_HLSQ_CS_BINDLESS_BASE(i0) (0x0000b9c0 + 0x2*(i0)) static inline uint32_t REG_A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000b9c0 + 0x2*i0; } #define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 @@ -7554,11 +8618,12 @@ static inline uint32_t A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx { return ((val) << A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; } -#define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffc +#define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc #define A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 -static inline uint32_t A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val) +static inline uint32_t A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) { - return ((val >> 2) << A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; } #define REG_A6XX_HLSQ_CS_UNKNOWN_B9D0 0x0000b9d0 @@ -7625,19 +8690,56 @@ static inline uint32_t A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val) return ((val) << A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK; } +#define REG_A7XX_HLSQ_INVALIDATE_CMD 0x0000ab1f +#define A7XX_HLSQ_INVALIDATE_CMD_VS_STATE 0x00000001 +#define A7XX_HLSQ_INVALIDATE_CMD_HS_STATE 0x00000002 +#define A7XX_HLSQ_INVALIDATE_CMD_DS_STATE 0x00000004 +#define A7XX_HLSQ_INVALIDATE_CMD_GS_STATE 0x00000008 +#define A7XX_HLSQ_INVALIDATE_CMD_FS_STATE 0x00000010 +#define A7XX_HLSQ_INVALIDATE_CMD_CS_STATE 0x00000020 +#define A7XX_HLSQ_INVALIDATE_CMD_CS_IBO 0x00000040 +#define A7XX_HLSQ_INVALIDATE_CMD_GFX_IBO 0x00000080 +#define A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK 0x0001fe00 +#define A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT 9 +static inline uint32_t A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(uint32_t val) +{ + return ((val) << A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__SHIFT) & A7XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS__MASK; +} +#define A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK 0x01fe0000 +#define A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT 17 +static inline uint32_t A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(uint32_t val) +{ + return ((val) << A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__SHIFT) & A7XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS__MASK; +} + #define REG_A6XX_HLSQ_FS_CNTL 0x0000bb10 #define A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff #define A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0 static inline uint32_t A6XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val) { - return ((val >> 2) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A6XX_HLSQ_FS_CNTL_CONSTLEN__MASK; } #define A6XX_HLSQ_FS_CNTL_ENABLED 0x00000100 +#define A6XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 + +#define REG_A7XX_HLSQ_FS_CNTL 0x0000ab03 +#define A7XX_HLSQ_FS_CNTL_CONSTLEN__MASK 0x000000ff +#define A7XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT 0 +static inline uint32_t A7XX_HLSQ_FS_CNTL_CONSTLEN(uint32_t val) +{ + assert(!(val & 0x3)); + return (((val >> 2)) << A7XX_HLSQ_FS_CNTL_CONSTLEN__SHIFT) & A7XX_HLSQ_FS_CNTL_CONSTLEN__MASK; +} +#define A7XX_HLSQ_FS_CNTL_ENABLED 0x00000100 +#define A7XX_HLSQ_FS_CNTL_READ_IMM_SHARED_CONSTS 0x00000200 + +#define REG_A7XX_HLSQ_SHARED_CONSTS_IMM(i0) (0x0000ab40 + 0x1*(i0)) #define REG_A6XX_HLSQ_SHARED_CONSTS 0x0000bb11 #define A6XX_HLSQ_SHARED_CONSTS_ENABLE 0x00000001 -static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE(uint32_t i0) { return 0x0000bb20 + 0x2*i0; } +#define REG_A6XX_HLSQ_BINDLESS_BASE(i0) (0x0000bb20 + 0x2*(i0)) static inline uint32_t REG_A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) { return 0x0000bb20 + 0x2*i0; } #define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK 0x00000003 @@ -7646,11 +8748,12 @@ static inline uint32_t A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE(enum a6xx_bi { return ((val) << A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__SHIFT) & A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_DESC_SIZE__MASK; } -#define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffc +#define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK 0xfffffffffffffffc #define A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT 2 -static inline uint32_t A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR(uint32_t val) +static inline uint32_t A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR(uint64_t val) { - return ((val >> 2) << A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__SHIFT) & A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR_ADDR__MASK; } #define REG_A6XX_HLSQ_2D_EVENT_CMD 0x0000bd80 @@ -7677,12 +8780,18 @@ static inline uint32_t A6XX_HLSQ_2D_EVENT_CMD_EVENT(enum vgt_event_type val) #define REG_A6XX_HLSQ_UNKNOWN_BE08 0x0000be08 -static inline uint32_t REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(uint32_t i0) { return 0x0000be10 + 0x1*i0; } +#define REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(i0) (0x0000be10 + 0x1*(i0)) #define REG_A6XX_HLSQ_CONTEXT_SWITCH_GFX_PREEMPTION_SAFE_MODE 0x0000be22 #define REG_A7XX_SP_AHB_READ_APERTURE 0x0000c000 +#define REG_A7XX_SP_UNKNOWN_0CE2 0x00000ce2 + +#define REG_A7XX_SP_UNKNOWN_0CE4 0x00000ce4 + +#define REG_A7XX_SP_UNKNOWN_0CE6 0x00000ce6 + #define REG_A6XX_CP_EVENT_START 0x0000d600 #define A6XX_CP_EVENT_START_STATE_ID__MASK 0x000000ff #define A6XX_CP_EVENT_START_STATE_ID__SHIFT 0 @@ -7907,17 +9016,19 @@ static inline uint32_t A6XX_TEX_CONST_2_TYPE(enum a6xx_tex_type val) } #define REG_A6XX_TEX_CONST_3 0x00000003 -#define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x00003fff +#define A6XX_TEX_CONST_3_ARRAY_PITCH__MASK 0x007fffff #define A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT 0 static inline uint32_t A6XX_TEX_CONST_3_ARRAY_PITCH(uint32_t val) { - return ((val >> 12) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A6XX_TEX_CONST_3_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_3_ARRAY_PITCH__MASK; } #define A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK 0x07800000 #define A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT 23 static inline uint32_t A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val) { - return ((val >> 12) << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK; + assert(!(val & 0xfff)); + return (((val >> 12)) << A6XX_TEX_CONST_3_MIN_LAYERSZ__SHIFT) & A6XX_TEX_CONST_3_MIN_LAYERSZ__MASK; } #define A6XX_TEX_CONST_3_TILE_ALL 0x08000000 #define A6XX_TEX_CONST_3_FLAG 0x10000000 @@ -7927,7 +9038,8 @@ static inline uint32_t A6XX_TEX_CONST_3_MIN_LAYERSZ(uint32_t val) #define A6XX_TEX_CONST_4_BASE_LO__SHIFT 5 static inline uint32_t A6XX_TEX_CONST_4_BASE_LO(uint32_t val) { - return ((val >> 5) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A6XX_TEX_CONST_4_BASE_LO__SHIFT) & A6XX_TEX_CONST_4_BASE_LO__MASK; } #define REG_A6XX_TEX_CONST_5 0x00000005 @@ -7963,7 +9075,8 @@ static inline uint32_t A6XX_TEX_CONST_6_PLANE_PITCH(uint32_t val) #define A6XX_TEX_CONST_7_FLAG_LO__SHIFT 5 static inline uint32_t A6XX_TEX_CONST_7_FLAG_LO(uint32_t val) { - return ((val >> 5) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK; + assert(!(val & 0x1f)); + return (((val >> 5)) << A6XX_TEX_CONST_7_FLAG_LO__SHIFT) & A6XX_TEX_CONST_7_FLAG_LO__MASK; } #define REG_A6XX_TEX_CONST_8 0x00000008 @@ -7979,7 +9092,8 @@ static inline uint32_t A6XX_TEX_CONST_8_FLAG_HI(uint32_t val) #define A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT 0 static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) { - return ((val >> 4) << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK; + assert(!(val & 0xf)); + return (((val >> 4)) << A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__SHIFT) & A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH__MASK; } #define REG_A6XX_TEX_CONST_10 0x0000000a @@ -7987,7 +9101,8 @@ static inline uint32_t A6XX_TEX_CONST_9_FLAG_BUFFER_ARRAY_PITCH(uint32_t val) #define A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT 0 static inline uint32_t A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH(uint32_t val) { - return ((val >> 6) << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK; + assert(!(val & 0x3f)); + return (((val >> 6)) << A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__SHIFT) & A6XX_TEX_CONST_10_FLAG_BUFFER_PITCH__MASK; } #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__MASK 0x00000f00 #define A6XX_TEX_CONST_10_FLAG_BUFFER_LOGW__SHIFT 8 @@ -8262,4 +9377,2482 @@ static inline uint32_t A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1_BYTEL15(uint32_t val) #define REG_A7XX_CX_MISC_TCM_RET_CNTL 0x00000039 +#ifdef __cplusplus +template<chip CHIP> constexpr inline uint16_t CMD_REGS[] = {}; +template<chip CHIP> constexpr inline uint16_t RP_BLIT_REGS[] = {}; +template<> constexpr inline uint16_t CMD_REGS<A6XX>[] = { + 0xc03, + 0xc04, + 0xc30, + 0xc31, + 0xc32, + 0xc33, + 0xc34, + 0xc35, + 0xc36, + 0xc37, + 0xe12, + 0xe17, + 0xe19, + 0x8099, + 0x80af, + 0x810a, + 0x8110, + 0x8600, + 0x880e, + 0x8811, + 0x8818, + 0x8819, + 0x881a, + 0x881b, + 0x881c, + 0x881d, + 0x881e, + 0x8864, + 0x8891, + 0x88f0, + 0x8927, + 0x8928, + 0x8e01, + 0x8e04, + 0x8e07, + 0x9210, + 0x9211, + 0x9218, + 0x9219, + 0x921a, + 0x921b, + 0x921c, + 0x921d, + 0x921e, + 0x921f, + 0x9220, + 0x9221, + 0x9222, + 0x9223, + 0x9224, + 0x9225, + 0x9226, + 0x9227, + 0x9228, + 0x9229, + 0x922a, + 0x922b, + 0x922c, + 0x922d, + 0x922e, + 0x922f, + 0x9230, + 0x9231, + 0x9232, + 0x9233, + 0x9234, + 0x9235, + 0x9236, + 0x9300, + 0x9600, + 0x9601, + 0x9602, + 0x9e08, + 0x9e09, + 0x9e72, + 0xa007, + 0xa009, + 0xa8a0, + 0xa8a1, + 0xa8a2, + 0xa8a3, + 0xa8a4, + 0xa8a5, + 0xa8a6, + 0xa8a7, + 0xa8a8, + 0xa8a9, + 0xa8aa, + 0xa8ab, + 0xa8ac, + 0xa8ad, + 0xa8ae, + 0xa8af, + 0xa9a8, + 0xa9b0, + 0xa9b1, + 0xa9b2, + 0xa9b3, + 0xa9b4, + 0xa9b5, + 0xa9b6, + 0xa9b7, + 0xa9b8, + 0xa9b9, + 0xa9ba, + 0xa9bb, + 0xa9bc, + 0xa9bd, + 0xa9c2, + 0xa9c3, + 0xa9e2, + 0xa9e3, + 0xa9e6, + 0xa9e7, + 0xa9e8, + 0xa9e9, + 0xa9ea, + 0xa9eb, + 0xa9ec, + 0xa9ed, + 0xa9ee, + 0xa9ef, + 0xa9f0, + 0xa9f1, + 0xaaf2, + 0xab1a, + 0xab1b, + 0xab20, + 0xae00, + 0xae03, + 0xae04, + 0xae0f, + 0xb180, + 0xb181, + 0xb182, + 0xb183, + 0xb302, + 0xb303, + 0xb309, + 0xb600, + 0xb602, + 0xb605, + 0xb987, + 0xb9d0, + 0xbb08, + 0xbb11, + 0xbb20, + 0xbb21, + 0xbb22, + 0xbb23, + 0xbb24, + 0xbb25, + 0xbb26, + 0xbb27, + 0xbb28, + 0xbb29, + 0xbe00, + 0xbe01, + 0xbe04, +}; +template<> constexpr inline uint16_t CMD_REGS<A7XX>[] = { + 0xc03, + 0xc04, + 0xc30, + 0xc31, + 0xc32, + 0xc33, + 0xc34, + 0xc35, + 0xc36, + 0xc37, + 0xce2, + 0xce3, + 0xce4, + 0xce5, + 0xce6, + 0xce7, + 0xe10, + 0xe11, + 0xe12, + 0xe17, + 0xe19, + 0x8008, + 0x8009, + 0x800a, + 0x800b, + 0x800c, + 0x8099, + 0x80a7, + 0x80af, + 0x80f4, + 0x80f5, + 0x80f5, + 0x80f6, + 0x80f6, + 0x80f7, + 0x80f8, + 0x80f9, + 0x80f9, + 0x80fa, + 0x80fa, + 0x80fb, + 0x810a, + 0x810b, + 0x8110, + 0x8120, + 0x8121, + 0x8600, + 0x880e, + 0x8811, + 0x8818, + 0x8819, + 0x881a, + 0x881b, + 0x881c, + 0x881d, + 0x881e, + 0x8864, + 0x8891, + 0x8899, + 0x88e5, + 0x88f0, + 0x8927, + 0x8928, + 0x8e01, + 0x8e04, + 0x8e06, + 0x8e07, + 0x8e09, + 0x8e79, + 0x9218, + 0x9219, + 0x921a, + 0x921b, + 0x921c, + 0x921d, + 0x921e, + 0x921f, + 0x9220, + 0x9221, + 0x9222, + 0x9223, + 0x9224, + 0x9225, + 0x9226, + 0x9227, + 0x9228, + 0x9229, + 0x922a, + 0x922b, + 0x922c, + 0x922d, + 0x922e, + 0x922f, + 0x9230, + 0x9231, + 0x9232, + 0x9233, + 0x9234, + 0x9235, + 0x9236, + 0x9300, + 0x9600, + 0x9601, + 0x9602, + 0x9810, + 0x9811, + 0x9e24, + 0x9e72, + 0xa007, + 0xa009, + 0xa600, + 0xa82d, + 0xa82f, + 0xa868, + 0xa899, + 0xa8a0, + 0xa8a1, + 0xa8a2, + 0xa8a3, + 0xa8a4, + 0xa8a5, + 0xa8a6, + 0xa8a7, + 0xa8a8, + 0xa8a9, + 0xa8aa, + 0xa8ab, + 0xa8ac, + 0xa8ad, + 0xa8ae, + 0xa8af, + 0xa9a8, + 0xa9ac, + 0xa9ad, + 0xa9b0, + 0xa9b1, + 0xa9b2, + 0xa9b3, + 0xa9b4, + 0xa9b5, + 0xa9b6, + 0xa9b7, + 0xa9b8, + 0xa9b9, + 0xa9ba, + 0xa9bb, + 0xa9bc, + 0xa9bd, + 0xa9be, + 0xa9c2, + 0xa9c3, + 0xa9c5, + 0xa9cd, + 0xa9df, + 0xa9e2, + 0xa9e3, + 0xa9e6, + 0xa9e7, + 0xa9e8, + 0xa9e9, + 0xa9ea, + 0xa9eb, + 0xa9ec, + 0xa9ed, + 0xa9ee, + 0xa9ef, + 0xa9f0, + 0xa9f1, + 0xa9f2, + 0xa9f3, + 0xa9f4, + 0xa9f5, + 0xa9f6, + 0xa9f7, + 0xaa01, + 0xaa02, + 0xaa03, + 0xaaf2, + 0xab01, + 0xab02, + 0xab1a, + 0xab1b, + 0xab1f, + 0xab20, + 0xab22, + 0xae00, + 0xae03, + 0xae04, + 0xae06, + 0xae08, + 0xae09, + 0xae0a, + 0xae0f, + 0xae6a, + 0xae6b, + 0xae6c, + 0xae73, + 0xb180, + 0xb181, + 0xb182, + 0xb183, + 0xb302, + 0xb303, + 0xb309, + 0xb310, + 0xb600, + 0xb602, + 0xb608, + 0xb609, + 0xb60a, + 0xb60b, + 0xb60c, +}; +template<> constexpr inline uint16_t RP_BLIT_REGS<A6XX>[] = { + 0xc02, + 0xc06, + 0xc10, + 0xc11, + 0xc12, + 0xc13, + 0xc14, + 0xc15, + 0xc16, + 0xc17, + 0xc18, + 0xc19, + 0xc1a, + 0xc1b, + 0xc1c, + 0xc1d, + 0xc1e, + 0xc1f, + 0xc20, + 0xc21, + 0xc22, + 0xc23, + 0xc24, + 0xc25, + 0xc26, + 0xc27, + 0xc28, + 0xc29, + 0xc2a, + 0xc2b, + 0xc2c, + 0xc2d, + 0xc2e, + 0xc2f, + 0xc38, + 0xc39, + 0xc3a, + 0xc3b, + 0xc3c, + 0xc3d, + 0xc3e, + 0xc3f, + 0xc40, + 0xc41, + 0xc42, + 0xc43, + 0xc44, + 0xc45, + 0xc46, + 0xc47, + 0xc48, + 0xc49, + 0xc4a, + 0xc4b, + 0xc4c, + 0xc4d, + 0xc4e, + 0xc4f, + 0xc50, + 0xc51, + 0xc52, + 0xc53, + 0xc54, + 0xc55, + 0xc56, + 0xc57, + 0xc58, + 0xc59, + 0xc5a, + 0xc5b, + 0xc5c, + 0xc5d, + 0xc5e, + 0xc5f, + 0xc60, + 0xc61, + 0xc62, + 0xc63, + 0xc64, + 0xc65, + 0xc66, + 0xc67, + 0xc68, + 0xc69, + 0xc6a, + 0xc6b, + 0xc6c, + 0xc6d, + 0xc6e, + 0xc6f, + 0xc70, + 0xc71, + 0xc72, + 0xc73, + 0xc74, + 0xc75, + 0xc76, + 0xc77, + 0xc78, + 0xc79, + 0xc7a, + 0xc7b, + 0xc7c, + 0xc7d, + 0xc7e, + 0xc7f, + 0xc80, + 0xc81, + 0xc82, + 0xc83, + 0xc84, + 0xc85, + 0xc86, + 0xc87, + 0xc88, + 0xc89, + 0xc8a, + 0xc8b, + 0xc8c, + 0xc8d, + 0xc8e, + 0xc8f, + 0xc90, + 0xc91, + 0xc92, + 0xc93, + 0xc94, + 0xc95, + 0xc96, + 0xc97, + 0x8000, + 0x8001, + 0x8002, + 0x8003, + 0x8004, + 0x8005, + 0x8006, + 0x8010, + 0x8011, + 0x8012, + 0x8013, + 0x8014, + 0x8015, + 0x8016, + 0x8017, + 0x8018, + 0x8019, + 0x801a, + 0x801b, + 0x801c, + 0x801d, + 0x801e, + 0x801f, + 0x8020, + 0x8021, + 0x8022, + 0x8023, + 0x8024, + 0x8025, + 0x8026, + 0x8027, + 0x8028, + 0x8029, + 0x802a, + 0x802b, + 0x802c, + 0x802d, + 0x802e, + 0x802f, + 0x8030, + 0x8031, + 0x8032, + 0x8033, + 0x8034, + 0x8035, + 0x8036, + 0x8037, + 0x8038, + 0x8039, + 0x803a, + 0x803b, + 0x803c, + 0x803d, + 0x803e, + 0x803f, + 0x8040, + 0x8041, + 0x8042, + 0x8043, + 0x8044, + 0x8045, + 0x8046, + 0x8047, + 0x8048, + 0x8049, + 0x804a, + 0x804b, + 0x804c, + 0x804d, + 0x804e, + 0x804f, + 0x8050, + 0x8051, + 0x8052, + 0x8053, + 0x8054, + 0x8055, + 0x8056, + 0x8057, + 0x8058, + 0x8059, + 0x805a, + 0x805b, + 0x805c, + 0x805d, + 0x805e, + 0x805f, + 0x8060, + 0x8061, + 0x8062, + 0x8063, + 0x8064, + 0x8065, + 0x8066, + 0x8067, + 0x8068, + 0x8069, + 0x806a, + 0x806b, + 0x806c, + 0x806d, + 0x806e, + 0x806f, + 0x8070, + 0x8071, + 0x8072, + 0x8073, + 0x8074, + 0x8075, + 0x8076, + 0x8077, + 0x8078, + 0x8079, + 0x807a, + 0x807b, + 0x807c, + 0x807d, + 0x807e, + 0x807f, + 0x8080, + 0x8081, + 0x8082, + 0x8083, + 0x8084, + 0x8085, + 0x8086, + 0x8087, + 0x8088, + 0x8089, + 0x808a, + 0x808b, + 0x808c, + 0x808d, + 0x808e, + 0x808f, + 0x8090, + 0x8091, + 0x8092, + 0x8094, + 0x8095, + 0x8096, + 0x8097, + 0x8098, + 0x809b, + 0x809c, + 0x809d, + 0x80a0, + 0x80a1, + 0x80a2, + 0x80a3, + 0x80a4, + 0x80a5, + 0x80a6, + 0x80b0, + 0x80b1, + 0x80b2, + 0x80b3, + 0x80b4, + 0x80b5, + 0x80b6, + 0x80b7, + 0x80b8, + 0x80b9, + 0x80ba, + 0x80bb, + 0x80bc, + 0x80bd, + 0x80be, + 0x80bf, + 0x80c0, + 0x80c1, + 0x80c2, + 0x80c3, + 0x80c4, + 0x80c5, + 0x80c6, + 0x80c7, + 0x80c8, + 0x80c9, + 0x80ca, + 0x80cb, + 0x80cc, + 0x80cd, + 0x80ce, + 0x80cf, + 0x80d0, + 0x80d1, + 0x80d2, + 0x80d3, + 0x80d4, + 0x80d5, + 0x80d6, + 0x80d7, + 0x80d8, + 0x80d9, + 0x80da, + 0x80db, + 0x80dc, + 0x80dd, + 0x80de, + 0x80df, + 0x80e0, + 0x80e1, + 0x80e2, + 0x80e3, + 0x80e4, + 0x80e5, + 0x80e6, + 0x80e7, + 0x80e8, + 0x80e9, + 0x80ea, + 0x80eb, + 0x80ec, + 0x80ed, + 0x80ee, + 0x80ef, + 0x80f0, + 0x80f1, + 0x8100, + 0x8101, + 0x8102, + 0x8103, + 0x8104, + 0x8105, + 0x8106, + 0x8107, + 0x8109, + 0x8114, + 0x8115, + 0x8400, + 0x8401, + 0x8402, + 0x8403, + 0x8404, + 0x8405, + 0x8406, + 0x840a, + 0x840b, + 0x8800, + 0x8801, + 0x8802, + 0x8803, + 0x8804, + 0x8805, + 0x8806, + 0x8809, + 0x880a, + 0x880b, + 0x880c, + 0x880d, + 0x880f, + 0x8810, + 0x8820, + 0x8821, + 0x8822, + 0x8823, + 0x8824, + 0x8825, + 0x8826, + 0x8827, + 0x8828, + 0x8829, + 0x882a, + 0x882b, + 0x882c, + 0x882d, + 0x882e, + 0x882f, + 0x8830, + 0x8831, + 0x8832, + 0x8833, + 0x8834, + 0x8835, + 0x8836, + 0x8837, + 0x8838, + 0x8839, + 0x883a, + 0x883b, + 0x883c, + 0x883d, + 0x883e, + 0x883f, + 0x8840, + 0x8841, + 0x8842, + 0x8843, + 0x8844, + 0x8845, + 0x8846, + 0x8847, + 0x8848, + 0x8849, + 0x884a, + 0x884b, + 0x884c, + 0x884d, + 0x884e, + 0x884f, + 0x8850, + 0x8851, + 0x8852, + 0x8853, + 0x8854, + 0x8855, + 0x8856, + 0x8857, + 0x8858, + 0x8859, + 0x885a, + 0x885b, + 0x885c, + 0x885d, + 0x885e, + 0x885f, + 0x8860, + 0x8861, + 0x8862, + 0x8863, + 0x8865, + 0x8870, + 0x8871, + 0x8872, + 0x8873, + 0x8874, + 0x8875, + 0x8876, + 0x8877, + 0x8878, + 0x8879, + 0x8880, + 0x8881, + 0x8882, + 0x8883, + 0x8884, + 0x8885, + 0x8886, + 0x8887, + 0x8888, + 0x8889, + 0x8890, + 0x8898, + 0x88c0, + 0x88c1, + 0x88d0, + 0x88d1, + 0x88d2, + 0x88d3, + 0x88d4, + 0x88d5, + 0x88d6, + 0x88d7, + 0x88d8, + 0x88d9, + 0x88da, + 0x88db, + 0x88dc, + 0x88dd, + 0x88de, + 0x88df, + 0x88e0, + 0x88e1, + 0x88e2, + 0x88e3, + 0x8900, + 0x8901, + 0x8902, + 0x8903, + 0x8904, + 0x8905, + 0x8906, + 0x8907, + 0x8908, + 0x8909, + 0x890a, + 0x890b, + 0x890c, + 0x890d, + 0x890e, + 0x890f, + 0x8910, + 0x8911, + 0x8912, + 0x8913, + 0x8914, + 0x8915, + 0x8916, + 0x8917, + 0x8918, + 0x8919, + 0x891a, + 0x8a00, + 0x8a10, + 0x8a20, + 0x8a30, + 0x8c00, + 0x8c01, + 0x8c17, + 0x8c18, + 0x8c19, + 0x8c1a, + 0x8c1b, + 0x8c1c, + 0x8c1d, + 0x8c1e, + 0x8c1f, + 0x8c20, + 0x8c21, + 0x8c22, + 0x8c23, + 0x8c24, + 0x8c25, + 0x8c2c, + 0x8c2d, + 0x8c2e, + 0x8c2f, + 0x9100, + 0x9101, + 0x9102, + 0x9103, + 0x9104, + 0x9105, + 0x9106, + 0x9107, + 0x9108, + 0x9200, + 0x9201, + 0x9202, + 0x9203, + 0x9204, + 0x9205, + 0x9206, + 0x9207, + 0x9208, + 0x9209, + 0x920a, + 0x920b, + 0x920c, + 0x920d, + 0x920e, + 0x920f, + 0x9212, + 0x9213, + 0x9214, + 0x9215, + 0x9216, + 0x9217, + 0x9301, + 0x9302, + 0x9303, + 0x9304, + 0x9305, + 0x9306, + 0x9311, + 0x9312, + 0x9313, + 0x9314, + 0x9315, + 0x9316, + 0x9800, + 0x9801, + 0x9802, + 0x9803, + 0x9804, + 0x9805, + 0x9806, + 0x9808, + 0x9980, + 0x9981, + 0x9b00, + 0x9b01, + 0x9b02, + 0x9b03, + 0x9b04, + 0x9b05, + 0x9b06, + 0x9b07, + 0x9b08, + 0xa000, + 0xa001, + 0xa002, + 0xa003, + 0xa004, + 0xa005, + 0xa006, + 0xa008, + 0xa00e, + 0xa00f, + 0xa010, + 0xa011, + 0xa012, + 0xa013, + 0xa014, + 0xa015, + 0xa016, + 0xa017, + 0xa018, + 0xa019, + 0xa01a, + 0xa01b, + 0xa01c, + 0xa01d, + 0xa01e, + 0xa01f, + 0xa020, + 0xa021, + 0xa022, + 0xa023, + 0xa024, + 0xa025, + 0xa026, + 0xa027, + 0xa028, + 0xa029, + 0xa02a, + 0xa02b, + 0xa02c, + 0xa02d, + 0xa02e, + 0xa02f, + 0xa030, + 0xa031, + 0xa032, + 0xa033, + 0xa034, + 0xa035, + 0xa036, + 0xa037, + 0xa038, + 0xa039, + 0xa03a, + 0xa03b, + 0xa03c, + 0xa03d, + 0xa03e, + 0xa03f, + 0xa040, + 0xa041, + 0xa042, + 0xa043, + 0xa044, + 0xa045, + 0xa046, + 0xa047, + 0xa048, + 0xa049, + 0xa04a, + 0xa04b, + 0xa04c, + 0xa04d, + 0xa04e, + 0xa04f, + 0xa050, + 0xa051, + 0xa052, + 0xa053, + 0xa054, + 0xa055, + 0xa056, + 0xa057, + 0xa058, + 0xa059, + 0xa05a, + 0xa05b, + 0xa05c, + 0xa05d, + 0xa05e, + 0xa05f, + 0xa060, + 0xa061, + 0xa062, + 0xa063, + 0xa064, + 0xa065, + 0xa066, + 0xa067, + 0xa068, + 0xa069, + 0xa06a, + 0xa06b, + 0xa06c, + 0xa06d, + 0xa06e, + 0xa06f, + 0xa070, + 0xa071, + 0xa072, + 0xa073, + 0xa074, + 0xa075, + 0xa076, + 0xa077, + 0xa078, + 0xa079, + 0xa07a, + 0xa07b, + 0xa07c, + 0xa07d, + 0xa07e, + 0xa07f, + 0xa080, + 0xa081, + 0xa082, + 0xa083, + 0xa084, + 0xa085, + 0xa086, + 0xa087, + 0xa088, + 0xa089, + 0xa08a, + 0xa08b, + 0xa08c, + 0xa08d, + 0xa08e, + 0xa08f, + 0xa090, + 0xa091, + 0xa092, + 0xa093, + 0xa094, + 0xa095, + 0xa096, + 0xa097, + 0xa098, + 0xa099, + 0xa09a, + 0xa09b, + 0xa09c, + 0xa09d, + 0xa09e, + 0xa09f, + 0xa0a0, + 0xa0a1, + 0xa0a2, + 0xa0a3, + 0xa0a4, + 0xa0a5, + 0xa0a6, + 0xa0a7, + 0xa0a8, + 0xa0a9, + 0xa0aa, + 0xa0ab, + 0xa0ac, + 0xa0ad, + 0xa0ae, + 0xa0af, + 0xa0b0, + 0xa0b1, + 0xa0b2, + 0xa0b3, + 0xa0b4, + 0xa0b5, + 0xa0b6, + 0xa0b7, + 0xa0b8, + 0xa0b9, + 0xa0ba, + 0xa0bb, + 0xa0bc, + 0xa0bd, + 0xa0be, + 0xa0bf, + 0xa0c0, + 0xa0c1, + 0xa0c2, + 0xa0c3, + 0xa0c4, + 0xa0c5, + 0xa0c6, + 0xa0c7, + 0xa0c8, + 0xa0c9, + 0xa0ca, + 0xa0cb, + 0xa0cc, + 0xa0cd, + 0xa0ce, + 0xa0cf, + 0xa0d0, + 0xa0d1, + 0xa0d2, + 0xa0d3, + 0xa0d4, + 0xa0d5, + 0xa0d6, + 0xa0d7, + 0xa0d8, + 0xa0d9, + 0xa0da, + 0xa0db, + 0xa0dc, + 0xa0dd, + 0xa0de, + 0xa0df, + 0xa0e0, + 0xa0e1, + 0xa0e2, + 0xa0e3, + 0xa0e4, + 0xa0e5, + 0xa0e6, + 0xa0e7, + 0xa0e8, + 0xa0e9, + 0xa0ea, + 0xa0eb, + 0xa0ec, + 0xa0ed, + 0xa0ee, + 0xa0ef, + 0xa0f8, + 0xa800, + 0xa802, + 0xa803, + 0xa804, + 0xa805, + 0xa806, + 0xa807, + 0xa808, + 0xa809, + 0xa80a, + 0xa80b, + 0xa80c, + 0xa80d, + 0xa80e, + 0xa80f, + 0xa810, + 0xa811, + 0xa812, + 0xa813, + 0xa814, + 0xa815, + 0xa816, + 0xa817, + 0xa818, + 0xa819, + 0xa81a, + 0xa81b, + 0xa81c, + 0xa81d, + 0xa81e, + 0xa81f, + 0xa820, + 0xa821, + 0xa822, + 0xa823, + 0xa824, + 0xa825, + 0xa830, + 0xa831, + 0xa832, + 0xa833, + 0xa834, + 0xa835, + 0xa836, + 0xa837, + 0xa838, + 0xa839, + 0xa83a, + 0xa83b, + 0xa83c, + 0xa83d, + 0xa840, + 0xa842, + 0xa843, + 0xa844, + 0xa845, + 0xa846, + 0xa847, + 0xa848, + 0xa849, + 0xa84a, + 0xa84b, + 0xa84c, + 0xa84d, + 0xa84e, + 0xa84f, + 0xa850, + 0xa851, + 0xa852, + 0xa853, + 0xa854, + 0xa855, + 0xa856, + 0xa857, + 0xa858, + 0xa859, + 0xa85a, + 0xa85b, + 0xa85c, + 0xa85d, + 0xa85e, + 0xa85f, + 0xa860, + 0xa861, + 0xa862, + 0xa863, + 0xa864, + 0xa865, + 0xa870, + 0xa871, + 0xa872, + 0xa873, + 0xa874, + 0xa875, + 0xa876, + 0xa877, + 0xa878, + 0xa879, + 0xa87a, + 0xa87b, + 0xa87c, + 0xa87d, + 0xa87e, + 0xa87f, + 0xa880, + 0xa881, + 0xa882, + 0xa883, + 0xa884, + 0xa885, + 0xa886, + 0xa887, + 0xa888, + 0xa889, + 0xa88a, + 0xa88b, + 0xa88c, + 0xa88d, + 0xa88e, + 0xa88f, + 0xa890, + 0xa891, + 0xa892, + 0xa893, + 0xa894, + 0xa895, + 0xa896, + 0xa980, + 0xa982, + 0xa983, + 0xa984, + 0xa985, + 0xa986, + 0xa987, + 0xa988, + 0xa989, + 0xa98a, + 0xa98b, + 0xa98c, + 0xa98d, + 0xa98e, + 0xa98f, + 0xa990, + 0xa991, + 0xa992, + 0xa993, + 0xa994, + 0xa995, + 0xa996, + 0xa997, + 0xa998, + 0xa999, + 0xa99a, + 0xa99b, + 0xa99c, + 0xa99d, + 0xa99e, + 0xa99f, + 0xa9a0, + 0xa9a1, + 0xa9a2, + 0xa9a3, + 0xa9a4, + 0xa9a5, + 0xa9a6, + 0xa9a7, + 0xa9a9, + 0xa9e0, + 0xa9e1, + 0xa9e4, + 0xa9e5, + 0xab00, + 0xab04, + 0xab05, + 0xab10, + 0xab11, + 0xab12, + 0xab13, + 0xab14, + 0xab15, + 0xab16, + 0xab17, + 0xab18, + 0xab19, + 0xacc0, + 0xb300, + 0xb301, + 0xb304, + 0xb305, + 0xb306, + 0xb307, + 0xb4c0, + 0xb4c1, + 0xb4c2, + 0xb4c3, + 0xb4c4, + 0xb4ca, + 0xb4cb, + 0xb4cc, + 0xb4d1, + 0xb800, + 0xb801, + 0xb802, + 0xb803, + 0xb980, + 0xb982, + 0xb983, + 0xb984, + 0xb985, + 0xb986, + 0xb990, + 0xb991, + 0xb992, + 0xb993, + 0xb994, + 0xb995, + 0xb996, + 0xb997, + 0xb998, + 0xb999, + 0xb99a, + 0xb99b, + 0xb9c0, + 0xb9c1, + 0xb9c2, + 0xb9c3, + 0xb9c4, + 0xb9c5, + 0xb9c6, + 0xb9c7, + 0xb9c8, + 0xb9c9, + 0xbb10, +}; +template<> constexpr inline uint16_t RP_BLIT_REGS<A7XX>[] = { + 0xc02, + 0xc06, + 0xc10, + 0xc11, + 0xc12, + 0xc13, + 0xc14, + 0xc15, + 0xc16, + 0xc17, + 0xc18, + 0xc19, + 0xc1a, + 0xc1b, + 0xc1c, + 0xc1d, + 0xc1e, + 0xc1f, + 0xc20, + 0xc21, + 0xc22, + 0xc23, + 0xc24, + 0xc25, + 0xc26, + 0xc27, + 0xc28, + 0xc29, + 0xc2a, + 0xc2b, + 0xc2c, + 0xc2d, + 0xc2e, + 0xc2f, + 0xc38, + 0xc39, + 0xc3a, + 0xc3b, + 0xc3c, + 0xc3d, + 0xc3e, + 0xc3f, + 0xc40, + 0xc41, + 0xc42, + 0xc43, + 0xc44, + 0xc45, + 0xc46, + 0xc47, + 0xc48, + 0xc49, + 0xc4a, + 0xc4b, + 0xc4c, + 0xc4d, + 0xc4e, + 0xc4f, + 0xc50, + 0xc51, + 0xc52, + 0xc53, + 0xc54, + 0xc55, + 0xc56, + 0xc57, + 0x8000, + 0x8001, + 0x8002, + 0x8003, + 0x8004, + 0x8005, + 0x8006, + 0x8007, + 0x8010, + 0x8011, + 0x8012, + 0x8013, + 0x8014, + 0x8015, + 0x8016, + 0x8017, + 0x8018, + 0x8019, + 0x801a, + 0x801b, + 0x801c, + 0x801d, + 0x801e, + 0x801f, + 0x8020, + 0x8021, + 0x8022, + 0x8023, + 0x8024, + 0x8025, + 0x8026, + 0x8027, + 0x8028, + 0x8029, + 0x802a, + 0x802b, + 0x802c, + 0x802d, + 0x802e, + 0x802f, + 0x8030, + 0x8031, + 0x8032, + 0x8033, + 0x8034, + 0x8035, + 0x8036, + 0x8037, + 0x8038, + 0x8039, + 0x803a, + 0x803b, + 0x803c, + 0x803d, + 0x803e, + 0x803f, + 0x8040, + 0x8041, + 0x8042, + 0x8043, + 0x8044, + 0x8045, + 0x8046, + 0x8047, + 0x8048, + 0x8049, + 0x804a, + 0x804b, + 0x804c, + 0x804d, + 0x804e, + 0x804f, + 0x8050, + 0x8051, + 0x8052, + 0x8053, + 0x8054, + 0x8055, + 0x8056, + 0x8057, + 0x8058, + 0x8059, + 0x805a, + 0x805b, + 0x805c, + 0x805d, + 0x805e, + 0x805f, + 0x8060, + 0x8061, + 0x8062, + 0x8063, + 0x8064, + 0x8065, + 0x8066, + 0x8067, + 0x8068, + 0x8069, + 0x806a, + 0x806b, + 0x806c, + 0x806d, + 0x806e, + 0x806f, + 0x8070, + 0x8071, + 0x8072, + 0x8073, + 0x8074, + 0x8075, + 0x8076, + 0x8077, + 0x8078, + 0x8079, + 0x807a, + 0x807b, + 0x807c, + 0x807d, + 0x807e, + 0x807f, + 0x8080, + 0x8081, + 0x8082, + 0x8083, + 0x8084, + 0x8085, + 0x8086, + 0x8087, + 0x8088, + 0x8089, + 0x808a, + 0x808b, + 0x808c, + 0x808d, + 0x808e, + 0x808f, + 0x8090, + 0x8091, + 0x8092, + 0x8094, + 0x8095, + 0x8096, + 0x8097, + 0x8098, + 0x809b, + 0x809c, + 0x809d, + 0x80a0, + 0x80a1, + 0x80a2, + 0x80a3, + 0x80a4, + 0x80a5, + 0x80a6, + 0x80b0, + 0x80b1, + 0x80b2, + 0x80b3, + 0x80b4, + 0x80b5, + 0x80b6, + 0x80b7, + 0x80b8, + 0x80b9, + 0x80ba, + 0x80bb, + 0x80bc, + 0x80bd, + 0x80be, + 0x80bf, + 0x80c0, + 0x80c1, + 0x80c2, + 0x80c3, + 0x80c4, + 0x80c5, + 0x80c6, + 0x80c7, + 0x80c8, + 0x80c9, + 0x80ca, + 0x80cb, + 0x80cc, + 0x80cd, + 0x80ce, + 0x80cf, + 0x80d0, + 0x80d1, + 0x80d2, + 0x80d3, + 0x80d4, + 0x80d5, + 0x80d6, + 0x80d7, + 0x80d8, + 0x80d9, + 0x80da, + 0x80db, + 0x80dc, + 0x80dd, + 0x80de, + 0x80df, + 0x80e0, + 0x80e1, + 0x80e2, + 0x80e3, + 0x80e4, + 0x80e5, + 0x80e6, + 0x80e7, + 0x80e8, + 0x80e9, + 0x80ea, + 0x80eb, + 0x80ec, + 0x80ed, + 0x80ee, + 0x80ef, + 0x80f0, + 0x80f1, + 0x8100, + 0x8101, + 0x8102, + 0x8103, + 0x8104, + 0x8105, + 0x8106, + 0x8107, + 0x8109, + 0x8113, + 0x8114, + 0x8115, + 0x8116, + 0x8400, + 0x8401, + 0x8402, + 0x8403, + 0x8404, + 0x8405, + 0x8406, + 0x840a, + 0x840b, + 0x8800, + 0x8801, + 0x8802, + 0x8803, + 0x8804, + 0x8805, + 0x8806, + 0x8809, + 0x880a, + 0x880b, + 0x880c, + 0x880d, + 0x880f, + 0x8810, + 0x8812, + 0x8820, + 0x8821, + 0x8822, + 0x8823, + 0x8824, + 0x8825, + 0x8826, + 0x8827, + 0x8828, + 0x8829, + 0x882a, + 0x882b, + 0x882c, + 0x882d, + 0x882e, + 0x882f, + 0x8830, + 0x8831, + 0x8832, + 0x8833, + 0x8834, + 0x8835, + 0x8836, + 0x8837, + 0x8838, + 0x8839, + 0x883a, + 0x883b, + 0x883c, + 0x883d, + 0x883e, + 0x883f, + 0x8840, + 0x8841, + 0x8842, + 0x8843, + 0x8844, + 0x8845, + 0x8846, + 0x8847, + 0x8848, + 0x8849, + 0x884a, + 0x884b, + 0x884c, + 0x884d, + 0x884e, + 0x884f, + 0x8850, + 0x8851, + 0x8852, + 0x8853, + 0x8854, + 0x8855, + 0x8856, + 0x8857, + 0x8858, + 0x8859, + 0x885a, + 0x885b, + 0x885c, + 0x885d, + 0x885e, + 0x885f, + 0x8860, + 0x8861, + 0x8862, + 0x8863, + 0x8865, + 0x8870, + 0x8871, + 0x8872, + 0x8873, + 0x8874, + 0x8875, + 0x8876, + 0x8877, + 0x8878, + 0x8879, + 0x8880, + 0x8881, + 0x8882, + 0x8883, + 0x8884, + 0x8885, + 0x8886, + 0x8887, + 0x8888, + 0x8889, + 0x8890, + 0x8898, + 0x88c0, + 0x88c1, + 0x88d0, + 0x88d1, + 0x88d2, + 0x88d3, + 0x88d4, + 0x88d5, + 0x88d6, + 0x88d7, + 0x88d8, + 0x88d9, + 0x88da, + 0x88db, + 0x88dc, + 0x88dd, + 0x88de, + 0x88df, + 0x88e0, + 0x88e1, + 0x88e2, + 0x88e3, + 0x8900, + 0x8901, + 0x8902, + 0x8903, + 0x8904, + 0x8905, + 0x8906, + 0x8907, + 0x8908, + 0x8909, + 0x890a, + 0x890b, + 0x890c, + 0x890d, + 0x890e, + 0x890f, + 0x8910, + 0x8911, + 0x8912, + 0x8913, + 0x8914, + 0x8915, + 0x8916, + 0x8917, + 0x8918, + 0x8919, + 0x891a, + 0x8c00, + 0x8c01, + 0x8c17, + 0x8c18, + 0x8c19, + 0x8c1a, + 0x8c1b, + 0x8c1c, + 0x8c1d, + 0x8c1e, + 0x8c1f, + 0x8c20, + 0x8c21, + 0x8c22, + 0x8c23, + 0x8c24, + 0x8c25, + 0x8c2c, + 0x8c2d, + 0x8c2e, + 0x8c2f, + 0x9101, + 0x9102, + 0x9103, + 0x9104, + 0x9105, + 0x9106, + 0x9107, + 0x9108, + 0x9109, + 0x910a, + 0x910b, + 0x910c, + 0x9200, + 0x9201, + 0x9202, + 0x9203, + 0x9204, + 0x9205, + 0x9206, + 0x9207, + 0x9208, + 0x9209, + 0x920a, + 0x920b, + 0x920c, + 0x920d, + 0x920e, + 0x920f, + 0x9212, + 0x9213, + 0x9214, + 0x9215, + 0x9216, + 0x9217, + 0x9301, + 0x9302, + 0x9303, + 0x9304, + 0x9305, + 0x9306, + 0x9307, + 0x9308, + 0x9309, + 0x9311, + 0x9312, + 0x9313, + 0x9314, + 0x9315, + 0x9316, + 0x9317, + 0x9800, + 0x9801, + 0x9802, + 0x9803, + 0x9804, + 0x9805, + 0x9806, + 0x9808, + 0x9809, + 0x9b00, + 0x9b01, + 0x9b02, + 0x9b03, + 0x9b04, + 0x9b05, + 0x9b07, + 0x9b08, + 0x9b09, + 0xa000, + 0xa001, + 0xa002, + 0xa003, + 0xa004, + 0xa005, + 0xa006, + 0xa008, + 0xa00e, + 0xa00f, + 0xa010, + 0xa011, + 0xa012, + 0xa013, + 0xa014, + 0xa015, + 0xa016, + 0xa017, + 0xa018, + 0xa019, + 0xa01a, + 0xa01b, + 0xa01c, + 0xa01d, + 0xa01e, + 0xa01f, + 0xa020, + 0xa021, + 0xa022, + 0xa023, + 0xa024, + 0xa025, + 0xa026, + 0xa027, + 0xa028, + 0xa029, + 0xa02a, + 0xa02b, + 0xa02c, + 0xa02d, + 0xa02e, + 0xa02f, + 0xa030, + 0xa031, + 0xa032, + 0xa033, + 0xa034, + 0xa035, + 0xa036, + 0xa037, + 0xa038, + 0xa039, + 0xa03a, + 0xa03b, + 0xa03c, + 0xa03d, + 0xa03e, + 0xa03f, + 0xa040, + 0xa041, + 0xa042, + 0xa043, + 0xa044, + 0xa045, + 0xa046, + 0xa047, + 0xa048, + 0xa049, + 0xa04a, + 0xa04b, + 0xa04c, + 0xa04d, + 0xa04e, + 0xa04f, + 0xa050, + 0xa051, + 0xa052, + 0xa053, + 0xa054, + 0xa055, + 0xa056, + 0xa057, + 0xa058, + 0xa059, + 0xa05a, + 0xa05b, + 0xa05c, + 0xa05d, + 0xa05e, + 0xa05f, + 0xa060, + 0xa061, + 0xa062, + 0xa063, + 0xa064, + 0xa065, + 0xa066, + 0xa067, + 0xa068, + 0xa069, + 0xa06a, + 0xa06b, + 0xa06c, + 0xa06d, + 0xa06e, + 0xa06f, + 0xa070, + 0xa071, + 0xa072, + 0xa073, + 0xa074, + 0xa075, + 0xa076, + 0xa077, + 0xa078, + 0xa079, + 0xa07a, + 0xa07b, + 0xa07c, + 0xa07d, + 0xa07e, + 0xa07f, + 0xa080, + 0xa081, + 0xa082, + 0xa083, + 0xa084, + 0xa085, + 0xa086, + 0xa087, + 0xa088, + 0xa089, + 0xa08a, + 0xa08b, + 0xa08c, + 0xa08d, + 0xa08e, + 0xa08f, + 0xa090, + 0xa091, + 0xa092, + 0xa093, + 0xa094, + 0xa095, + 0xa096, + 0xa097, + 0xa098, + 0xa099, + 0xa09a, + 0xa09b, + 0xa09c, + 0xa09d, + 0xa09e, + 0xa09f, + 0xa0a0, + 0xa0a1, + 0xa0a2, + 0xa0a3, + 0xa0a4, + 0xa0a5, + 0xa0a6, + 0xa0a7, + 0xa0a8, + 0xa0a9, + 0xa0aa, + 0xa0ab, + 0xa0ac, + 0xa0ad, + 0xa0ae, + 0xa0af, + 0xa0b0, + 0xa0b1, + 0xa0b2, + 0xa0b3, + 0xa0b4, + 0xa0b5, + 0xa0b6, + 0xa0b7, + 0xa0b8, + 0xa0b9, + 0xa0ba, + 0xa0bb, + 0xa0bc, + 0xa0bd, + 0xa0be, + 0xa0bf, + 0xa0c0, + 0xa0c1, + 0xa0c2, + 0xa0c3, + 0xa0c4, + 0xa0c5, + 0xa0c6, + 0xa0c7, + 0xa0c8, + 0xa0c9, + 0xa0ca, + 0xa0cb, + 0xa0cc, + 0xa0cd, + 0xa0ce, + 0xa0cf, + 0xa0d0, + 0xa0d1, + 0xa0d2, + 0xa0d3, + 0xa0d4, + 0xa0d5, + 0xa0d6, + 0xa0d7, + 0xa0d8, + 0xa0d9, + 0xa0da, + 0xa0db, + 0xa0dc, + 0xa0dd, + 0xa0de, + 0xa0df, + 0xa0e0, + 0xa0e1, + 0xa0e2, + 0xa0e3, + 0xa0e4, + 0xa0e5, + 0xa0e6, + 0xa0e7, + 0xa0e8, + 0xa0e9, + 0xa0ea, + 0xa0eb, + 0xa0ec, + 0xa0ed, + 0xa0ee, + 0xa0ef, + 0xa0f8, + 0xa800, + 0xa802, + 0xa803, + 0xa804, + 0xa805, + 0xa806, + 0xa807, + 0xa808, + 0xa809, + 0xa80a, + 0xa80b, + 0xa80c, + 0xa80d, + 0xa80e, + 0xa80f, + 0xa810, + 0xa811, + 0xa812, + 0xa813, + 0xa814, + 0xa815, + 0xa816, + 0xa817, + 0xa818, + 0xa819, + 0xa81a, + 0xa81b, + 0xa81c, + 0xa81d, + 0xa81e, + 0xa81f, + 0xa820, + 0xa821, + 0xa822, + 0xa823, + 0xa824, + 0xa825, + 0xa827, + 0xa830, + 0xa831, + 0xa832, + 0xa833, + 0xa834, + 0xa835, + 0xa836, + 0xa837, + 0xa838, + 0xa839, + 0xa83a, + 0xa83b, + 0xa83c, + 0xa83d, + 0xa83f, + 0xa840, + 0xa842, + 0xa843, + 0xa844, + 0xa845, + 0xa846, + 0xa847, + 0xa848, + 0xa849, + 0xa84a, + 0xa84b, + 0xa84c, + 0xa84d, + 0xa84e, + 0xa84f, + 0xa850, + 0xa851, + 0xa852, + 0xa853, + 0xa854, + 0xa855, + 0xa856, + 0xa857, + 0xa858, + 0xa859, + 0xa85a, + 0xa85b, + 0xa85c, + 0xa85d, + 0xa85e, + 0xa85f, + 0xa860, + 0xa861, + 0xa862, + 0xa863, + 0xa864, + 0xa865, + 0xa867, + 0xa870, + 0xa871, + 0xa872, + 0xa873, + 0xa874, + 0xa875, + 0xa876, + 0xa877, + 0xa878, + 0xa879, + 0xa87a, + 0xa87b, + 0xa87c, + 0xa87d, + 0xa87e, + 0xa87f, + 0xa880, + 0xa881, + 0xa882, + 0xa883, + 0xa884, + 0xa885, + 0xa886, + 0xa887, + 0xa888, + 0xa889, + 0xa88a, + 0xa88b, + 0xa88c, + 0xa88d, + 0xa88e, + 0xa88f, + 0xa890, + 0xa891, + 0xa892, + 0xa893, + 0xa894, + 0xa895, + 0xa896, + 0xa898, + 0xa980, + 0xa982, + 0xa983, + 0xa984, + 0xa985, + 0xa986, + 0xa987, + 0xa988, + 0xa989, + 0xa98a, + 0xa98b, + 0xa98c, + 0xa98d, + 0xa98e, + 0xa98f, + 0xa990, + 0xa991, + 0xa992, + 0xa993, + 0xa994, + 0xa995, + 0xa996, + 0xa997, + 0xa998, + 0xa999, + 0xa99a, + 0xa99b, + 0xa99c, + 0xa99d, + 0xa99e, + 0xa99f, + 0xa9a0, + 0xa9a1, + 0xa9a2, + 0xa9a3, + 0xa9a4, + 0xa9a5, + 0xa9a6, + 0xa9a7, + 0xa9a9, + 0xa9aa, + 0xa9ae, + 0xa9bf, + 0xa9c6, + 0xa9c7, + 0xa9c8, + 0xa9c9, + 0xa9ca, + 0xa9cb, + 0xa9d4, + 0xa9d5, + 0xa9d6, + 0xa9d7, + 0xa9d8, + 0xa9d9, + 0xa9da, + 0xa9db, + 0xa9dc, + 0xa9dd, + 0xa9de, + 0xa9e0, + 0xa9e1, + 0xa9e4, + 0xa9e5, + 0xab00, + 0xab03, + 0xab04, + 0xab05, + 0xab0a, + 0xab0b, + 0xab0c, + 0xab0d, + 0xab0e, + 0xab0f, + 0xab10, + 0xab11, + 0xab12, + 0xab13, + 0xab14, + 0xab15, + 0xab16, + 0xab17, + 0xab18, + 0xab19, + 0xab21, + 0xb2c0, + 0xb2c2, + 0xb2c3, + 0xb2ca, + 0xb2cb, + 0xb2cc, + 0xb2d2, + 0xb300, + 0xb301, + 0xb304, + 0xb305, + 0xb306, + 0xb307, +}; +#endif + #endif /* A6XX_XML */ diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 8c4900444b2c..8bea8ef26f77 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -223,7 +223,7 @@ static int a6xx_gmu_start(struct a6xx_gmu *gmu) * note: downstream saves the value in poweroff and restores it here */ if (adreno_is_a7xx(adreno_gpu)) - gmu_write(gmu, REG_A6XX_GMU_GENERAL_9, 0); + gmu_write(gmu, REG_A7XX_GMU_GENERAL_9, 0); else gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0); @@ -842,6 +842,8 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) */ if (adreno_is_a740(adreno_gpu)) chipid_min = 2; + else if (adreno_is_a750(adreno_gpu)) + chipid_min = 9; else return -EINVAL; @@ -863,8 +865,8 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) } if (adreno_is_a7xx(adreno_gpu)) { - gmu_write(gmu, REG_A6XX_GMU_GENERAL_10, chipid); - gmu_write(gmu, REG_A6XX_GMU_GENERAL_8, + gmu_write(gmu, REG_A7XX_GMU_GENERAL_10, chipid); + gmu_write(gmu, REG_A7XX_GMU_GENERAL_8, (gmu->log.iova & GENMASK(31, 12)) | ((gmu->log.size / SZ_4K - 1) & GENMASK(7, 0))); } else { diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h index 5b66efafc901..9d7f93929367 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.xml.h @@ -3,28 +3,19 @@ /* Autogenerated file, DO NOT EDIT manually! -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://github.com/freedreno/envytools/ -git clone https://github.com/freedreno/envytools.git +This file was generated by the rules-ng-ng gen_header.py tool in this git repository: +http://gitlab.freedesktop.org/mesa/mesa/ +git clone https://gitlab.freedesktop.org/mesa/mesa.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2023-03-10 18:32:52) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 91929 bytes, from 2023-02-28 23:52:27) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from 2023-03-10 18:32:53) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 74995 bytes, from 2023-03-20 18:06:23) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113474 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149590 bytes, from 2023-02-14 19:37:12) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 198949 bytes, from 2023-03-20 18:06:23) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11404 bytes, from 2023-03-10 18:32:53) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 9055 bytes, from 2023-03-10 18:32:52) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2976 bytes, from 2023-03-10 18:32:52) - -Copyright (C) 2013-2023 by the following authors: -- Rob Clark <robdclark@gmail.com> (robclark) -- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) + +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11820 bytes, from Fri Jun 2 14:59:26 2023) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from Fri Jun 2 14:59:26 2023) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023) + +Copyright (C) 2013-2024 by the following authors: +- Rob Clark <robdclark@gmail.com> Rob Clark +- Ilia Mirkin <imirkin@alum.mit.edu> Ilia Mirkin Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the @@ -45,112 +36,42 @@ IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ +#ifdef __KERNEL__ +#include <linux/bug.h> +#define assert(x) BUG_ON(!(x)) +#else +#include <assert.h> +#endif + +#ifdef __cplusplus +#define __struct_cast(X) +#else +#define __struct_cast(X) (struct X) +#endif + +#define A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB 0x00800000 +#define A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB 0x40000000 + +#define A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK 0x00400000 +#define A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK 0x40000000 +#define A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK 0x40000000 +#define A6XX_GMU_OOB_DCVS_SET_MASK 0x00800000 +#define A6XX_GMU_OOB_DCVS_CHECK_MASK 0x80000000 +#define A6XX_GMU_OOB_DCVS_CLEAR_MASK 0x80000000 +#define A6XX_GMU_OOB_GPU_SET_MASK 0x00040000 +#define A6XX_GMU_OOB_GPU_CHECK_MASK 0x04000000 +#define A6XX_GMU_OOB_GPU_CLEAR_MASK 0x04000000 +#define A6XX_GMU_OOB_PERFCNTR_SET_MASK 0x00020000 +#define A6XX_GMU_OOB_PERFCNTR_CHECK_MASK 0x02000000 +#define A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK 0x02000000 -#define A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB__MASK 0x00800000 -#define A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB__SHIFT 23 -static inline uint32_t A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB(uint32_t val) -{ - return ((val) << A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB__SHIFT) & A6XX_GMU_GPU_IDLE_STATUS_BUSY_IGN_AHB__MASK; -} -#define A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB__MASK 0x40000000 -#define A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB__SHIFT 30 -static inline uint32_t A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB(uint32_t val) -{ - return ((val) << A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB__SHIFT) & A6XX_GMU_GPU_IDLE_STATUS_CX_GX_CPU_BUSY_IGN_AHB__MASK; -} -#define A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK__MASK 0x00400000 -#define A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK__SHIFT 22 -static inline uint32_t A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK(uint32_t val) -{ - return ((val) << A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK__SHIFT) & A6XX_GMU_OOB_BOOT_SLUMBER_SET_MASK__MASK; -} -#define A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK__MASK 0x40000000 -#define A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK__SHIFT 30 -static inline uint32_t A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK(uint32_t val) -{ - return ((val) << A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK__SHIFT) & A6XX_GMU_OOB_BOOT_SLUMBER_CHECK_MASK__MASK; -} -#define A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK__MASK 0x40000000 -#define A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK__SHIFT 30 -static inline uint32_t A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK(uint32_t val) -{ - return ((val) << A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK__SHIFT) & A6XX_GMU_OOB_BOOT_SLUMBER_CLEAR_MASK__MASK; -} -#define A6XX_GMU_OOB_DCVS_SET_MASK__MASK 0x00800000 -#define A6XX_GMU_OOB_DCVS_SET_MASK__SHIFT 23 -static inline uint32_t A6XX_GMU_OOB_DCVS_SET_MASK(uint32_t val) -{ - return ((val) << A6XX_GMU_OOB_DCVS_SET_MASK__SHIFT) & A6XX_GMU_OOB_DCVS_SET_MASK__MASK; -} -#define A6XX_GMU_OOB_DCVS_CHECK_MASK__MASK 0x80000000 -#define A6XX_GMU_OOB_DCVS_CHECK_MASK__SHIFT 31 -static inline uint32_t A6XX_GMU_OOB_DCVS_CHECK_MASK(uint32_t val) -{ - return ((val) << A6XX_GMU_OOB_DCVS_CHECK_MASK__SHIFT) & A6XX_GMU_OOB_DCVS_CHECK_MASK__MASK; -} -#define A6XX_GMU_OOB_DCVS_CLEAR_MASK__MASK 0x80000000 -#define A6XX_GMU_OOB_DCVS_CLEAR_MASK__SHIFT 31 -static inline uint32_t A6XX_GMU_OOB_DCVS_CLEAR_MASK(uint32_t val) -{ - return ((val) << A6XX_GMU_OOB_DCVS_CLEAR_MASK__SHIFT) & A6XX_GMU_OOB_DCVS_CLEAR_MASK__MASK; -} -#define A6XX_GMU_OOB_GPU_SET_MASK__MASK 0x00040000 -#define A6XX_GMU_OOB_GPU_SET_MASK__SHIFT 18 -static inline uint32_t A6XX_GMU_OOB_GPU_SET_MASK(uint32_t val) -{ - return ((val) << A6XX_GMU_OOB_GPU_SET_MASK__SHIFT) & A6XX_GMU_OOB_GPU_SET_MASK__MASK; -} -#define A6XX_GMU_OOB_GPU_CHECK_MASK__MASK 0x04000000 -#define A6XX_GMU_OOB_GPU_CHECK_MASK__SHIFT 26 -static inline uint32_t A6XX_GMU_OOB_GPU_CHECK_MASK(uint32_t val) -{ - return ((val) << A6XX_GMU_OOB_GPU_CHECK_MASK__SHIFT) & A6XX_GMU_OOB_GPU_CHECK_MASK__MASK; -} -#define A6XX_GMU_OOB_GPU_CLEAR_MASK__MASK 0x04000000 -#define A6XX_GMU_OOB_GPU_CLEAR_MASK__SHIFT 26 -static inline uint32_t A6XX_GMU_OOB_GPU_CLEAR_MASK(uint32_t val) -{ - return ((val) << A6XX_GMU_OOB_GPU_CLEAR_MASK__SHIFT) & A6XX_GMU_OOB_GPU_CLEAR_MASK__MASK; -} -#define A6XX_GMU_OOB_PERFCNTR_SET_MASK__MASK 0x00020000 -#define A6XX_GMU_OOB_PERFCNTR_SET_MASK__SHIFT 17 -static inline uint32_t A6XX_GMU_OOB_PERFCNTR_SET_MASK(uint32_t val) -{ - return ((val) << A6XX_GMU_OOB_PERFCNTR_SET_MASK__SHIFT) & A6XX_GMU_OOB_PERFCNTR_SET_MASK__MASK; -} -#define A6XX_GMU_OOB_PERFCNTR_CHECK_MASK__MASK 0x02000000 -#define A6XX_GMU_OOB_PERFCNTR_CHECK_MASK__SHIFT 25 -static inline uint32_t A6XX_GMU_OOB_PERFCNTR_CHECK_MASK(uint32_t val) -{ - return ((val) << A6XX_GMU_OOB_PERFCNTR_CHECK_MASK__SHIFT) & A6XX_GMU_OOB_PERFCNTR_CHECK_MASK__MASK; -} -#define A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK__MASK 0x02000000 -#define A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK__SHIFT 25 -static inline uint32_t A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK(uint32_t val) -{ - return ((val) << A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK__SHIFT) & A6XX_GMU_OOB_PERFCNTR_CLEAR_MASK__MASK; -} #define A6XX_HFI_IRQ_MSGQ_MASK 0x00000001 -#define A6XX_HFI_IRQ_DSGQ_MASK__MASK 0x00000002 -#define A6XX_HFI_IRQ_DSGQ_MASK__SHIFT 1 -static inline uint32_t A6XX_HFI_IRQ_DSGQ_MASK(uint32_t val) -{ - return ((val) << A6XX_HFI_IRQ_DSGQ_MASK__SHIFT) & A6XX_HFI_IRQ_DSGQ_MASK__MASK; -} -#define A6XX_HFI_IRQ_BLOCKED_MSG_MASK__MASK 0x00000004 -#define A6XX_HFI_IRQ_BLOCKED_MSG_MASK__SHIFT 2 -static inline uint32_t A6XX_HFI_IRQ_BLOCKED_MSG_MASK(uint32_t val) -{ - return ((val) << A6XX_HFI_IRQ_BLOCKED_MSG_MASK__SHIFT) & A6XX_HFI_IRQ_BLOCKED_MSG_MASK__MASK; -} -#define A6XX_HFI_IRQ_CM3_FAULT_MASK__MASK 0x00800000 -#define A6XX_HFI_IRQ_CM3_FAULT_MASK__SHIFT 23 -static inline uint32_t A6XX_HFI_IRQ_CM3_FAULT_MASK(uint32_t val) -{ - return ((val) << A6XX_HFI_IRQ_CM3_FAULT_MASK__SHIFT) & A6XX_HFI_IRQ_CM3_FAULT_MASK__MASK; -} +#define A6XX_HFI_IRQ_DSGQ_MASK 0x00000002 +#define A6XX_HFI_IRQ_BLOCKED_MSG_MASK 0x00000004 +#define A6XX_HFI_IRQ_CM3_FAULT_MASK 0x00800000 #define A6XX_HFI_IRQ_GMU_ERR_MASK__MASK 0x007f0000 #define A6XX_HFI_IRQ_GMU_ERR_MASK__SHIFT 16 static inline uint32_t A6XX_HFI_IRQ_GMU_ERR_MASK(uint32_t val) @@ -163,7 +84,9 @@ static inline uint32_t A6XX_HFI_IRQ_OOB_MASK(uint32_t val) { return ((val) << A6XX_HFI_IRQ_OOB_MASK__SHIFT) & A6XX_HFI_IRQ_OOB_MASK__MASK; } + #define A6XX_HFI_H2F_IRQ_MASK_BIT 0x00000001 + #define REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL 0x00000080 #define REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL 0x00000081 @@ -356,15 +279,19 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val) #define REG_A6XX_GMU_HOST2GMU_INTR_INFO_3 0x0000519e +#define REG_A6XX_GMU_GENERAL_0 0x000051c5 + #define REG_A6XX_GMU_GENERAL_1 0x000051c6 +#define REG_A6XX_GMU_GENERAL_6 0x000051cb + #define REG_A6XX_GMU_GENERAL_7 0x000051cc -#define REG_A6XX_GMU_GENERAL_8 0x000051cd +#define REG_A7XX_GMU_GENERAL_8 0x000051cd -#define REG_A6XX_GMU_GENERAL_9 0x000051ce +#define REG_A7XX_GMU_GENERAL_9 0x000051ce -#define REG_A6XX_GMU_GENERAL_10 0x000051cf +#define REG_A7XX_GMU_GENERAL_10 0x000051cf #define REG_A6XX_GMU_ISENSE_CTRL 0x0000515d @@ -489,5 +416,7 @@ static inline uint32_t A6XX_GMU_GPU_NAP_CTRL_SID(uint32_t val) #define REG_A6XX_RSCC_TCS3_DRV0_STATUS 0x0000053e +#ifdef __cplusplus +#endif #endif /* A6XX_GMU_XML */ diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index c9c55e2ea584..0674aca0f8a3 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -837,6 +837,65 @@ const struct adreno_reglist a690_hwcg[] = { {} }; +const struct adreno_reglist a702_hwcg[] = { + { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220 }, + { REG_A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000081 }, + { REG_A6XX_RBBM_CLOCK_HYST_SP0, 0x0000f3cf }, + { REG_A6XX_RBBM_CLOCK_CNTL_TP0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111 }, + { REG_A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111 }, + { REG_A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111 }, + { REG_A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111 }, + { REG_A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777 }, + { REG_A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777 }, + { REG_A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777 }, + { REG_A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777 }, + { REG_A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_RB0, 0x01202222 }, + { REG_A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220 }, + { REG_A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040f00 }, + { REG_A6XX_RBBM_CLOCK_CNTL_RAC, 0x05522022 }, + { REG_A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555 }, + { REG_A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011 }, + { REG_A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044 }, + { REG_A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222 }, + { REG_A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222 }, + { REG_A6XX_RBBM_CLOCK_MODE_GPC, 0x02222222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002 }, + { REG_A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000 }, + { REG_A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200 }, + { REG_A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004 }, + { REG_A6XX_RBBM_CLOCK_HYST_HLSQ, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222 }, + { REG_A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004 }, + { REG_A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002 }, + { REG_A6XX_RBBM_ISDB_CNT, 0x00000182 }, + { REG_A6XX_RBBM_RAC_THRESHOLD_CNT, 0x00000000 }, + { REG_A6XX_RBBM_SP_HYST_CNT, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111 }, + { REG_A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555 }, + { REG_A6XX_RBBM_CLOCK_CNTL_FCHE, 0x00000222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_FCHE, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_FCHE, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_CNTL_GLC, 0x00222222 }, + { REG_A6XX_RBBM_CLOCK_DELAY_GLC, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_GLC, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_CNTL_MHUB, 0x00000002 }, + { REG_A6XX_RBBM_CLOCK_DELAY_MHUB, 0x00000000 }, + { REG_A6XX_RBBM_CLOCK_HYST_MHUB, 0x00000000 }, + {} +}; + const struct adreno_reglist a730_hwcg[] = { { REG_A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222 }, { REG_A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022222 }, @@ -961,13 +1020,15 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) unsigned int i; u32 val, clock_cntl_on, cgc_mode; - if (!adreno_gpu->info->hwcg) + if (!(adreno_gpu->info->hwcg || adreno_is_a7xx(adreno_gpu))) return; if (adreno_is_a630(adreno_gpu)) clock_cntl_on = 0x8aa8aa02; else if (adreno_is_a610(adreno_gpu)) clock_cntl_on = 0xaaa8aa82; + else if (adreno_is_a702(adreno_gpu)) + clock_cntl_on = 0xaaaaaa82; else clock_cntl_on = 0x8aa8aa82; @@ -982,6 +1043,25 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) state ? 0x5555 : 0); } + if (!adreno_gpu->info->hwcg) { + gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 1); + gpu_write(gpu, REG_A7XX_RBBM_CGC_GLOBAL_LOAD_CMD, state ? 1 : 0); + + if (state) { + gpu_write(gpu, REG_A7XX_RBBM_CGC_P2S_TRIG_CMD, 1); + + if (gpu_poll_timeout(gpu, REG_A7XX_RBBM_CGC_P2S_STATUS, val, + val & A7XX_RBBM_CGC_P2S_STATUS_TXDONE, 1, 10)) { + dev_err(&gpu->pdev->dev, "RBBM_CGC_P2S_STATUS TXDONE Poll failed\n"); + return; + } + + gpu_write(gpu, REG_A7XX_RBBM_CLOCK_CNTL_GLOBAL, 0); + } + + return; + } + val = gpu_read(gpu, REG_A6XX_RBBM_CLOCK_CNTL); /* Don't re-program the registers if they are already correct */ @@ -989,14 +1069,14 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state) return; /* Disable SP clock before programming HWCG registers */ - if (!adreno_is_a610(adreno_gpu) && !adreno_is_a7xx(adreno_gpu)) + if (!adreno_is_a610_family(adreno_gpu) && !adreno_is_a7xx(adreno_gpu)) gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); for (i = 0; (reg = &adreno_gpu->info->hwcg[i], reg->offset); i++) gpu_write(gpu, reg->offset, state ? reg->value : 0); /* Enable SP clock */ - if (!adreno_is_a610(adreno_gpu) && !adreno_is_a7xx(adreno_gpu)) + if (!adreno_is_a610_family(adreno_gpu) && !adreno_is_a7xx(adreno_gpu)) gmu_rmw(gmu, REG_A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); gpu_write(gpu, REG_A6XX_RBBM_CLOCK_CNTL, state ? clock_cntl_on : 0); @@ -1224,7 +1304,7 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) const u32 *regs = a6xx_protect; unsigned i, count, count_max; - if (adreno_is_a650(adreno_gpu)) { + if (adreno_is_a650(adreno_gpu) || adreno_is_a702(adreno_gpu)) { regs = a650_protect; count = ARRAY_SIZE(a650_protect); count_max = 48; @@ -1239,7 +1319,9 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu) count = ARRAY_SIZE(a660_protect); count_max = 48; BUILD_BUG_ON(ARRAY_SIZE(a660_protect) > 48); - } else if (adreno_is_a730(adreno_gpu) || adreno_is_a740(adreno_gpu)) { + } else if (adreno_is_a730(adreno_gpu) || + adreno_is_a740(adreno_gpu) || + adreno_is_a750(adreno_gpu)) { regs = a730_protect; count = ARRAY_SIZE(a730_protect); count_max = 48; @@ -1292,9 +1374,8 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) gpu->ubwc_config.ubwc_mode = 1; } - /* a618 is using the hw default values */ if (adreno_is_a618(gpu)) - return; + gpu->ubwc_config.highest_bank_bit = 14; if (adreno_is_a619_holi(gpu)) gpu->ubwc_config.highest_bank_bit = 13; @@ -1320,6 +1401,12 @@ static void a6xx_calc_ubwc_config(struct adreno_gpu *gpu) gpu->ubwc_config.rgb565_predicator = 1; gpu->ubwc_config.uavflagprd_inv = 2; } + + if (adreno_is_a702(gpu)) { + gpu->ubwc_config.highest_bank_bit = 14; + gpu->ubwc_config.min_acc_len = 1; + gpu->ubwc_config.ubwc_mode = 2; + } } static void a6xx_set_ubwc_config(struct msm_gpu *gpu) @@ -1453,7 +1540,7 @@ static bool a6xx_ucode_check_version(struct a6xx_gpu *a6xx_gpu, return false; /* A7xx is safe! */ - if (adreno_is_a7xx(adreno_gpu)) + if (adreno_is_a7xx(adreno_gpu) || adreno_is_a702(adreno_gpu)) return true; /* @@ -1671,7 +1758,7 @@ static int hw_init(struct msm_gpu *gpu) a6xx_set_hwcg(gpu, true); /* VBIF/GBIF start*/ - if (adreno_is_a610(adreno_gpu) || + if (adreno_is_a610_family(adreno_gpu) || adreno_is_a640_family(adreno_gpu) || adreno_is_a650_family(adreno_gpu) || adreno_is_a7xx(adreno_gpu)) { @@ -1705,6 +1792,7 @@ static int hw_init(struct msm_gpu *gpu) } if (!(adreno_is_a650_family(adreno_gpu) || + adreno_is_a702(adreno_gpu) || adreno_is_a730(adreno_gpu))) { gmem_range_min = adreno_is_a740_family(adreno_gpu) ? SZ_16M : SZ_1M; @@ -1725,7 +1813,7 @@ static int hw_init(struct msm_gpu *gpu) if (adreno_is_a640_family(adreno_gpu) || adreno_is_a650_family(adreno_gpu)) { gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140); gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362c); - } else if (adreno_is_a610(adreno_gpu)) { + } else if (adreno_is_a610_family(adreno_gpu)) { gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_2, 0x00800060); gpu_write(gpu, REG_A6XX_CP_ROQ_THRESHOLDS_1, 0x40201b16); } else if (!adreno_is_a7xx(adreno_gpu)) { @@ -1740,13 +1828,18 @@ static int hw_init(struct msm_gpu *gpu) if (adreno_is_a610(adreno_gpu)) { gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48); gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47); + } else if (adreno_is_a702(adreno_gpu)) { + gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 64); + gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 63); } else if (!adreno_is_a7xx(adreno_gpu)) gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 128); /* Setting the primFifo thresholds default values, * and vccCacheSkipDis=1 bit (0x200) for A640 and newer */ - if (adreno_is_a690(adreno_gpu)) + if (adreno_is_a702(adreno_gpu)) + gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x0000c000); + else if (adreno_is_a690(adreno_gpu)) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00800200); else if (adreno_is_a650(adreno_gpu) || adreno_is_a660(adreno_gpu)) gpu_write(gpu, REG_A6XX_PC_DBG_ECO_CNTL, 0x00300200); @@ -1786,7 +1879,7 @@ static int hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x4fffff); else if (adreno_is_a619(adreno_gpu)) gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3fffff); - else if (adreno_is_a610(adreno_gpu)) + else if (adreno_is_a610(adreno_gpu) || adreno_is_a702(adreno_gpu)) gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x3ffff); else gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0x1fffff); @@ -1822,6 +1915,9 @@ static int hw_init(struct msm_gpu *gpu) else gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, 0x1); gpu_write(gpu, REG_A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, 0x0); + } else if (adreno_is_a702(adreno_gpu)) { + /* Something to do with the HLSQ cluster */ + gpu_write(gpu, REG_A6XX_CP_CHICKEN_DBG, BIT(24)); } if (adreno_is_a690(adreno_gpu)) @@ -2043,13 +2139,19 @@ static void a6xx_recover(struct msm_gpu *gpu) static const char *a6xx_uche_fault_block(struct msm_gpu *gpu, u32 mid) { + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); static const char *uche_clients[7] = { "VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ", }; u32 val; - if (mid < 1 || mid > 3) - return "UNKNOWN"; + if (adreno_is_a7xx(adreno_gpu)) { + if (mid != 1 && mid != 2 && mid != 3 && mid != 8) + return "UNKNOWN"; + } else { + if (mid < 1 || mid > 3) + return "UNKNOWN"; + } /* * The source of the data depends on the mid ID read from FSYNR1. @@ -2057,26 +2159,95 @@ static const char *a6xx_uche_fault_block(struct msm_gpu *gpu, u32 mid) */ val = gpu_read(gpu, REG_A6XX_UCHE_CLIENT_PF); - /* mid = 3 is most precise and refers to only one block per client */ - if (mid == 3) - return uche_clients[val & 7]; + if (adreno_is_a7xx(adreno_gpu)) { + /* Bit 3 for mid=3 indicates BR or BV */ + static const char *uche_clients_a7xx[16] = { + "BR_VFD", "BR_SP", "BR_VSC", "BR_VPC", + "BR_HLSQ", "BR_PC", "BR_LRZ", "BR_TP", + "BV_VFD", "BV_SP", "BV_VSC", "BV_VPC", + "BV_HLSQ", "BV_PC", "BV_LRZ", "BV_TP", + }; + + /* LPAC has the same clients as BR and BV, but because it is + * compute-only some of them do not exist and there are holes + * in the array. + */ + static const char *uche_clients_lpac_a7xx[8] = { + "-", "LPAC_SP", "-", "-", + "LPAC_HLSQ", "-", "-", "LPAC_TP", + }; + + val &= GENMASK(6, 0); + + /* mid=3 refers to BR or BV */ + if (mid == 3) { + if (val < ARRAY_SIZE(uche_clients_a7xx)) + return uche_clients_a7xx[val]; + else + return "UCHE"; + } + + /* mid=8 refers to LPAC */ + if (mid == 8) { + if (val < ARRAY_SIZE(uche_clients_lpac_a7xx)) + return uche_clients_lpac_a7xx[val]; + else + return "UCHE_LPAC"; + } + + /* mid=2 is a catchall for everything else in LPAC */ + if (mid == 2) + return "UCHE_LPAC"; + + /* mid=1 is a catchall for everything else in BR/BV */ + return "UCHE"; + } else if (adreno_is_a660_family(adreno_gpu)) { + static const char *uche_clients_a660[8] = { + "VFD", "SP", "VSC", "VPC", "HLSQ", "PC", "LRZ", "TP", + }; - /* For mid=2 the source is TP or VFD except when the client id is 0 */ - if (mid == 2) - return ((val & 7) == 0) ? "TP" : "TP|VFD"; + static const char *uche_clients_a660_not[8] = { + "not VFD", "not SP", "not VSC", "not VPC", + "not HLSQ", "not PC", "not LRZ", "not TP", + }; - /* For mid=1 just return "UCHE" as a catchall for everything else */ - return "UCHE"; + val &= GENMASK(6, 0); + + if (mid == 3 && val < ARRAY_SIZE(uche_clients_a660)) + return uche_clients_a660[val]; + + if (mid == 1 && val < ARRAY_SIZE(uche_clients_a660_not)) + return uche_clients_a660_not[val]; + + return "UCHE"; + } else { + /* mid = 3 is most precise and refers to only one block per client */ + if (mid == 3) + return uche_clients[val & 7]; + + /* For mid=2 the source is TP or VFD except when the client id is 0 */ + if (mid == 2) + return ((val & 7) == 0) ? "TP" : "TP|VFD"; + + /* For mid=1 just return "UCHE" as a catchall for everything else */ + return "UCHE"; + } } static const char *a6xx_fault_block(struct msm_gpu *gpu, u32 id) { + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + if (id == 0) return "CP"; else if (id == 4) return "CCU"; else if (id == 6) return "CDP Prefetch"; + else if (id == 7) + return "GMU"; + else if (id == 5 && adreno_is_a7xx(adreno_gpu)) + return "Flag cache"; return a6xx_uche_fault_block(gpu, id); } @@ -2427,7 +2598,7 @@ static int a6xx_gmu_pm_resume(struct msm_gpu *gpu) msm_devfreq_resume(gpu); - adreno_is_a7xx(adreno_gpu) ? a7xx_llc_activate : a6xx_llc_activate(a6xx_gpu); + adreno_is_a7xx(adreno_gpu) ? a7xx_llc_activate(a6xx_gpu) : a6xx_llc_activate(a6xx_gpu); return ret; } @@ -2880,7 +3051,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) /* gpu->info only gets assigned in adreno_gpu_init() */ is_a7xx = config->info->family == ADRENO_7XX_GEN1 || - config->info->family == ADRENO_7XX_GEN2; + config->info->family == ADRENO_7XX_GEN2 || + config->info->family == ADRENO_7XX_GEN3; a6xx_llc_slices_init(pdev, a6xx_gpu, is_a7xx); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c index 91a564a24dbe..1f5245fc2cdc 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c @@ -8,6 +8,17 @@ #include "a6xx_gpu_state.h" #include "a6xx_gmu.xml.h" +/* Ignore diagnostics about register tables that we aren't using yet. We don't + * want to modify these headers too much from their original source. + */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wunused-variable" + +#include "adreno_gen7_0_0_snapshot.h" +#include "adreno_gen7_2_0_snapshot.h" + +#pragma GCC diagnostic pop + struct a6xx_gpu_state_obj { const void *handle; u32 *data; @@ -322,12 +333,98 @@ static void a6xx_get_cx_debugbus_block(void __iomem *cxdbg, ptr += cx_debugbus_read(cxdbg, block->id, i, ptr); } +static void a6xx_get_debugbus_blocks(struct msm_gpu *gpu, + struct a6xx_gpu_state *a6xx_state) +{ + int nr_debugbus_blocks = ARRAY_SIZE(a6xx_debugbus_blocks) + + (a6xx_has_gbif(to_adreno_gpu(gpu)) ? 1 : 0); + + if (adreno_is_a650_family(to_adreno_gpu(gpu))) + nr_debugbus_blocks += ARRAY_SIZE(a650_debugbus_blocks); + + a6xx_state->debugbus = state_kcalloc(a6xx_state, nr_debugbus_blocks, + sizeof(*a6xx_state->debugbus)); + + if (a6xx_state->debugbus) { + int i; + + for (i = 0; i < ARRAY_SIZE(a6xx_debugbus_blocks); i++) + a6xx_get_debugbus_block(gpu, + a6xx_state, + &a6xx_debugbus_blocks[i], + &a6xx_state->debugbus[i]); + + a6xx_state->nr_debugbus = ARRAY_SIZE(a6xx_debugbus_blocks); + + /* + * GBIF has same debugbus as of other GPU blocks, fall back to + * default path if GPU uses GBIF, also GBIF uses exactly same + * ID as of VBIF. + */ + if (a6xx_has_gbif(to_adreno_gpu(gpu))) { + a6xx_get_debugbus_block(gpu, a6xx_state, + &a6xx_gbif_debugbus_block, + &a6xx_state->debugbus[i]); + + a6xx_state->nr_debugbus += 1; + } + + + if (adreno_is_a650_family(to_adreno_gpu(gpu))) { + for (i = 0; i < ARRAY_SIZE(a650_debugbus_blocks); i++) + a6xx_get_debugbus_block(gpu, + a6xx_state, + &a650_debugbus_blocks[i], + &a6xx_state->debugbus[i]); + } + } +} + +static void a7xx_get_debugbus_blocks(struct msm_gpu *gpu, + struct a6xx_gpu_state *a6xx_state) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + int debugbus_blocks_count, total_debugbus_blocks; + const u32 *debugbus_blocks; + int i; + + if (adreno_is_a730(adreno_gpu)) { + debugbus_blocks = gen7_0_0_debugbus_blocks; + debugbus_blocks_count = ARRAY_SIZE(gen7_0_0_debugbus_blocks); + } else { + BUG_ON(!adreno_is_a740_family(adreno_gpu)); + debugbus_blocks = gen7_2_0_debugbus_blocks; + debugbus_blocks_count = ARRAY_SIZE(gen7_2_0_debugbus_blocks); + } + + total_debugbus_blocks = debugbus_blocks_count + + ARRAY_SIZE(a7xx_gbif_debugbus_blocks); + + a6xx_state->debugbus = state_kcalloc(a6xx_state, total_debugbus_blocks, + sizeof(*a6xx_state->debugbus)); + + if (a6xx_state->debugbus) { + for (i = 0; i < debugbus_blocks_count; i++) { + a6xx_get_debugbus_block(gpu, + a6xx_state, &a7xx_debugbus_blocks[debugbus_blocks[i]], + &a6xx_state->debugbus[i]); + } + + for (i = 0; i < ARRAY_SIZE(a7xx_gbif_debugbus_blocks); i++) { + a6xx_get_debugbus_block(gpu, + a6xx_state, &a7xx_gbif_debugbus_blocks[i], + &a6xx_state->debugbus[i + debugbus_blocks_count]); + } + } + +} + static void a6xx_get_debugbus(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state) { + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct resource *res; void __iomem *cxdbg = NULL; - int nr_debugbus_blocks; /* Set up the GX debug bus */ @@ -382,51 +479,14 @@ static void a6xx_get_debugbus(struct msm_gpu *gpu, cxdbg_write(cxdbg, REG_A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3, 0); } - nr_debugbus_blocks = ARRAY_SIZE(a6xx_debugbus_blocks) + - (a6xx_has_gbif(to_adreno_gpu(gpu)) ? 1 : 0); - - if (adreno_is_a650_family(to_adreno_gpu(gpu))) - nr_debugbus_blocks += ARRAY_SIZE(a650_debugbus_blocks); - - a6xx_state->debugbus = state_kcalloc(a6xx_state, nr_debugbus_blocks, - sizeof(*a6xx_state->debugbus)); - - if (a6xx_state->debugbus) { - int i; - - for (i = 0; i < ARRAY_SIZE(a6xx_debugbus_blocks); i++) - a6xx_get_debugbus_block(gpu, - a6xx_state, - &a6xx_debugbus_blocks[i], - &a6xx_state->debugbus[i]); - - a6xx_state->nr_debugbus = ARRAY_SIZE(a6xx_debugbus_blocks); - - /* - * GBIF has same debugbus as of other GPU blocks, fall back to - * default path if GPU uses GBIF, also GBIF uses exactly same - * ID as of VBIF. - */ - if (a6xx_has_gbif(to_adreno_gpu(gpu))) { - a6xx_get_debugbus_block(gpu, a6xx_state, - &a6xx_gbif_debugbus_block, - &a6xx_state->debugbus[i]); - - a6xx_state->nr_debugbus += 1; - } - - - if (adreno_is_a650_family(to_adreno_gpu(gpu))) { - for (i = 0; i < ARRAY_SIZE(a650_debugbus_blocks); i++) - a6xx_get_debugbus_block(gpu, - a6xx_state, - &a650_debugbus_blocks[i], - &a6xx_state->debugbus[i]); - } + if (adreno_is_a7xx(adreno_gpu)) { + a7xx_get_debugbus_blocks(gpu, a6xx_state); + } else { + a6xx_get_debugbus_blocks(gpu, a6xx_state); } /* Dump the VBIF debugbus on applicable targets */ - if (!a6xx_has_gbif(to_adreno_gpu(gpu))) { + if (!a6xx_has_gbif(adreno_gpu)) { a6xx_state->vbif_debugbus = state_kcalloc(a6xx_state, 1, sizeof(*a6xx_state->vbif_debugbus)); @@ -437,22 +497,34 @@ static void a6xx_get_debugbus(struct msm_gpu *gpu, } if (cxdbg) { + unsigned nr_cx_debugbus_blocks; + const struct a6xx_debugbus_block *cx_debugbus_blocks; + + if (adreno_is_a7xx(adreno_gpu)) { + BUG_ON(!(adreno_is_a730(adreno_gpu) || adreno_is_a740_family(adreno_gpu))); + cx_debugbus_blocks = a7xx_cx_debugbus_blocks; + nr_cx_debugbus_blocks = ARRAY_SIZE(a7xx_cx_debugbus_blocks); + } else { + cx_debugbus_blocks = a6xx_cx_debugbus_blocks; + nr_cx_debugbus_blocks = ARRAY_SIZE(a6xx_cx_debugbus_blocks); + } + a6xx_state->cx_debugbus = state_kcalloc(a6xx_state, - ARRAY_SIZE(a6xx_cx_debugbus_blocks), + nr_cx_debugbus_blocks, sizeof(*a6xx_state->cx_debugbus)); if (a6xx_state->cx_debugbus) { int i; - for (i = 0; i < ARRAY_SIZE(a6xx_cx_debugbus_blocks); i++) + for (i = 0; i < nr_cx_debugbus_blocks; i++) a6xx_get_cx_debugbus_block(cxdbg, a6xx_state, - &a6xx_cx_debugbus_blocks[i], + &cx_debugbus_blocks[i], &a6xx_state->cx_debugbus[i]); a6xx_state->nr_cx_debugbus = - ARRAY_SIZE(a6xx_cx_debugbus_blocks); + nr_cx_debugbus_blocks; } iounmap(cxdbg); @@ -508,6 +580,48 @@ static void a6xx_get_dbgahb_cluster(struct msm_gpu *gpu, datasize); } +static void a7xx_get_dbgahb_cluster(struct msm_gpu *gpu, + struct a6xx_gpu_state *a6xx_state, + const struct gen7_sptp_cluster_registers *dbgahb, + struct a6xx_gpu_state_obj *obj, + struct a6xx_crashdumper *dumper) +{ + u64 *in = dumper->ptr; + u64 out = dumper->iova + A6XX_CD_DATA_OFFSET; + size_t datasize; + int i, regcount = 0; + + in += CRASHDUMP_WRITE(in, REG_A7XX_SP_READ_SEL, + A7XX_SP_READ_SEL_LOCATION(dbgahb->location_id) | + A7XX_SP_READ_SEL_PIPE(dbgahb->pipe_id) | + A7XX_SP_READ_SEL_STATETYPE(dbgahb->statetype)); + + for (i = 0; dbgahb->regs[i] != UINT_MAX; i += 2) { + int count = RANGE(dbgahb->regs, i); + u32 offset = REG_A7XX_SP_AHB_READ_APERTURE + + dbgahb->regs[i] - dbgahb->regbase; + + in += CRASHDUMP_READ(in, offset, count, out); + + out += count * sizeof(u32); + regcount += count; + } + + CRASHDUMP_FINI(in); + + datasize = regcount * sizeof(u32); + + if (WARN_ON(datasize > A6XX_CD_DATA_SIZE)) + return; + + if (a6xx_crashdumper_run(gpu, dumper)) + return; + + obj->handle = dbgahb; + obj->data = state_kmemdup(a6xx_state, dumper->ptr + A6XX_CD_DATA_OFFSET, + datasize); +} + static void a6xx_get_dbgahb_clusters(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, struct a6xx_crashdumper *dumper) @@ -529,6 +643,39 @@ static void a6xx_get_dbgahb_clusters(struct msm_gpu *gpu, &a6xx_state->dbgahb_clusters[i], dumper); } +static void a7xx_get_dbgahb_clusters(struct msm_gpu *gpu, + struct a6xx_gpu_state *a6xx_state, + struct a6xx_crashdumper *dumper) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + int i; + const struct gen7_sptp_cluster_registers *dbgahb_clusters; + unsigned dbgahb_clusters_size; + + if (adreno_is_a730(adreno_gpu)) { + dbgahb_clusters = gen7_0_0_sptp_clusters; + dbgahb_clusters_size = ARRAY_SIZE(gen7_0_0_sptp_clusters); + } else { + BUG_ON(!adreno_is_a740_family(adreno_gpu)); + dbgahb_clusters = gen7_2_0_sptp_clusters; + dbgahb_clusters_size = ARRAY_SIZE(gen7_2_0_sptp_clusters); + } + + a6xx_state->dbgahb_clusters = state_kcalloc(a6xx_state, + dbgahb_clusters_size, + sizeof(*a6xx_state->dbgahb_clusters)); + + if (!a6xx_state->dbgahb_clusters) + return; + + a6xx_state->nr_dbgahb_clusters = dbgahb_clusters_size; + + for (i = 0; i < dbgahb_clusters_size; i++) + a7xx_get_dbgahb_cluster(gpu, a6xx_state, + &dbgahb_clusters[i], + &a6xx_state->dbgahb_clusters[i], dumper); +} + /* Read a data cluster from the CP aperture with the crashdumper */ static void a6xx_get_cluster(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, @@ -590,6 +737,51 @@ static void a6xx_get_cluster(struct msm_gpu *gpu, datasize); } +static void a7xx_get_cluster(struct msm_gpu *gpu, + struct a6xx_gpu_state *a6xx_state, + const struct gen7_cluster_registers *cluster, + struct a6xx_gpu_state_obj *obj, + struct a6xx_crashdumper *dumper) +{ + u64 *in = dumper->ptr; + u64 out = dumper->iova + A6XX_CD_DATA_OFFSET; + size_t datasize; + int i, regcount = 0; + + /* Some clusters need a selector register to be programmed too */ + if (cluster->sel) + in += CRASHDUMP_WRITE(in, cluster->sel->cd_reg, cluster->sel->val); + + in += CRASHDUMP_WRITE(in, REG_A7XX_CP_APERTURE_CNTL_CD, + A7XX_CP_APERTURE_CNTL_CD_PIPE(cluster->pipe_id) | + A7XX_CP_APERTURE_CNTL_CD_CLUSTER(cluster->cluster_id) | + A7XX_CP_APERTURE_CNTL_CD_CONTEXT(cluster->context_id)); + + for (i = 0; cluster->regs[i] != UINT_MAX; i += 2) { + int count = RANGE(cluster->regs, i); + + in += CRASHDUMP_READ(in, cluster->regs[i], + count, out); + + out += count * sizeof(u32); + regcount += count; + } + + CRASHDUMP_FINI(in); + + datasize = regcount * sizeof(u32); + + if (WARN_ON(datasize > A6XX_CD_DATA_SIZE)) + return; + + if (a6xx_crashdumper_run(gpu, dumper)) + return; + + obj->handle = cluster; + obj->data = state_kmemdup(a6xx_state, dumper->ptr + A6XX_CD_DATA_OFFSET, + datasize); +} + static void a6xx_get_clusters(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, struct a6xx_crashdumper *dumper) @@ -609,6 +801,37 @@ static void a6xx_get_clusters(struct msm_gpu *gpu, &a6xx_state->clusters[i], dumper); } +static void a7xx_get_clusters(struct msm_gpu *gpu, + struct a6xx_gpu_state *a6xx_state, + struct a6xx_crashdumper *dumper) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + int i; + const struct gen7_cluster_registers *clusters; + unsigned clusters_size; + + if (adreno_is_a730(adreno_gpu)) { + clusters = gen7_0_0_clusters; + clusters_size = ARRAY_SIZE(gen7_0_0_clusters); + } else { + BUG_ON(!adreno_is_a740_family(adreno_gpu)); + clusters = gen7_2_0_clusters; + clusters_size = ARRAY_SIZE(gen7_2_0_clusters); + } + + a6xx_state->clusters = state_kcalloc(a6xx_state, + clusters_size, sizeof(*a6xx_state->clusters)); + + if (!a6xx_state->clusters) + return; + + a6xx_state->nr_clusters = clusters_size; + + for (i = 0; i < clusters_size; i++) + a7xx_get_cluster(gpu, a6xx_state, &clusters[i], + &a6xx_state->clusters[i], dumper); +} + /* Read a shader / debug block from the HLSQ aperture with the crashdumper */ static void a6xx_get_shader_block(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, @@ -617,6 +840,7 @@ static void a6xx_get_shader_block(struct msm_gpu *gpu, struct a6xx_crashdumper *dumper) { u64 *in = dumper->ptr; + u64 out = dumper->iova + A6XX_CD_DATA_OFFSET; size_t datasize = block->size * A6XX_NUM_SHADER_BANKS * sizeof(u32); int i; @@ -629,6 +853,8 @@ static void a6xx_get_shader_block(struct msm_gpu *gpu, in += CRASHDUMP_READ(in, REG_A6XX_HLSQ_DBG_AHB_READ_APERTURE, block->size, dumper->iova + A6XX_CD_DATA_OFFSET); + + out += block->size * sizeof(u32); } CRASHDUMP_FINI(in); @@ -641,6 +867,56 @@ static void a6xx_get_shader_block(struct msm_gpu *gpu, datasize); } +static void a7xx_get_shader_block(struct msm_gpu *gpu, + struct a6xx_gpu_state *a6xx_state, + const struct gen7_shader_block *block, + struct a6xx_gpu_state_obj *obj, + struct a6xx_crashdumper *dumper) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + u64 *in = dumper->ptr; + u64 out = dumper->iova + A6XX_CD_DATA_OFFSET; + size_t datasize = block->size * block->num_sps * block->num_usptps * sizeof(u32); + int i, j; + + if (WARN_ON(datasize > A6XX_CD_DATA_SIZE)) + return; + + if (adreno_is_a730(adreno_gpu)) { + gpu_rmw(gpu, REG_A7XX_SP_DBG_CNTL, GENMASK(1, 0), 3); + } + + for (i = 0; i < block->num_sps; i++) { + for (j = 0; j < block->num_usptps; j++) { + in += CRASHDUMP_WRITE(in, REG_A7XX_SP_READ_SEL, + A7XX_SP_READ_SEL_LOCATION(block->location) | + A7XX_SP_READ_SEL_PIPE(block->pipeid) | + A7XX_SP_READ_SEL_STATETYPE(block->statetype) | + A7XX_SP_READ_SEL_USPTP(j) | + A7XX_SP_READ_SEL_SPTP(i)); + + in += CRASHDUMP_READ(in, REG_A7XX_SP_AHB_READ_APERTURE, + block->size, out); + + out += block->size * sizeof(u32); + } + } + + CRASHDUMP_FINI(in); + + if (a6xx_crashdumper_run(gpu, dumper)) + goto out; + + obj->handle = block; + obj->data = state_kmemdup(a6xx_state, dumper->ptr + A6XX_CD_DATA_OFFSET, + datasize); + +out: + if (adreno_is_a730(adreno_gpu)) { + gpu_rmw(gpu, REG_A7XX_SP_DBG_CNTL, GENMASK(1, 0), 0); + } +} + static void a6xx_get_shaders(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, struct a6xx_crashdumper *dumper) @@ -660,6 +936,37 @@ static void a6xx_get_shaders(struct msm_gpu *gpu, &a6xx_state->shaders[i], dumper); } +static void a7xx_get_shaders(struct msm_gpu *gpu, + struct a6xx_gpu_state *a6xx_state, + struct a6xx_crashdumper *dumper) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + const struct gen7_shader_block *shader_blocks; + unsigned num_shader_blocks; + int i; + + if (adreno_is_a730(adreno_gpu)) { + shader_blocks = gen7_0_0_shader_blocks; + num_shader_blocks = ARRAY_SIZE(gen7_0_0_shader_blocks); + } else { + BUG_ON(!adreno_is_a740_family(adreno_gpu)); + shader_blocks = gen7_2_0_shader_blocks; + num_shader_blocks = ARRAY_SIZE(gen7_2_0_shader_blocks); + } + + a6xx_state->shaders = state_kcalloc(a6xx_state, + num_shader_blocks, sizeof(*a6xx_state->shaders)); + + if (!a6xx_state->shaders) + return; + + a6xx_state->nr_shaders = num_shader_blocks; + + for (i = 0; i < num_shader_blocks; i++) + a7xx_get_shader_block(gpu, a6xx_state, &shader_blocks[i], + &a6xx_state->shaders[i], dumper); +} + /* Read registers from behind the HLSQ aperture with the crashdumper */ static void a6xx_get_crashdumper_hlsq_registers(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, @@ -741,6 +1048,44 @@ static void a6xx_get_crashdumper_registers(struct msm_gpu *gpu, regcount * sizeof(u32)); } +static void a7xx_get_crashdumper_registers(struct msm_gpu *gpu, + struct a6xx_gpu_state *a6xx_state, + const struct gen7_reg_list *regs, + struct a6xx_gpu_state_obj *obj, + struct a6xx_crashdumper *dumper) + +{ + u64 *in = dumper->ptr; + u64 out = dumper->iova + A6XX_CD_DATA_OFFSET; + int i, regcount = 0; + + /* Some blocks might need to program a selector register first */ + if (regs->sel) + in += CRASHDUMP_WRITE(in, regs->sel->cd_reg, regs->sel->val); + + for (i = 0; regs->regs[i] != UINT_MAX; i += 2) { + u32 count = RANGE(regs->regs, i); + + in += CRASHDUMP_READ(in, regs->regs[i], count, out); + + out += count * sizeof(u32); + regcount += count; + } + + CRASHDUMP_FINI(in); + + if (WARN_ON((regcount * sizeof(u32)) > A6XX_CD_DATA_SIZE)) + return; + + if (a6xx_crashdumper_run(gpu, dumper)) + return; + + obj->handle = regs->regs; + obj->data = state_kmemdup(a6xx_state, dumper->ptr + A6XX_CD_DATA_OFFSET, + regcount * sizeof(u32)); +} + + /* Read a block of registers via AHB */ static void a6xx_get_ahb_gpu_registers(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, @@ -772,6 +1117,41 @@ static void a6xx_get_ahb_gpu_registers(struct msm_gpu *gpu, } } +static void a7xx_get_ahb_gpu_registers(struct msm_gpu *gpu, + struct a6xx_gpu_state *a6xx_state, + const u32 *regs, + struct a6xx_gpu_state_obj *obj) +{ + int i, regcount = 0, index = 0; + + for (i = 0; regs[i] != UINT_MAX; i += 2) + regcount += RANGE(regs, i); + + obj->handle = (const void *) regs; + obj->data = state_kcalloc(a6xx_state, regcount, sizeof(u32)); + if (!obj->data) + return; + + for (i = 0; regs[i] != UINT_MAX; i += 2) { + u32 count = RANGE(regs, i); + int j; + + for (j = 0; j < count; j++) + obj->data[index++] = gpu_read(gpu, regs[i] + j); + } +} + +static void a7xx_get_ahb_gpu_reglist(struct msm_gpu *gpu, + struct a6xx_gpu_state *a6xx_state, + const struct gen7_reg_list *regs, + struct a6xx_gpu_state_obj *obj) +{ + if (regs->sel) + gpu_write(gpu, regs->sel->host_reg, regs->sel->val); + + a7xx_get_ahb_gpu_registers(gpu, a6xx_state, regs->regs, obj); +} + /* Read a block of GMU registers */ static void _a6xx_get_gmu_registers(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state, @@ -902,20 +1282,11 @@ static void a6xx_get_registers(struct msm_gpu *gpu, a6xx_state->nr_registers = count; - if (adreno_is_a7xx(adreno_gpu)) - a6xx_get_ahb_gpu_registers(gpu, - a6xx_state, &a7xx_ahb_reglist, - &a6xx_state->registers[index++]); - else - a6xx_get_ahb_gpu_registers(gpu, - a6xx_state, &a6xx_ahb_reglist, - &a6xx_state->registers[index++]); + a6xx_get_ahb_gpu_registers(gpu, + a6xx_state, &a6xx_ahb_reglist, + &a6xx_state->registers[index++]); - if (adreno_is_a7xx(adreno_gpu)) - a6xx_get_ahb_gpu_registers(gpu, - a6xx_state, &a7xx_gbif_reglist, - &a6xx_state->registers[index++]); - else if (a6xx_has_gbif(adreno_gpu)) + if (a6xx_has_gbif(adreno_gpu)) a6xx_get_ahb_gpu_registers(gpu, a6xx_state, &a6xx_gbif_reglist, &a6xx_state->registers[index++]); @@ -951,6 +1322,80 @@ static void a6xx_get_registers(struct msm_gpu *gpu, dumper); } +#define A7XX_PRE_CRASHDUMPER_SIZE 1 +#define A7XX_POST_CRASHDUMPER_SIZE 1 +static void a7xx_get_registers(struct msm_gpu *gpu, + struct a6xx_gpu_state *a6xx_state, + struct a6xx_crashdumper *dumper) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + int i, count; + int index = 0; + const u32 *pre_crashdumper_regs; + const struct gen7_reg_list *reglist; + + if (adreno_is_a730(adreno_gpu)) { + reglist = gen7_0_0_reg_list; + pre_crashdumper_regs = gen7_0_0_pre_crashdumper_gpu_registers; + } else { + BUG_ON(!adreno_is_a740_family(adreno_gpu)); + reglist = gen7_2_0_reg_list; + pre_crashdumper_regs = gen7_0_0_pre_crashdumper_gpu_registers; + } + + count = A7XX_PRE_CRASHDUMPER_SIZE + A7XX_POST_CRASHDUMPER_SIZE; + + /* The downstream reglist contains registers in other memory regions + * (cx_misc/cx_mem and cx_dbgc) and we need to plumb through their + * offsets and map them to read them on the CPU. For now only read the + * first region which is the main one. + */ + if (dumper) { + for (i = 0; reglist[i].regs; i++) + count++; + } else { + count++; + } + + a6xx_state->registers = state_kcalloc(a6xx_state, + count, sizeof(*a6xx_state->registers)); + + if (!a6xx_state->registers) + return; + + a6xx_state->nr_registers = count; + + a7xx_get_ahb_gpu_registers(gpu, a6xx_state, pre_crashdumper_regs, + &a6xx_state->registers[index++]); + + if (!dumper) { + a7xx_get_ahb_gpu_reglist(gpu, + a6xx_state, ®list[0], + &a6xx_state->registers[index++]); + return; + } + + for (i = 0; reglist[i].regs; i++) + a7xx_get_crashdumper_registers(gpu, + a6xx_state, ®list[i], + &a6xx_state->registers[index++], + dumper); +} + +static void a7xx_get_post_crashdumper_registers(struct msm_gpu *gpu, + struct a6xx_gpu_state *a6xx_state) +{ + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); + const u32 *regs; + + BUG_ON(!(adreno_is_a730(adreno_gpu) || adreno_is_a740_family(adreno_gpu))); + regs = gen7_0_0_post_crashdumper_registers; + + a7xx_get_ahb_gpu_registers(gpu, + a6xx_state, regs, + &a6xx_state->registers[a6xx_state->nr_registers - 1]); +} + static u32 a6xx_get_cp_roq_size(struct msm_gpu *gpu) { /* The value at [16:31] is in 4dword units. Convert it to dwords */ @@ -1045,8 +1490,10 @@ static void a6xx_get_indexed_registers(struct msm_gpu *gpu, static void a7xx_get_indexed_registers(struct msm_gpu *gpu, struct a6xx_gpu_state *a6xx_state) { + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); int i, indexed_count, mempool_count; + BUG_ON(!(adreno_is_a730(adreno_gpu) || adreno_is_a740_family(adreno_gpu))); indexed_count = ARRAY_SIZE(a7xx_indexed_reglist); mempool_count = ARRAY_SIZE(a7xx_cp_bv_mempool_indexed); @@ -1068,8 +1515,8 @@ static void a7xx_get_indexed_registers(struct msm_gpu *gpu, /* Get the contents of the CP_BV mempool */ for (i = 0; i < mempool_count; i++) - a6xx_get_indexed_regs(gpu, a6xx_state, a7xx_cp_bv_mempool_indexed, - &a6xx_state->indexed_regs[indexed_count - 1 + i]); + a6xx_get_indexed_regs(gpu, a6xx_state, &a7xx_cp_bv_mempool_indexed[i], + &a6xx_state->indexed_regs[indexed_count + i]); gpu_rmw(gpu, REG_A6XX_CP_CHICKEN_DBG, BIT(2), 0); gpu_rmw(gpu, REG_A7XX_CP_BV_CHICKEN_DBG, BIT(2), 0); @@ -1109,13 +1556,10 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu) return &a6xx_state->base; /* Get the banks of indexed registers */ - if (adreno_is_a7xx(adreno_gpu)) { + if (adreno_is_a7xx(adreno_gpu)) a7xx_get_indexed_registers(gpu, a6xx_state); - /* Further codeflow is untested on A7xx. */ - return &a6xx_state->base; - } - - a6xx_get_indexed_registers(gpu, a6xx_state); + else + a6xx_get_indexed_registers(gpu, a6xx_state); /* * Try to initialize the crashdumper, if we are not dumping state @@ -1128,14 +1572,28 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu) dumper = &_dumper; } - a6xx_get_registers(gpu, a6xx_state, dumper); + if (adreno_is_a7xx(adreno_gpu)) { + a7xx_get_registers(gpu, a6xx_state, dumper); - if (dumper) { - a6xx_get_shaders(gpu, a6xx_state, dumper); - a6xx_get_clusters(gpu, a6xx_state, dumper); - a6xx_get_dbgahb_clusters(gpu, a6xx_state, dumper); + if (dumper) { + a7xx_get_shaders(gpu, a6xx_state, dumper); + a7xx_get_clusters(gpu, a6xx_state, dumper); + a7xx_get_dbgahb_clusters(gpu, a6xx_state, dumper); + + msm_gem_kernel_put(dumper->bo, gpu->aspace); + } + + a7xx_get_post_crashdumper_registers(gpu, a6xx_state); + } else { + a6xx_get_registers(gpu, a6xx_state, dumper); - msm_gem_kernel_put(dumper->bo, gpu->aspace); + if (dumper) { + a6xx_get_shaders(gpu, a6xx_state, dumper); + a6xx_get_clusters(gpu, a6xx_state, dumper); + a6xx_get_dbgahb_clusters(gpu, a6xx_state, dumper); + + msm_gem_kernel_put(dumper->bo, gpu->aspace); + } } if (snapshot_debugbus) @@ -1203,6 +1661,35 @@ static void a6xx_show_registers(const u32 *registers, u32 *data, size_t count, } } +static void a7xx_show_registers_indented(const u32 *registers, u32 *data, + struct drm_printer *p, unsigned indent) +{ + int i, index = 0; + + for (i = 0; registers[i] != UINT_MAX; i += 2) { + u32 count = RANGE(registers, i); + u32 offset = registers[i]; + int j; + + for (j = 0; j < count; index++, offset++, j++) { + int k; + + if (data[index] == 0xdeafbead) + continue; + + for (k = 0; k < indent; k++) + drm_printf(p, " "); + drm_printf(p, "- { offset: 0x%06x, value: 0x%08x }\n", + offset << 2, data[index]); + } + } +} + +static void a7xx_show_registers(const u32 *registers, u32 *data, struct drm_printer *p) +{ + a7xx_show_registers_indented(registers, data, p, 1); +} + static void print_ascii85(struct drm_printer *p, size_t len, u32 *data) { char out[ASCII85_BUFSZ]; @@ -1258,6 +1745,36 @@ static void a6xx_show_shader(struct a6xx_gpu_state_obj *obj, } } +static void a7xx_show_shader(struct a6xx_gpu_state_obj *obj, + struct drm_printer *p) +{ + const struct gen7_shader_block *block = obj->handle; + int i, j; + u32 *data = obj->data; + + if (!obj->handle) + return; + + print_name(p, " - type: ", a7xx_statetype_names[block->statetype]); + print_name(p, " - pipe: ", a7xx_pipe_names[block->pipeid]); + + for (i = 0; i < block->num_sps; i++) { + drm_printf(p, " - sp: %d\n", i); + + for (j = 0; j < block->num_usptps; j++) { + drm_printf(p, " - usptp: %d\n", j); + drm_printf(p, " size: %d\n", block->size); + + if (!obj->data) + continue; + + print_ascii85(p, block->size << 2, data); + + data += block->size; + } + } +} + static void a6xx_show_cluster_data(const u32 *registers, int size, u32 *data, struct drm_printer *p) { @@ -1308,6 +1825,34 @@ static void a6xx_show_cluster(struct a6xx_gpu_state_obj *obj, } } +static void a7xx_show_dbgahb_cluster(struct a6xx_gpu_state_obj *obj, + struct drm_printer *p) +{ + const struct gen7_sptp_cluster_registers *dbgahb = obj->handle; + + if (dbgahb) { + print_name(p, " - pipe: ", a7xx_pipe_names[dbgahb->pipe_id]); + print_name(p, " - cluster-name: ", a7xx_cluster_names[dbgahb->cluster_id]); + drm_printf(p, " - context: %d\n", dbgahb->context_id); + a7xx_show_registers_indented(dbgahb->regs, obj->data, p, 4); + } +} + +static void a7xx_show_cluster(struct a6xx_gpu_state_obj *obj, + struct drm_printer *p) +{ + const struct gen7_cluster_registers *cluster = obj->handle; + + if (cluster) { + int context = (cluster->context_id == STATE_FORCE_CTXT_1) ? 1 : 0; + + print_name(p, " - pipe: ", a7xx_pipe_names[cluster->pipe_id]); + print_name(p, " - cluster-name: ", a7xx_cluster_names[cluster->cluster_id]); + drm_printf(p, " - context: %d\n", context); + a7xx_show_registers_indented(cluster->regs, obj->data, p, 4); + } +} + static void a6xx_show_indexed_regs(struct a6xx_gpu_state_obj *obj, struct drm_printer *p) { @@ -1369,6 +1914,7 @@ static void a6xx_show_debugbus(struct a6xx_gpu_state *a6xx_state, void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state, struct drm_printer *p) { + struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu_state *a6xx_state = container_of(state, struct a6xx_gpu_state, base); int i; @@ -1421,12 +1967,17 @@ void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state, drm_puts(p, "registers:\n"); for (i = 0; i < a6xx_state->nr_registers; i++) { struct a6xx_gpu_state_obj *obj = &a6xx_state->registers[i]; - const struct a6xx_registers *regs = obj->handle; if (!obj->handle) continue; - a6xx_show_registers(regs->registers, obj->data, regs->count, p); + if (adreno_is_a7xx(adreno_gpu)) { + a7xx_show_registers(obj->handle, obj->data, p); + } else { + const struct a6xx_registers *regs = obj->handle; + + a6xx_show_registers(regs->registers, obj->data, regs->count, p); + } } drm_puts(p, "registers-gmu:\n"); @@ -1445,15 +1996,27 @@ void a6xx_show(struct msm_gpu *gpu, struct msm_gpu_state *state, a6xx_show_indexed_regs(&a6xx_state->indexed_regs[i], p); drm_puts(p, "shader-blocks:\n"); - for (i = 0; i < a6xx_state->nr_shaders; i++) - a6xx_show_shader(&a6xx_state->shaders[i], p); + for (i = 0; i < a6xx_state->nr_shaders; i++) { + if (adreno_is_a7xx(adreno_gpu)) + a7xx_show_shader(&a6xx_state->shaders[i], p); + else + a6xx_show_shader(&a6xx_state->shaders[i], p); + } drm_puts(p, "clusters:\n"); - for (i = 0; i < a6xx_state->nr_clusters; i++) - a6xx_show_cluster(&a6xx_state->clusters[i], p); + for (i = 0; i < a6xx_state->nr_clusters; i++) { + if (adreno_is_a7xx(adreno_gpu)) + a7xx_show_cluster(&a6xx_state->clusters[i], p); + else + a6xx_show_cluster(&a6xx_state->clusters[i], p); + } - for (i = 0; i < a6xx_state->nr_dbgahb_clusters; i++) - a6xx_show_dbgahb_cluster(&a6xx_state->dbgahb_clusters[i], p); + for (i = 0; i < a6xx_state->nr_dbgahb_clusters; i++) { + if (adreno_is_a7xx(adreno_gpu)) + a7xx_show_dbgahb_cluster(&a6xx_state->dbgahb_clusters[i], p); + else + a6xx_show_dbgahb_cluster(&a6xx_state->dbgahb_clusters[i], p); + } drm_puts(p, "debugbus:\n"); a6xx_show_debugbus(a6xx_state, p); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h index 9560fc1b858a..5ddd32063bcc 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu_state.h @@ -1,5 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 -/* Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. */ +/* + * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + */ #ifndef _A6XX_CRASH_DUMP_H_ #define _A6XX_CRASH_DUMP_H_ @@ -51,6 +54,7 @@ static const u32 a6xx_pc_vs_cluster[] = { #define CLUSTER_SP_PS 4 #define CLUSTER_PS 5 #define CLUSTER_VPC_PS 6 +#define CLUSTER_NONE 7 #define CLUSTER(_id, _reg, _sel_reg, _sel_val) \ { .id = _id, .name = #_id,\ @@ -337,27 +341,6 @@ static const struct a6xx_registers a6xx_vbif_reglist = static const struct a6xx_registers a6xx_gbif_reglist = REGS(a6xx_gbif_registers, 0, 0); -static const u32 a7xx_ahb_registers[] = { - /* RBBM_STATUS */ - 0x210, 0x210, - /* RBBM_STATUS2-3 */ - 0x212, 0x213, -}; - -static const u32 a7xx_gbif_registers[] = { - 0x3c00, 0x3c0b, - 0x3c40, 0x3c42, - 0x3c45, 0x3c47, - 0x3c49, 0x3c4a, - 0x3cc0, 0x3cd1, -}; - -static const struct a6xx_registers a7xx_ahb_reglist= - REGS(a7xx_ahb_registers, 0, 0); - -static const struct a6xx_registers a7xx_gbif_reglist = - REGS(a7xx_gbif_registers, 0, 0); - static const u32 a6xx_gmu_gx_registers[] = { /* GMU GX */ 0x0000, 0x0000, 0x0010, 0x0013, 0x0016, 0x0016, 0x0018, 0x001b, @@ -534,4 +517,288 @@ static const struct a6xx_debugbus_block a650_debugbus_blocks[] = { DEBUGBUS(A6XX_DBGBUS_SPTP_5, 0x100), }; +static const struct a6xx_debugbus_block a7xx_gbif_debugbus_blocks[] = { + DEBUGBUS(A7XX_DBGBUS_GBIF_CX, 0x100), + DEBUGBUS(A7XX_DBGBUS_GBIF_GX, 0x100), +}; + +static const struct a6xx_debugbus_block a7xx_cx_debugbus_blocks[] = { + DEBUGBUS(A7XX_DBGBUS_GMU_CX, 0x100), + DEBUGBUS(A7XX_DBGBUS_CX, 0x100), + DEBUGBUS(A7XX_DBGBUS_GBIF_CX, 0x100), +}; + +#define STATE_NON_CONTEXT 0 +#define STATE_TOGGLE_CTXT 1 +#define STATE_FORCE_CTXT_0 2 +#define STATE_FORCE_CTXT_1 3 + +struct gen7_sel_reg { + unsigned int host_reg; + unsigned int cd_reg; + unsigned int val; +}; + +struct gen7_cluster_registers { + /* cluster_id: Cluster identifier */ + int cluster_id; + /* pipe_id: Pipe Identifier */ + int pipe_id; + /* context_id: one of STATE_ that identifies the context to dump */ + int context_id; + /* regs: Pointer to an array of register pairs */ + const u32 *regs; + /* sel: Pointer to a selector register to write before reading */ + const struct gen7_sel_reg *sel; +}; + +struct gen7_sptp_cluster_registers { + /* cluster_id: Cluster identifier */ + enum a7xx_cluster cluster_id; + /* statetype: SP block state type for the cluster */ + enum a7xx_statetype_id statetype; + /* pipe_id: Pipe identifier */ + enum a7xx_pipe pipe_id; + /* context_id: Context identifier */ + int context_id; + /* location_id: Location identifier */ + enum a7xx_state_location location_id; + /* regs: Pointer to the list of register pairs to read */ + const u32 *regs; + /* regbase: Dword offset of the register block in the GPu register space */ + unsigned int regbase; +}; + +struct gen7_shader_block { + /* statetype: Type identifer for the block */ + u32 statetype; + /* size: Size of the block (in dwords) */ + u32 size; + /* num_sps: The SP id to dump */ + u32 num_sps; + /* num_usptps: The number of USPTPs to dump */; + u32 num_usptps; + /* pipe_id: Pipe identifier for the block data */ + u32 pipeid; + /* location: Location identifer for the block data */ + u32 location; +}; + +struct gen7_reg_list { + const u32 *regs; + const struct gen7_sel_reg *sel; +}; + +/* adreno_gen7_x_y_snapshot.h defines which debugbus blocks a given family has, but the + * list of debugbus blocks is global on a7xx. + */ + +#define A7XX_DEBUGBUS(_id, _count) [_id] = { .id = _id, .name = #_id, .count = _count }, +static const struct a6xx_debugbus_block a7xx_debugbus_blocks[] = { + A7XX_DEBUGBUS(A7XX_DBGBUS_CP_0_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_CP_0_1, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_RBBM, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_GBIF_GX, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_GBIF_CX, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_UCHE_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_UCHE_1, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TESS_BR, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TESS_BV, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_PC_BR, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_PC_BV, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VFDP_BR, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VFDP_BV, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_BR, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_BV, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TSE_BR, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TSE_BV, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_RAS_BR, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_RAS_BV, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VSC, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_COM_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_LRZ_BR, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_LRZ_BV, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_1, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_GMU_GX, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_DBGC, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_CX, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_GMU_CX, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_GPC_BR, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_GPC_BV, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_LARC, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_SPTP, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_RB_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_RB_1, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_RB_2, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_RB_3, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_RB_4, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_RB_5, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_UCHE_WRAPPER, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_1, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_2, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_3, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_4, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_CCU_5, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_1, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_2, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_3, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_4, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_5, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_6, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BR_7, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BV_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BV_1, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BV_2, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VFD_BV_3, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USP_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USP_1, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USP_2, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USP_3, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USP_4, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USP_5, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TP_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TP_1, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TP_2, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TP_3, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TP_4, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TP_5, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TP_6, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TP_7, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TP_8, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TP_9, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TP_10, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_TP_11, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_1, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_2, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_3, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_4, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_5, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_6, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_7, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_8, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_9, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_10, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_USPTP_11, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_CCHE_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_CCHE_1, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_CCHE_2, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_DSTR_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_DSTR_1, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_VPC_DSTR_2, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_1, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_2, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_3, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_4, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_HLSQ_DP_STR_5, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_DSTR_0, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_DSTR_1, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_UFC_DSTR_2, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_CGC_SUBCORE, 0x100) + A7XX_DEBUGBUS(A7XX_DBGBUS_CGC_CORE, 0x100) +}; + +#define A7XX_NAME(enumval) [enumval] = #enumval +static const char *a7xx_statetype_names[] = { + A7XX_NAME(A7XX_TP0_NCTX_REG), + A7XX_NAME(A7XX_TP0_CTX0_3D_CVS_REG), + A7XX_NAME(A7XX_TP0_CTX0_3D_CPS_REG), + A7XX_NAME(A7XX_TP0_CTX1_3D_CVS_REG), + A7XX_NAME(A7XX_TP0_CTX1_3D_CPS_REG), + A7XX_NAME(A7XX_TP0_CTX2_3D_CPS_REG), + A7XX_NAME(A7XX_TP0_CTX3_3D_CPS_REG), + A7XX_NAME(A7XX_TP0_TMO_DATA), + A7XX_NAME(A7XX_TP0_SMO_DATA), + A7XX_NAME(A7XX_TP0_MIPMAP_BASE_DATA), + A7XX_NAME(A7XX_SP_NCTX_REG), + A7XX_NAME(A7XX_SP_CTX0_3D_CVS_REG), + A7XX_NAME(A7XX_SP_CTX0_3D_CPS_REG), + A7XX_NAME(A7XX_SP_CTX1_3D_CVS_REG), + A7XX_NAME(A7XX_SP_CTX1_3D_CPS_REG), + A7XX_NAME(A7XX_SP_CTX2_3D_CPS_REG), + A7XX_NAME(A7XX_SP_CTX3_3D_CPS_REG), + A7XX_NAME(A7XX_SP_INST_DATA), + A7XX_NAME(A7XX_SP_INST_DATA_1), + A7XX_NAME(A7XX_SP_LB_0_DATA), + A7XX_NAME(A7XX_SP_LB_1_DATA), + A7XX_NAME(A7XX_SP_LB_2_DATA), + A7XX_NAME(A7XX_SP_LB_3_DATA), + A7XX_NAME(A7XX_SP_LB_4_DATA), + A7XX_NAME(A7XX_SP_LB_5_DATA), + A7XX_NAME(A7XX_SP_LB_6_DATA), + A7XX_NAME(A7XX_SP_LB_7_DATA), + A7XX_NAME(A7XX_SP_CB_RAM), + A7XX_NAME(A7XX_SP_LB_13_DATA), + A7XX_NAME(A7XX_SP_LB_14_DATA), + A7XX_NAME(A7XX_SP_INST_TAG), + A7XX_NAME(A7XX_SP_INST_DATA_2), + A7XX_NAME(A7XX_SP_TMO_TAG), + A7XX_NAME(A7XX_SP_SMO_TAG), + A7XX_NAME(A7XX_SP_STATE_DATA), + A7XX_NAME(A7XX_SP_HWAVE_RAM), + A7XX_NAME(A7XX_SP_L0_INST_BUF), + A7XX_NAME(A7XX_SP_LB_8_DATA), + A7XX_NAME(A7XX_SP_LB_9_DATA), + A7XX_NAME(A7XX_SP_LB_10_DATA), + A7XX_NAME(A7XX_SP_LB_11_DATA), + A7XX_NAME(A7XX_SP_LB_12_DATA), + A7XX_NAME(A7XX_HLSQ_DATAPATH_DSTR_META), + A7XX_NAME(A7XX_HLSQ_L2STC_TAG_RAM), + A7XX_NAME(A7XX_HLSQ_L2STC_INFO_CMD), + A7XX_NAME(A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG), + A7XX_NAME(A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG), + A7XX_NAME(A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM), + A7XX_NAME(A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM), + A7XX_NAME(A7XX_HLSQ_CHUNK_CVS_RAM), + A7XX_NAME(A7XX_HLSQ_CHUNK_CPS_RAM), + A7XX_NAME(A7XX_HLSQ_CHUNK_CVS_RAM_TAG), + A7XX_NAME(A7XX_HLSQ_CHUNK_CPS_RAM_TAG), + A7XX_NAME(A7XX_HLSQ_ICB_CVS_CB_BASE_TAG), + A7XX_NAME(A7XX_HLSQ_ICB_CPS_CB_BASE_TAG), + A7XX_NAME(A7XX_HLSQ_CVS_MISC_RAM), + A7XX_NAME(A7XX_HLSQ_CPS_MISC_RAM), + A7XX_NAME(A7XX_HLSQ_CPS_MISC_RAM_1), + A7XX_NAME(A7XX_HLSQ_INST_RAM), + A7XX_NAME(A7XX_HLSQ_GFX_CVS_CONST_RAM), + A7XX_NAME(A7XX_HLSQ_GFX_CPS_CONST_RAM), + A7XX_NAME(A7XX_HLSQ_CVS_MISC_RAM_TAG), + A7XX_NAME(A7XX_HLSQ_CPS_MISC_RAM_TAG), + A7XX_NAME(A7XX_HLSQ_INST_RAM_TAG), + A7XX_NAME(A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG), + A7XX_NAME(A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG), + A7XX_NAME(A7XX_HLSQ_GFX_LOCAL_MISC_RAM), + A7XX_NAME(A7XX_HLSQ_GFX_LOCAL_MISC_RAM_TAG), + A7XX_NAME(A7XX_HLSQ_INST_RAM_1), + A7XX_NAME(A7XX_HLSQ_STPROC_META), + A7XX_NAME(A7XX_HLSQ_BV_BE_META), + A7XX_NAME(A7XX_HLSQ_INST_RAM_2), + A7XX_NAME(A7XX_HLSQ_DATAPATH_META), + A7XX_NAME(A7XX_HLSQ_FRONTEND_META), + A7XX_NAME(A7XX_HLSQ_INDIRECT_META), + A7XX_NAME(A7XX_HLSQ_BACKEND_META), +}; + +static const char *a7xx_pipe_names[] = { + A7XX_NAME(A7XX_PIPE_NONE), + A7XX_NAME(A7XX_PIPE_BR), + A7XX_NAME(A7XX_PIPE_BV), + A7XX_NAME(A7XX_PIPE_LPAC), +}; + +static const char *a7xx_cluster_names[] = { + A7XX_NAME(A7XX_CLUSTER_NONE), + A7XX_NAME(A7XX_CLUSTER_FE), + A7XX_NAME(A7XX_CLUSTER_SP_VS), + A7XX_NAME(A7XX_CLUSTER_PC_VS), + A7XX_NAME(A7XX_CLUSTER_GRAS), + A7XX_NAME(A7XX_CLUSTER_SP_PS), + A7XX_NAME(A7XX_CLUSTER_VPC_PS), + A7XX_NAME(A7XX_CLUSTER_PS), +}; + #endif diff --git a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h index 51c320a2e5c0..fbc27930e550 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_common.xml.h +++ b/drivers/gpu/drm/msm/adreno/adreno_common.xml.h @@ -3,50 +3,27 @@ /* Autogenerated file, DO NOT EDIT manually! -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://github.com/freedreno/envytools/ -git clone https://github.com/freedreno/envytools.git +This file was generated by the rules-ng-ng gen_header.py tool in this git repository: +http://gitlab.freedesktop.org/mesa/mesa/ +git clone https://gitlab.freedesktop.org/mesa/mesa.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2023-03-10 18:32:52) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 91929 bytes, from 2023-02-28 23:52:27) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from 2023-03-10 18:32:53) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 74995 bytes, from 2023-03-20 18:06:23) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113474 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149590 bytes, from 2023-02-14 19:37:12) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 198949 bytes, from 2023-03-20 18:06:23) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11404 bytes, from 2023-03-10 18:32:53) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 9055 bytes, from 2023-03-10 18:32:52) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2976 bytes, from 2023-03-10 18:32:52) - -Copyright (C) 2013-2023 by the following authors: -- Rob Clark <robdclark@gmail.com> (robclark) -- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023) */ +#ifdef __KERNEL__ +#include <linux/bug.h> +#define assert(x) BUG_ON(!(x)) +#else +#include <assert.h> +#endif + +#ifdef __cplusplus +#define __struct_cast(X) +#else +#define __struct_cast(X) (struct X) +#endif enum chip { A2XX = 2, @@ -141,11 +118,13 @@ enum a3xx_rop_code { ROP_COPY_INVERTED = 3, ROP_AND_REVERSE = 4, ROP_INVERT = 5, + ROP_XOR = 6, ROP_NAND = 7, ROP_AND = 8, ROP_EQUIV = 9, ROP_NOOP = 10, ROP_OR_INVERTED = 11, + ROP_COPY = 12, ROP_OR_REVERSE = 13, ROP_OR = 14, ROP_SET = 15, @@ -258,7 +237,8 @@ static inline uint32_t AXXX_CP_RB_RPTR_ADDR_SWAP(uint32_t val) #define AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT 2 static inline uint32_t AXXX_CP_RB_RPTR_ADDR_ADDR(uint32_t val) { - return ((val >> 2) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << AXXX_CP_RB_RPTR_ADDR_ADDR__SHIFT) & AXXX_CP_RB_RPTR_ADDR_ADDR__MASK; } #define REG_AXXX_CP_RB_RPTR 0x000001c4 @@ -471,174 +451,34 @@ static inline uint32_t AXXX_CP_CSQ_IB2_STAT_WPTR(uint32_t val) #define REG_AXXX_CP_IB2_BUFSZ 0x0000045b #define REG_AXXX_CP_STAT 0x0000047f -#define AXXX_CP_STAT_CP_BUSY__MASK 0x80000000 -#define AXXX_CP_STAT_CP_BUSY__SHIFT 31 -static inline uint32_t AXXX_CP_STAT_CP_BUSY(uint32_t val) -{ - return ((val) << AXXX_CP_STAT_CP_BUSY__SHIFT) & AXXX_CP_STAT_CP_BUSY__MASK; -} -#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__MASK 0x40000000 -#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__SHIFT 30 -static inline uint32_t AXXX_CP_STAT_VS_EVENT_FIFO_BUSY(uint32_t val) -{ - return ((val) << AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_VS_EVENT_FIFO_BUSY__MASK; -} -#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__MASK 0x20000000 -#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__SHIFT 29 -static inline uint32_t AXXX_CP_STAT_PS_EVENT_FIFO_BUSY(uint32_t val) -{ - return ((val) << AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_PS_EVENT_FIFO_BUSY__MASK; -} -#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__MASK 0x10000000 -#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__SHIFT 28 -static inline uint32_t AXXX_CP_STAT_CF_EVENT_FIFO_BUSY(uint32_t val) -{ - return ((val) << AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_CF_EVENT_FIFO_BUSY__MASK; -} -#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__MASK 0x08000000 -#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__SHIFT 27 -static inline uint32_t AXXX_CP_STAT_RB_EVENT_FIFO_BUSY(uint32_t val) -{ - return ((val) << AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__SHIFT) & AXXX_CP_STAT_RB_EVENT_FIFO_BUSY__MASK; -} -#define AXXX_CP_STAT_ME_BUSY__MASK 0x04000000 -#define AXXX_CP_STAT_ME_BUSY__SHIFT 26 -static inline uint32_t AXXX_CP_STAT_ME_BUSY(uint32_t val) -{ - return ((val) << AXXX_CP_STAT_ME_BUSY__SHIFT) & AXXX_CP_STAT_ME_BUSY__MASK; -} -#define AXXX_CP_STAT_MIU_WR_C_BUSY__MASK 0x02000000 -#define AXXX_CP_STAT_MIU_WR_C_BUSY__SHIFT 25 -static inline uint32_t AXXX_CP_STAT_MIU_WR_C_BUSY(uint32_t val) -{ - return ((val) << AXXX_CP_STAT_MIU_WR_C_BUSY__SHIFT) & AXXX_CP_STAT_MIU_WR_C_BUSY__MASK; -} -#define AXXX_CP_STAT_CP_3D_BUSY__MASK 0x00800000 -#define AXXX_CP_STAT_CP_3D_BUSY__SHIFT 23 -static inline uint32_t AXXX_CP_STAT_CP_3D_BUSY(uint32_t val) -{ - return ((val) << AXXX_CP_STAT_CP_3D_BUSY__SHIFT) & AXXX_CP_STAT_CP_3D_BUSY__MASK; -} -#define AXXX_CP_STAT_CP_NRT_BUSY__MASK 0x00400000 -#define AXXX_CP_STAT_CP_NRT_BUSY__SHIFT 22 -static inline uint32_t AXXX_CP_STAT_CP_NRT_BUSY(uint32_t val) -{ - return ((val) << AXXX_CP_STAT_CP_NRT_BUSY__SHIFT) & AXXX_CP_STAT_CP_NRT_BUSY__MASK; -} -#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY__MASK 0x00200000 -#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY__SHIFT 21 -static inline uint32_t AXXX_CP_STAT_RBIU_SCRATCH_BUSY(uint32_t val) -{ - return ((val) << AXXX_CP_STAT_RBIU_SCRATCH_BUSY__SHIFT) & AXXX_CP_STAT_RBIU_SCRATCH_BUSY__MASK; -} -#define AXXX_CP_STAT_RCIU_ME_BUSY__MASK 0x00100000 -#define AXXX_CP_STAT_RCIU_ME_BUSY__SHIFT 20 -static inline uint32_t AXXX_CP_STAT_RCIU_ME_BUSY(uint32_t val) -{ - return ((val) << AXXX_CP_STAT_RCIU_ME_BUSY__SHIFT) & AXXX_CP_STAT_RCIU_ME_BUSY__MASK; -} -#define AXXX_CP_STAT_RCIU_PFP_BUSY__MASK 0x00080000 -#define AXXX_CP_STAT_RCIU_PFP_BUSY__SHIFT 19 -static inline uint32_t AXXX_CP_STAT_RCIU_PFP_BUSY(uint32_t val) -{ - return ((val) << AXXX_CP_STAT_RCIU_PFP_BUSY__SHIFT) & AXXX_CP_STAT_RCIU_PFP_BUSY__MASK; -} -#define AXXX_CP_STAT_MEQ_RING_BUSY__MASK 0x00040000 -#define AXXX_CP_STAT_MEQ_RING_BUSY__SHIFT 18 -static inline uint32_t AXXX_CP_STAT_MEQ_RING_BUSY(uint32_t val) -{ - return ((val) << AXXX_CP_STAT_MEQ_RING_BUSY__SHIFT) & AXXX_CP_STAT_MEQ_RING_BUSY__MASK; -} -#define AXXX_CP_STAT_PFP_BUSY__MASK 0x00020000 -#define AXXX_CP_STAT_PFP_BUSY__SHIFT 17 -static inline uint32_t AXXX_CP_STAT_PFP_BUSY(uint32_t val) -{ - return ((val) << AXXX_CP_STAT_PFP_BUSY__SHIFT) & AXXX_CP_STAT_PFP_BUSY__MASK; -} -#define AXXX_CP_STAT_ST_QUEUE_BUSY__MASK 0x00010000 -#define AXXX_CP_STAT_ST_QUEUE_BUSY__SHIFT 16 -static inline uint32_t AXXX_CP_STAT_ST_QUEUE_BUSY(uint32_t val) -{ - return ((val) << AXXX_CP_STAT_ST_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_ST_QUEUE_BUSY__MASK; -} -#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__MASK 0x00002000 -#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__SHIFT 13 -static inline uint32_t AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY(uint32_t val) -{ - return ((val) << AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY__MASK; -} -#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__MASK 0x00001000 -#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__SHIFT 12 -static inline uint32_t AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY(uint32_t val) -{ - return ((val) << AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY__MASK; -} -#define AXXX_CP_STAT_RING_QUEUE_BUSY__MASK 0x00000800 -#define AXXX_CP_STAT_RING_QUEUE_BUSY__SHIFT 11 -static inline uint32_t AXXX_CP_STAT_RING_QUEUE_BUSY(uint32_t val) -{ - return ((val) << AXXX_CP_STAT_RING_QUEUE_BUSY__SHIFT) & AXXX_CP_STAT_RING_QUEUE_BUSY__MASK; -} -#define AXXX_CP_STAT_CSF_BUSY__MASK 0x00000400 -#define AXXX_CP_STAT_CSF_BUSY__SHIFT 10 -static inline uint32_t AXXX_CP_STAT_CSF_BUSY(uint32_t val) -{ - return ((val) << AXXX_CP_STAT_CSF_BUSY__SHIFT) & AXXX_CP_STAT_CSF_BUSY__MASK; -} -#define AXXX_CP_STAT_CSF_ST_BUSY__MASK 0x00000200 -#define AXXX_CP_STAT_CSF_ST_BUSY__SHIFT 9 -static inline uint32_t AXXX_CP_STAT_CSF_ST_BUSY(uint32_t val) -{ - return ((val) << AXXX_CP_STAT_CSF_ST_BUSY__SHIFT) & AXXX_CP_STAT_CSF_ST_BUSY__MASK; -} -#define AXXX_CP_STAT_EVENT_BUSY__MASK 0x00000100 -#define AXXX_CP_STAT_EVENT_BUSY__SHIFT 8 -static inline uint32_t AXXX_CP_STAT_EVENT_BUSY(uint32_t val) -{ - return ((val) << AXXX_CP_STAT_EVENT_BUSY__SHIFT) & AXXX_CP_STAT_EVENT_BUSY__MASK; -} -#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY__MASK 0x00000080 -#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY__SHIFT 7 -static inline uint32_t AXXX_CP_STAT_CSF_INDIRECT2_BUSY(uint32_t val) -{ - return ((val) << AXXX_CP_STAT_CSF_INDIRECT2_BUSY__SHIFT) & AXXX_CP_STAT_CSF_INDIRECT2_BUSY__MASK; -} -#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY__MASK 0x00000040 -#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY__SHIFT 6 -static inline uint32_t AXXX_CP_STAT_CSF_INDIRECTS_BUSY(uint32_t val) -{ - return ((val) << AXXX_CP_STAT_CSF_INDIRECTS_BUSY__SHIFT) & AXXX_CP_STAT_CSF_INDIRECTS_BUSY__MASK; -} -#define AXXX_CP_STAT_CSF_RING_BUSY__MASK 0x00000020 -#define AXXX_CP_STAT_CSF_RING_BUSY__SHIFT 5 -static inline uint32_t AXXX_CP_STAT_CSF_RING_BUSY(uint32_t val) -{ - return ((val) << AXXX_CP_STAT_CSF_RING_BUSY__SHIFT) & AXXX_CP_STAT_CSF_RING_BUSY__MASK; -} -#define AXXX_CP_STAT_RCIU_BUSY__MASK 0x00000010 -#define AXXX_CP_STAT_RCIU_BUSY__SHIFT 4 -static inline uint32_t AXXX_CP_STAT_RCIU_BUSY(uint32_t val) -{ - return ((val) << AXXX_CP_STAT_RCIU_BUSY__SHIFT) & AXXX_CP_STAT_RCIU_BUSY__MASK; -} -#define AXXX_CP_STAT_RBIU_BUSY__MASK 0x00000008 -#define AXXX_CP_STAT_RBIU_BUSY__SHIFT 3 -static inline uint32_t AXXX_CP_STAT_RBIU_BUSY(uint32_t val) -{ - return ((val) << AXXX_CP_STAT_RBIU_BUSY__SHIFT) & AXXX_CP_STAT_RBIU_BUSY__MASK; -} -#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY__MASK 0x00000004 -#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY__SHIFT 2 -static inline uint32_t AXXX_CP_STAT_MIU_RD_RETURN_BUSY(uint32_t val) -{ - return ((val) << AXXX_CP_STAT_MIU_RD_RETURN_BUSY__SHIFT) & AXXX_CP_STAT_MIU_RD_RETURN_BUSY__MASK; -} -#define AXXX_CP_STAT_MIU_RD_REQ_BUSY__MASK 0x00000002 -#define AXXX_CP_STAT_MIU_RD_REQ_BUSY__SHIFT 1 -static inline uint32_t AXXX_CP_STAT_MIU_RD_REQ_BUSY(uint32_t val) -{ - return ((val) << AXXX_CP_STAT_MIU_RD_REQ_BUSY__SHIFT) & AXXX_CP_STAT_MIU_RD_REQ_BUSY__MASK; -} +#define AXXX_CP_STAT_CP_BUSY 0x80000000 +#define AXXX_CP_STAT_VS_EVENT_FIFO_BUSY 0x40000000 +#define AXXX_CP_STAT_PS_EVENT_FIFO_BUSY 0x20000000 +#define AXXX_CP_STAT_CF_EVENT_FIFO_BUSY 0x10000000 +#define AXXX_CP_STAT_RB_EVENT_FIFO_BUSY 0x08000000 +#define AXXX_CP_STAT_ME_BUSY 0x04000000 +#define AXXX_CP_STAT_MIU_WR_C_BUSY 0x02000000 +#define AXXX_CP_STAT_CP_3D_BUSY 0x00800000 +#define AXXX_CP_STAT_CP_NRT_BUSY 0x00400000 +#define AXXX_CP_STAT_RBIU_SCRATCH_BUSY 0x00200000 +#define AXXX_CP_STAT_RCIU_ME_BUSY 0x00100000 +#define AXXX_CP_STAT_RCIU_PFP_BUSY 0x00080000 +#define AXXX_CP_STAT_MEQ_RING_BUSY 0x00040000 +#define AXXX_CP_STAT_PFP_BUSY 0x00020000 +#define AXXX_CP_STAT_ST_QUEUE_BUSY 0x00010000 +#define AXXX_CP_STAT_INDIRECT2_QUEUE_BUSY 0x00002000 +#define AXXX_CP_STAT_INDIRECTS_QUEUE_BUSY 0x00001000 +#define AXXX_CP_STAT_RING_QUEUE_BUSY 0x00000800 +#define AXXX_CP_STAT_CSF_BUSY 0x00000400 +#define AXXX_CP_STAT_CSF_ST_BUSY 0x00000200 +#define AXXX_CP_STAT_EVENT_BUSY 0x00000100 +#define AXXX_CP_STAT_CSF_INDIRECT2_BUSY 0x00000080 +#define AXXX_CP_STAT_CSF_INDIRECTS_BUSY 0x00000040 +#define AXXX_CP_STAT_CSF_RING_BUSY 0x00000020 +#define AXXX_CP_STAT_RCIU_BUSY 0x00000010 +#define AXXX_CP_STAT_RBIU_BUSY 0x00000008 +#define AXXX_CP_STAT_MIU_RD_RETURN_BUSY 0x00000004 +#define AXXX_CP_STAT_MIU_RD_REQ_BUSY 0x00000002 #define AXXX_CP_STAT_MIU_WR_BUSY 0x00000001 #define REG_AXXX_CP_SCRATCH_REG0 0x00000578 @@ -693,5 +533,7 @@ static inline uint32_t AXXX_CP_STAT_MIU_RD_REQ_BUSY(uint32_t val) #define REG_AXXX_CP_ME_VS_FETCH_DONE_DATA 0x00000614 +#ifdef __cplusplus +#endif #endif /* ADRENO_COMMON_XML */ diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 2ce7d7b1690d..c3703a51287b 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -55,10 +55,17 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a2xx_gpu_init, }, { - .chip_ids = ADRENO_CHIP_IDS( - 0x03000512, - 0x03000520 - ), + .chip_ids = ADRENO_CHIP_IDS(0x03000512), + .family = ADRENO_3XX, + .fw = { + [ADRENO_FW_PM4] = "a330_pm4.fw", + [ADRENO_FW_PFP] = "a330_pfp.fw", + }, + .gmem = SZ_128K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a3xx_gpu_init, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x03000520), .family = ADRENO_3XX, .revn = 305, .fw = { @@ -294,6 +301,27 @@ static const struct adreno_info gpulist[] = { { 127, 4 }, ), }, { + .machine = "qcom,sm7150", + .chip_ids = ADRENO_CHIP_IDS(0x06010800), + .family = ADRENO_6XX_GEN1, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a630_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, + .init = a6xx_gpu_init, + .zapfw = "a615_zap.mbn", + .hwcg = a615_hwcg, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 128, 1 }, + { 146, 2 }, + { 167, 3 }, + { 172, 4 }, + ), + }, { .chip_ids = ADRENO_CHIP_IDS(0x06010800), .family = ADRENO_6XX_GEN1, .revn = 618, @@ -493,6 +521,24 @@ static const struct adreno_info gpulist[] = { .hwcg = a690_hwcg, .address_space_size = SZ_16G, }, { + .chip_ids = ADRENO_CHIP_IDS(0x07000200), + .family = ADRENO_6XX_GEN1, /* NOT a mistake! */ + .fw = { + [ADRENO_FW_SQE] = "a702_sqe.fw", + }, + .gmem = SZ_128K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_HW_APRIV, + .init = a6xx_gpu_init, + .zapfw = "a702_zap.mbn", + .hwcg = a702_hwcg, + .speedbins = ADRENO_SPEEDBINS( + { 0, 0 }, + { 236, 1 }, + { 178, 2 }, + { 142, 3 }, + ), + }, { .chip_ids = ADRENO_CHIP_IDS(0x07030001), .family = ADRENO_7XX_GEN1, .fw = { @@ -522,6 +568,20 @@ static const struct adreno_info gpulist[] = { .zapfw = "a740_zap.mdt", .hwcg = a740_hwcg, .address_space_size = SZ_16G, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */ + .family = ADRENO_7XX_GEN3, + .fw = { + [ADRENO_FW_SQE] = "gen70900_sqe.fw", + [ADRENO_FW_GMU] = "gmu_gen70900.bin", + }, + .gmem = 3 * SZ_1M, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, + .init = a6xx_gpu_init, + .zapfw = "gen70900_zap.mbn", + .address_space_size = SZ_16G, }, }; @@ -539,6 +599,7 @@ MODULE_FIRMWARE("qcom/a530_zap.b00"); MODULE_FIRMWARE("qcom/a530_zap.b01"); MODULE_FIRMWARE("qcom/a530_zap.b02"); MODULE_FIRMWARE("qcom/a540_gpmu.fw2"); +MODULE_FIRMWARE("qcom/a615_zap.mbn"); MODULE_FIRMWARE("qcom/a619_gmu.bin"); MODULE_FIRMWARE("qcom/a630_sqe.fw"); MODULE_FIRMWARE("qcom/a630_gmu.bin"); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h b/drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h new file mode 100644 index 000000000000..cb66ece6606b --- /dev/null +++ b/drivers/gpu/drm/msm/adreno/adreno_gen7_0_0_snapshot.h @@ -0,0 +1,928 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#ifndef __ADRENO_GEN7_0_0_SNAPSHOT_H +#define __ADRENO_GEN7_0_0_SNAPSHOT_H + +#include "a6xx_gpu_state.h" + +static const u32 gen7_0_0_debugbus_blocks[] = { + A7XX_DBGBUS_CP_0_0, + A7XX_DBGBUS_CP_0_1, + A7XX_DBGBUS_RBBM, + A7XX_DBGBUS_HLSQ, + A7XX_DBGBUS_UCHE_0, + A7XX_DBGBUS_TESS_BR, + A7XX_DBGBUS_TESS_BV, + A7XX_DBGBUS_PC_BR, + A7XX_DBGBUS_PC_BV, + A7XX_DBGBUS_VFDP_BR, + A7XX_DBGBUS_VFDP_BV, + A7XX_DBGBUS_VPC_BR, + A7XX_DBGBUS_VPC_BV, + A7XX_DBGBUS_TSE_BR, + A7XX_DBGBUS_TSE_BV, + A7XX_DBGBUS_RAS_BR, + A7XX_DBGBUS_RAS_BV, + A7XX_DBGBUS_VSC, + A7XX_DBGBUS_COM_0, + A7XX_DBGBUS_LRZ_BR, + A7XX_DBGBUS_LRZ_BV, + A7XX_DBGBUS_UFC_0, + A7XX_DBGBUS_UFC_1, + A7XX_DBGBUS_GMU_GX, + A7XX_DBGBUS_DBGC, + A7XX_DBGBUS_GPC_BR, + A7XX_DBGBUS_GPC_BV, + A7XX_DBGBUS_LARC, + A7XX_DBGBUS_HLSQ_SPTP, + A7XX_DBGBUS_RB_0, + A7XX_DBGBUS_RB_1, + A7XX_DBGBUS_RB_2, + A7XX_DBGBUS_RB_3, + A7XX_DBGBUS_UCHE_WRAPPER, + A7XX_DBGBUS_CCU_0, + A7XX_DBGBUS_CCU_1, + A7XX_DBGBUS_CCU_2, + A7XX_DBGBUS_CCU_3, + A7XX_DBGBUS_VFD_BR_0, + A7XX_DBGBUS_VFD_BR_1, + A7XX_DBGBUS_VFD_BR_2, + A7XX_DBGBUS_VFD_BR_3, + A7XX_DBGBUS_VFD_BR_4, + A7XX_DBGBUS_VFD_BR_5, + A7XX_DBGBUS_VFD_BR_6, + A7XX_DBGBUS_VFD_BR_7, + A7XX_DBGBUS_VFD_BV_0, + A7XX_DBGBUS_VFD_BV_1, + A7XX_DBGBUS_VFD_BV_2, + A7XX_DBGBUS_VFD_BV_3, + A7XX_DBGBUS_USP_0, + A7XX_DBGBUS_USP_1, + A7XX_DBGBUS_USP_2, + A7XX_DBGBUS_USP_3, + A7XX_DBGBUS_TP_0, + A7XX_DBGBUS_TP_1, + A7XX_DBGBUS_TP_2, + A7XX_DBGBUS_TP_3, + A7XX_DBGBUS_TP_4, + A7XX_DBGBUS_TP_5, + A7XX_DBGBUS_TP_6, + A7XX_DBGBUS_TP_7, + A7XX_DBGBUS_USPTP_0, + A7XX_DBGBUS_USPTP_1, + A7XX_DBGBUS_USPTP_2, + A7XX_DBGBUS_USPTP_3, + A7XX_DBGBUS_USPTP_4, + A7XX_DBGBUS_USPTP_5, + A7XX_DBGBUS_USPTP_6, + A7XX_DBGBUS_USPTP_7, +}; + +static struct gen7_shader_block gen7_0_0_shader_blocks[] = { + {A7XX_TP0_TMO_DATA, 0x200, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_TP0_SMO_DATA, 0x80, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_TP0_MIPMAP_BASE_DATA, 0x3c0, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_INST_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_INST_DATA_1, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_0_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_1_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_2_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_3_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_4_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_5_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_6_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_7_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_CB_RAM, 0x390, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_INST_TAG, 0x90, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_INST_DATA_2, 0x200, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_TMO_TAG, 0x80, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_SMO_TAG, 0x80, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_STATE_DATA, 0x40, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_HWAVE_RAM, 0x100, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_L0_INST_BUF, 0x50, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_8_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_9_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_10_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_11_DATA, 0x800, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_12_DATA, 0x200, 4, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CHUNK_CPS_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CHUNK_CPS_RAM, 0x300, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CVS_MISC_RAM, 0x280, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CVS_MISC_RAM, 0x280, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CPS_MISC_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CPS_MISC_RAM, 0x800, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CPS_MISC_RAM_1, 0x200, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_INST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_INST_RAM, 0x800, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_INST_RAM, 0x800, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_INST_RAM_1, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_STPROC_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_BV_BE_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_BV_BE_META, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_DATAPATH_META, 0x20, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_FRONTEND_META, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_FRONTEND_META, 0x40, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_FRONTEND_META, 0x40, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_INDIRECT_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE}, +}; + +static const u32 gen7_0_0_pre_crashdumper_gpu_registers[] = { + 0x00210, 0x00210, 0x00212, 0x00213, 0x03c00, 0x03c0b, 0x03c40, 0x03c42, + 0x03c45, 0x03c47, 0x03c49, 0x03c4a, 0x03cc0, 0x03cd1, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_pre_crashdumper_gpu_registers), 8)); + +static const u32 gen7_0_0_post_crashdumper_registers[] = { + 0x00535, 0x00535, 0x0f400, 0x0f400, 0x0f800, 0x0f803, 0x0fc00, 0x0fc01, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_post_crashdumper_registers), 8)); + +static const u32 gen7_0_0_gpu_registers[] = { + 0x00000, 0x00000, 0x00002, 0x00002, 0x00011, 0x00012, 0x00016, 0x0001b, + 0x0001f, 0x00032, 0x00038, 0x0003c, 0x00042, 0x00042, 0x00044, 0x00044, + 0x00047, 0x00047, 0x00049, 0x0004a, 0x0004c, 0x0004c, 0x00050, 0x00050, + 0x00056, 0x00056, 0x00073, 0x00075, 0x000ad, 0x000ae, 0x000b0, 0x000b0, + 0x000b4, 0x000b4, 0x000b8, 0x000b8, 0x000bc, 0x000bc, 0x000c0, 0x000c0, + 0x000c4, 0x000c4, 0x000c8, 0x000c8, 0x000cc, 0x000cc, 0x000d0, 0x000d0, + 0x000d4, 0x000d4, 0x000d8, 0x000d8, 0x000dc, 0x000dc, 0x000e0, 0x000e0, + 0x000e4, 0x000e4, 0x000e8, 0x000e8, 0x000ec, 0x000ec, 0x000f0, 0x000f0, + 0x000f4, 0x000f4, 0x000f8, 0x000f8, 0x00100, 0x00100, 0x00104, 0x0010b, + 0x0010f, 0x0011d, 0x0012f, 0x0012f, 0x00200, 0x0020d, 0x00211, 0x00211, + 0x00215, 0x00243, 0x00260, 0x00268, 0x00272, 0x00274, 0x00281, 0x0028d, + 0x00300, 0x00401, 0x00410, 0x00451, 0x00460, 0x004a3, 0x004c0, 0x004d1, + 0x00500, 0x00500, 0x00507, 0x0050b, 0x0050f, 0x0050f, 0x00511, 0x00511, + 0x00533, 0x00534, 0x00536, 0x00536, 0x00540, 0x00555, 0x00564, 0x00567, + 0x00574, 0x00577, 0x005fb, 0x005ff, 0x00800, 0x00808, 0x00810, 0x00813, + 0x00820, 0x00821, 0x00823, 0x00827, 0x00830, 0x00834, 0x0083f, 0x00841, + 0x00843, 0x00847, 0x0084f, 0x00886, 0x008a0, 0x008ab, 0x008c0, 0x008c0, + 0x008c4, 0x008c5, 0x008d0, 0x008dd, 0x008e0, 0x008e6, 0x008f0, 0x008f3, + 0x00900, 0x00903, 0x00908, 0x00911, 0x00928, 0x0093e, 0x00942, 0x0094d, + 0x00980, 0x00984, 0x0098d, 0x0098f, 0x009b0, 0x009b4, 0x009c2, 0x009c9, + 0x009ce, 0x009d7, 0x009e0, 0x009e7, 0x00a00, 0x00a00, 0x00a02, 0x00a03, + 0x00a10, 0x00a4f, 0x00a61, 0x00a9f, 0x00ad0, 0x00adb, 0x00b00, 0x00b31, + 0x00b35, 0x00b3c, 0x00b40, 0x00b40, 0x00c00, 0x00c00, 0x00c02, 0x00c04, + 0x00c06, 0x00c06, 0x00c10, 0x00cd9, 0x00ce0, 0x00d0c, 0x00df0, 0x00df4, + 0x00e01, 0x00e02, 0x00e07, 0x00e0e, 0x00e10, 0x00e13, 0x00e17, 0x00e19, + 0x00e1b, 0x00e2b, 0x00e30, 0x00e32, 0x00e38, 0x00e3c, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_gpu_registers), 8)); + +static const u32 gen7_0_0_gmu_registers[] = { + 0x10001, 0x10001, 0x10003, 0x10003, 0x10401, 0x10401, 0x10403, 0x10403, + 0x10801, 0x10801, 0x10803, 0x10803, 0x10c01, 0x10c01, 0x10c03, 0x10c03, + 0x11001, 0x11001, 0x11003, 0x11003, 0x11401, 0x11401, 0x11403, 0x11403, + 0x11801, 0x11801, 0x11803, 0x11803, 0x11c01, 0x11c01, 0x11c03, 0x11c03, + 0x1f400, 0x1f40d, 0x1f40f, 0x1f411, 0x1f500, 0x1f500, 0x1f507, 0x1f507, + 0x1f509, 0x1f50b, 0x1f800, 0x1f804, 0x1f807, 0x1f808, 0x1f80b, 0x1f80c, + 0x1f80f, 0x1f80f, 0x1f811, 0x1f811, 0x1f813, 0x1f817, 0x1f819, 0x1f81c, + 0x1f824, 0x1f82a, 0x1f82d, 0x1f830, 0x1f840, 0x1f853, 0x1f860, 0x1f860, + 0x1f870, 0x1f879, 0x1f87f, 0x1f87f, 0x1f888, 0x1f889, 0x1f8a0, 0x1f8a2, + 0x1f8a4, 0x1f8af, 0x1f8c0, 0x1f8c1, 0x1f8c3, 0x1f8c4, 0x1f8d0, 0x1f8d0, + 0x1f8ec, 0x1f8ec, 0x1f8f0, 0x1f8f1, 0x1f910, 0x1f914, 0x1f920, 0x1f921, + 0x1f924, 0x1f925, 0x1f928, 0x1f929, 0x1f92c, 0x1f92d, 0x1f940, 0x1f940, + 0x1f942, 0x1f944, 0x1f948, 0x1f94a, 0x1f94f, 0x1f951, 0x1f958, 0x1f95a, + 0x1f95d, 0x1f95d, 0x1f962, 0x1f962, 0x1f964, 0x1f96b, 0x1f970, 0x1f979, + 0x1f980, 0x1f981, 0x1f984, 0x1f986, 0x1f992, 0x1f993, 0x1f996, 0x1f99e, + 0x1f9c0, 0x1f9c0, 0x1f9c5, 0x1f9d4, 0x1f9f0, 0x1f9f1, 0x1f9f8, 0x1f9fa, + 0x1fa00, 0x1fa03, 0x20000, 0x20005, 0x20008, 0x2000c, 0x20010, 0x20012, + 0x20018, 0x20018, 0x20020, 0x20023, 0x20030, 0x20031, 0x23801, 0x23801, + 0x23803, 0x23803, 0x23805, 0x23805, 0x23807, 0x23807, 0x23809, 0x23809, + 0x2380b, 0x2380b, 0x2380d, 0x2380d, 0x2380f, 0x2380f, 0x23811, 0x23811, + 0x23813, 0x23813, 0x23815, 0x23815, 0x23817, 0x23817, 0x23819, 0x23819, + 0x2381b, 0x2381b, 0x2381d, 0x2381d, 0x2381f, 0x23820, 0x23822, 0x23822, + 0x23824, 0x23824, 0x23826, 0x23826, 0x23828, 0x23828, 0x2382a, 0x2382a, + 0x2382c, 0x2382c, 0x2382e, 0x2382e, 0x23830, 0x23830, 0x23832, 0x23832, + 0x23834, 0x23834, 0x23836, 0x23836, 0x23838, 0x23838, 0x2383a, 0x2383a, + 0x2383c, 0x2383c, 0x2383e, 0x2383e, 0x23840, 0x23847, 0x23b00, 0x23b01, + 0x23b03, 0x23b03, 0x23b05, 0x23b0e, 0x23b10, 0x23b13, 0x23b15, 0x23b16, + 0x23b20, 0x23b20, 0x23b28, 0x23b28, 0x23b30, 0x23b30, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_gmu_registers), 8)); + +static const u32 gen7_0_0_gmugx_registers[] = { + 0x1a400, 0x1a41f, 0x1a440, 0x1a45f, 0x1a480, 0x1a49f, 0x1a4c0, 0x1a4df, + 0x1a500, 0x1a51f, 0x1a540, 0x1a55f, 0x1a580, 0x1a59f, 0x1a5c0, 0x1a5df, + 0x1a780, 0x1a781, 0x1a783, 0x1a785, 0x1a787, 0x1a789, 0x1a78b, 0x1a78d, + 0x1a78f, 0x1a791, 0x1a793, 0x1a795, 0x1a797, 0x1a799, 0x1a79b, 0x1a79b, + 0x1a7c0, 0x1a7c1, 0x1a7c4, 0x1a7c5, 0x1a7c8, 0x1a7c9, 0x1a7cc, 0x1a7cd, + 0x1a7d0, 0x1a7d1, 0x1a7d4, 0x1a7d5, 0x1a7d8, 0x1a7d9, 0x1a7fc, 0x1a7fd, + 0x1a800, 0x1a802, 0x1a804, 0x1a804, 0x1a816, 0x1a816, 0x1a81e, 0x1a81e, + 0x1a826, 0x1a826, 0x1a82e, 0x1a82e, 0x1a836, 0x1a836, 0x1a83e, 0x1a83e, + 0x1a846, 0x1a846, 0x1a860, 0x1a862, 0x1a864, 0x1a867, 0x1a870, 0x1a870, + 0x1a883, 0x1a884, 0x1a8c0, 0x1a8c2, 0x1a8c4, 0x1a8c7, 0x1a8d0, 0x1a8d3, + 0x1a900, 0x1a92b, 0x1a940, 0x1a940, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_gmugx_registers), 8)); + +static const u32 gen7_0_0_noncontext_pipe_br_registers[] = { + 0x00887, 0x0088c, 0x08600, 0x08600, 0x08602, 0x08602, 0x08610, 0x0861b, + 0x08620, 0x08620, 0x08630, 0x08630, 0x08637, 0x08639, 0x08640, 0x08640, + 0x09600, 0x09600, 0x09602, 0x09603, 0x0960a, 0x09616, 0x09624, 0x0963a, + 0x09640, 0x09640, 0x09e00, 0x09e00, 0x09e02, 0x09e07, 0x09e0a, 0x09e16, + 0x09e19, 0x09e19, 0x09e1c, 0x09e1c, 0x09e20, 0x09e25, 0x09e30, 0x09e31, + 0x09e40, 0x09e51, 0x09e64, 0x09e64, 0x09e70, 0x09e72, 0x09e78, 0x09e79, + 0x09e80, 0x09fff, 0x0a600, 0x0a600, 0x0a603, 0x0a603, 0x0a610, 0x0a61f, + 0x0a630, 0x0a631, 0x0a638, 0x0a638, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_noncontext_pipe_br_registers), 8)); + +static const u32 gen7_0_0_noncontext_pipe_bv_registers[] = { + 0x00887, 0x0088c, 0x08600, 0x08600, 0x08602, 0x08602, 0x08610, 0x0861b, + 0x08620, 0x08620, 0x08630, 0x08630, 0x08637, 0x08639, 0x08640, 0x08640, + 0x09600, 0x09600, 0x09602, 0x09603, 0x0960a, 0x09616, 0x09624, 0x0963a, + 0x09640, 0x09640, 0x09e00, 0x09e00, 0x09e02, 0x09e07, 0x09e0a, 0x09e16, + 0x09e19, 0x09e19, 0x09e1c, 0x09e1c, 0x09e20, 0x09e25, 0x09e30, 0x09e31, + 0x09e40, 0x09e51, 0x09e64, 0x09e64, 0x09e70, 0x09e72, 0x09e78, 0x09e79, + 0x09e80, 0x09fff, 0x0a600, 0x0a600, 0x0a603, 0x0a603, 0x0a610, 0x0a61f, + 0x0a630, 0x0a631, 0x0a638, 0x0a638, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_noncontext_pipe_bv_registers), 8)); + +static const u32 gen7_0_0_noncontext_pipe_lpac_registers[] = { + 0x00887, 0x0088c, 0x00f80, 0x00f80, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_noncontext_pipe_lpac_registers), 8)); + +static const u32 gen7_0_0_noncontext_rb_rac_pipe_br_registers[] = { + 0x08e10, 0x08e1c, 0x08e20, 0x08e25, 0x08e51, 0x08e5a, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_noncontext_rb_rac_pipe_br_registers), 8)); + +static const u32 gen7_0_0_noncontext_rb_rbp_pipe_br_registers[] = { + 0x08e01, 0x08e01, 0x08e04, 0x08e04, 0x08e06, 0x08e09, 0x08e0c, 0x08e0c, + 0x08e28, 0x08e28, 0x08e2c, 0x08e35, 0x08e3b, 0x08e3f, 0x08e50, 0x08e50, + 0x08e5b, 0x08e5d, 0x08e5f, 0x08e5f, 0x08e61, 0x08e61, 0x08e63, 0x08e65, + 0x08e68, 0x08e68, 0x08e70, 0x08e79, 0x08e80, 0x08e8f, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_noncontext_rb_rbp_pipe_br_registers), 8)); + +/* Block: GRAS Cluster: A7XX_CLUSTER_GRAS Pipeline: A7XX_PIPE_BR */ +static const u32 gen7_0_0_gras_cluster_gras_pipe_br_registers[] = { + 0x08000, 0x08008, 0x08010, 0x08092, 0x08094, 0x08099, 0x0809b, 0x0809d, + 0x080a0, 0x080a7, 0x080af, 0x080f1, 0x080f4, 0x080f6, 0x080f8, 0x080fa, + 0x08100, 0x08107, 0x08109, 0x0810b, 0x08110, 0x08110, 0x08120, 0x0813f, + 0x08400, 0x08406, 0x0840a, 0x0840b, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_gras_cluster_gras_pipe_br_registers), 8)); + +/* Block: GRAS Cluster: A7XX_CLUSTER_GRAS Pipeline: A7XX_PIPE_BV */ +static const u32 gen7_0_0_gras_cluster_gras_pipe_bv_registers[] = { + 0x08000, 0x08008, 0x08010, 0x08092, 0x08094, 0x08099, 0x0809b, 0x0809d, + 0x080a0, 0x080a7, 0x080af, 0x080f1, 0x080f4, 0x080f6, 0x080f8, 0x080fa, + 0x08100, 0x08107, 0x08109, 0x0810b, 0x08110, 0x08110, 0x08120, 0x0813f, + 0x08400, 0x08406, 0x0840a, 0x0840b, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_gras_cluster_gras_pipe_bv_registers), 8)); + +/* Block: PC Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BR */ +static const u32 gen7_0_0_pc_cluster_fe_pipe_br_registers[] = { + 0x09800, 0x09804, 0x09806, 0x0980a, 0x09810, 0x09811, 0x09884, 0x09886, + 0x09b00, 0x09b08, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_pc_cluster_fe_pipe_br_registers), 8)); + +/* Block: PC Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BV */ +static const u32 gen7_0_0_pc_cluster_fe_pipe_bv_registers[] = { + 0x09800, 0x09804, 0x09806, 0x0980a, 0x09810, 0x09811, 0x09884, 0x09886, + 0x09b00, 0x09b08, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_pc_cluster_fe_pipe_bv_registers), 8)); + +/* Block: RB_RAC Cluster: A7XX_CLUSTER_PS Pipeline: A7XX_PIPE_BR */ +static const u32 gen7_0_0_rb_rac_cluster_ps_pipe_br_registers[] = { + 0x08802, 0x08802, 0x08804, 0x08806, 0x08809, 0x0880a, 0x0880e, 0x08811, + 0x08818, 0x0881e, 0x08821, 0x08821, 0x08823, 0x08826, 0x08829, 0x08829, + 0x0882b, 0x0882e, 0x08831, 0x08831, 0x08833, 0x08836, 0x08839, 0x08839, + 0x0883b, 0x0883e, 0x08841, 0x08841, 0x08843, 0x08846, 0x08849, 0x08849, + 0x0884b, 0x0884e, 0x08851, 0x08851, 0x08853, 0x08856, 0x08859, 0x08859, + 0x0885b, 0x0885e, 0x08860, 0x08864, 0x08870, 0x08870, 0x08873, 0x08876, + 0x08878, 0x08879, 0x08882, 0x08885, 0x08887, 0x08889, 0x08891, 0x08891, + 0x08898, 0x08898, 0x088c0, 0x088c1, 0x088e5, 0x088e5, 0x088f4, 0x088f5, + 0x08a00, 0x08a05, 0x08a10, 0x08a15, 0x08a20, 0x08a25, 0x08a30, 0x08a35, + 0x08c00, 0x08c01, 0x08c18, 0x08c1f, 0x08c26, 0x08c34, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_rb_rac_cluster_ps_pipe_br_registers), 8)); + +/* Block: RB_RBP Cluster: A7XX_CLUSTER_PS Pipeline: A7XX_PIPE_BR */ +static const u32 gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers[] = { + 0x08800, 0x08801, 0x08803, 0x08803, 0x0880b, 0x0880d, 0x08812, 0x08812, + 0x08820, 0x08820, 0x08822, 0x08822, 0x08827, 0x08828, 0x0882a, 0x0882a, + 0x0882f, 0x08830, 0x08832, 0x08832, 0x08837, 0x08838, 0x0883a, 0x0883a, + 0x0883f, 0x08840, 0x08842, 0x08842, 0x08847, 0x08848, 0x0884a, 0x0884a, + 0x0884f, 0x08850, 0x08852, 0x08852, 0x08857, 0x08858, 0x0885a, 0x0885a, + 0x0885f, 0x0885f, 0x08865, 0x08865, 0x08871, 0x08872, 0x08877, 0x08877, + 0x08880, 0x08881, 0x08886, 0x08886, 0x08890, 0x08890, 0x088d0, 0x088e4, + 0x088e8, 0x088ea, 0x088f0, 0x088f0, 0x08900, 0x0891a, 0x08927, 0x08928, + 0x08c17, 0x08c17, 0x08c20, 0x08c25, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers), 8)); + +/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR Location: HLSQ_STATE */ +static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers[] = { + 0x0a980, 0x0a980, 0x0a982, 0x0a984, 0x0a99e, 0x0a99e, 0x0a9a7, 0x0a9a7, + 0x0a9aa, 0x0a9aa, 0x0a9ae, 0x0a9b0, 0x0a9b3, 0x0a9b5, 0x0a9ba, 0x0a9ba, + 0x0a9bc, 0x0a9bc, 0x0a9c4, 0x0a9c4, 0x0a9cd, 0x0a9cd, 0x0a9e0, 0x0a9fc, + 0x0aa00, 0x0aa00, 0x0aa30, 0x0aa31, 0x0aa40, 0x0aabf, 0x0ab00, 0x0ab03, + 0x0ab05, 0x0ab05, 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20, 0x0ab40, 0x0abbf, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers), 8)); + +/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC Location: HLSQ_STATE */ +static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers[] = { + 0x0a9b0, 0x0a9b0, 0x0a9b3, 0x0a9b5, 0x0a9ba, 0x0a9ba, 0x0a9bc, 0x0a9bc, + 0x0a9c4, 0x0a9c4, 0x0a9cd, 0x0a9cd, 0x0a9e2, 0x0a9e3, 0x0a9e6, 0x0a9fc, + 0x0aa00, 0x0aa00, 0x0aa31, 0x0aa31, 0x0ab00, 0x0ab01, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers), 8)); + +/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR Location: HLSQ_DP */ +static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers[] = { + 0x0a9b1, 0x0a9b1, 0x0a9c6, 0x0a9cb, 0x0a9d4, 0x0a9df, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers), 8)); + +/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC Location: HLSQ_DP */ +static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_dp_registers[] = { + 0x0a9b1, 0x0a9b1, 0x0a9d4, 0x0a9df, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_dp_registers), 8)); + +/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR Location: SP_TOP */ +static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers[] = { + 0x0a980, 0x0a980, 0x0a982, 0x0a984, 0x0a99e, 0x0a9a2, 0x0a9a7, 0x0a9a8, + 0x0a9aa, 0x0a9aa, 0x0a9ae, 0x0a9ae, 0x0a9b0, 0x0a9b1, 0x0a9b3, 0x0a9b5, + 0x0a9ba, 0x0a9bc, 0x0a9e0, 0x0a9f9, 0x0aa00, 0x0aa00, 0x0ab00, 0x0ab00, + 0x0ab02, 0x0ab02, 0x0ab04, 0x0ab05, 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers), 8)); + +/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC Location: SP_TOP */ +static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_sp_top_registers[] = { + 0x0a9b0, 0x0a9b1, 0x0a9b3, 0x0a9b5, 0x0a9ba, 0x0a9bc, 0x0a9e2, 0x0a9e3, + 0x0a9e6, 0x0a9f9, 0x0aa00, 0x0aa00, 0x0ab00, 0x0ab00, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_lpac_sp_top_registers), 8)); + +/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR Location: uSPTP */ +static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers[] = { + 0x0a980, 0x0a982, 0x0a985, 0x0a9a6, 0x0a9a8, 0x0a9a9, 0x0a9ab, 0x0a9ae, + 0x0a9b0, 0x0a9b3, 0x0a9b6, 0x0a9b9, 0x0a9bb, 0x0a9bf, 0x0a9c2, 0x0a9c3, + 0x0a9cd, 0x0a9cd, 0x0a9d0, 0x0a9d3, 0x0aa30, 0x0aa31, 0x0aa40, 0x0aabf, + 0x0ab00, 0x0ab05, 0x0ab21, 0x0ab22, 0x0ab40, 0x0abbf, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers), 8)); + +/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC Location: uSPTP */ +static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers[] = { + 0x0a9b0, 0x0a9b3, 0x0a9b6, 0x0a9b9, 0x0a9bb, 0x0a9be, 0x0a9c2, 0x0a9c3, + 0x0a9cd, 0x0a9cd, 0x0a9d0, 0x0a9d3, 0x0aa31, 0x0aa31, 0x0ab00, 0x0ab01, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers), 8)); + +/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BR Location: HLSQ_STATE */ +static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers[] = { + 0x0a800, 0x0a800, 0x0a81b, 0x0a81d, 0x0a822, 0x0a822, 0x0a824, 0x0a824, + 0x0a827, 0x0a82a, 0x0a830, 0x0a830, 0x0a833, 0x0a835, 0x0a83a, 0x0a83a, + 0x0a83c, 0x0a83c, 0x0a83f, 0x0a840, 0x0a85b, 0x0a85d, 0x0a862, 0x0a862, + 0x0a864, 0x0a864, 0x0a867, 0x0a867, 0x0a870, 0x0a870, 0x0a88c, 0x0a88e, + 0x0a893, 0x0a893, 0x0a895, 0x0a895, 0x0a898, 0x0a898, 0x0a89a, 0x0a89d, + 0x0a8a0, 0x0a8af, 0x0a8c0, 0x0a8c3, 0x0ab00, 0x0ab03, 0x0ab05, 0x0ab05, + 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20, 0x0ab40, 0x0abbf, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers), 8)); + +/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BV Location: HLSQ_STATE */ +static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers[] = { + 0x0a800, 0x0a800, 0x0a81b, 0x0a81d, 0x0a822, 0x0a822, 0x0a824, 0x0a824, + 0x0a827, 0x0a82a, 0x0a830, 0x0a830, 0x0a833, 0x0a835, 0x0a83a, 0x0a83a, + 0x0a83c, 0x0a83c, 0x0a83f, 0x0a840, 0x0a85b, 0x0a85d, 0x0a862, 0x0a862, + 0x0a864, 0x0a864, 0x0a867, 0x0a867, 0x0a870, 0x0a870, 0x0a88c, 0x0a88e, + 0x0a893, 0x0a893, 0x0a895, 0x0a895, 0x0a898, 0x0a898, 0x0a89a, 0x0a89d, + 0x0a8a0, 0x0a8af, 0x0a8c0, 0x0a8c3, 0x0ab00, 0x0ab02, 0x0ab0a, 0x0ab1b, + 0x0ab20, 0x0ab20, 0x0ab40, 0x0abbf, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers), 8)); + +/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BR Location: SP_TOP */ +static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_br_sp_top_registers[] = { + 0x0a800, 0x0a800, 0x0a81c, 0x0a81d, 0x0a822, 0x0a824, 0x0a830, 0x0a831, + 0x0a834, 0x0a835, 0x0a83a, 0x0a83c, 0x0a840, 0x0a840, 0x0a85c, 0x0a85d, + 0x0a862, 0x0a864, 0x0a870, 0x0a871, 0x0a88d, 0x0a88e, 0x0a893, 0x0a895, + 0x0a8a0, 0x0a8af, 0x0ab00, 0x0ab00, 0x0ab02, 0x0ab02, 0x0ab04, 0x0ab05, + 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_br_sp_top_registers), 8)); + +/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BV Location: SP_TOP */ +static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers[] = { + 0x0a800, 0x0a800, 0x0a81c, 0x0a81d, 0x0a822, 0x0a824, 0x0a830, 0x0a831, + 0x0a834, 0x0a835, 0x0a83a, 0x0a83c, 0x0a840, 0x0a840, 0x0a85c, 0x0a85d, + 0x0a862, 0x0a864, 0x0a870, 0x0a871, 0x0a88d, 0x0a88e, 0x0a893, 0x0a895, + 0x0a8a0, 0x0a8af, 0x0ab00, 0x0ab00, 0x0ab02, 0x0ab02, 0x0ab0a, 0x0ab1b, + 0x0ab20, 0x0ab20, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers), 8)); + +/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BR Location: uSPTP */ +static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_br_usptp_registers[] = { + 0x0a800, 0x0a81b, 0x0a81e, 0x0a821, 0x0a823, 0x0a827, 0x0a830, 0x0a833, + 0x0a836, 0x0a839, 0x0a83b, 0x0a85b, 0x0a85e, 0x0a861, 0x0a863, 0x0a867, + 0x0a870, 0x0a88c, 0x0a88f, 0x0a892, 0x0a894, 0x0a898, 0x0a8c0, 0x0a8c3, + 0x0ab00, 0x0ab05, 0x0ab21, 0x0ab22, 0x0ab40, 0x0abbf, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_br_usptp_registers), 8)); + +/* Block: SP Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BV Location: uSPTP */ +static const u32 gen7_0_0_sp_cluster_sp_vs_pipe_bv_usptp_registers[] = { + 0x0a800, 0x0a81b, 0x0a81e, 0x0a821, 0x0a823, 0x0a827, 0x0a830, 0x0a833, + 0x0a836, 0x0a839, 0x0a83b, 0x0a85b, 0x0a85e, 0x0a861, 0x0a863, 0x0a867, + 0x0a870, 0x0a88c, 0x0a88f, 0x0a892, 0x0a894, 0x0a898, 0x0a8c0, 0x0a8c3, + 0x0ab00, 0x0ab02, 0x0ab21, 0x0ab22, 0x0ab40, 0x0abbf, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_vs_pipe_bv_usptp_registers), 8)); + +/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BR */ +static const u32 gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers[] = { + 0x0b180, 0x0b183, 0x0b190, 0x0b195, 0x0b2c0, 0x0b2d5, 0x0b300, 0x0b307, + 0x0b309, 0x0b309, 0x0b310, 0x0b310, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers), 8)); + +/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BV Location: HLSQ_STATE */ +static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_bv_hlsq_state_registers[] = { + 0x0ab00, 0x0ab02, 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20, 0x0ab40, 0x0abbf, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_bv_hlsq_state_registers), 8)); + +/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BV Location: SP_TOP */ +static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_bv_sp_top_registers[] = { + 0x0ab00, 0x0ab00, 0x0ab02, 0x0ab02, 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_bv_sp_top_registers), 8)); + +/* Block: SP Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BV Location: uSPTP */ +static const u32 gen7_0_0_sp_cluster_sp_ps_pipe_bv_usptp_registers[] = { + 0x0ab00, 0x0ab02, 0x0ab21, 0x0ab22, 0x0ab40, 0x0abbf, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_cluster_sp_ps_pipe_bv_usptp_registers), 8)); + +/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_BV */ +static const u32 gen7_0_0_tpl1_cluster_sp_ps_pipe_bv_registers[] = { + 0x0b300, 0x0b307, 0x0b309, 0x0b309, 0x0b310, 0x0b310, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_cluster_sp_ps_pipe_bv_registers), 8)); + +/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_PS Pipeline: A7XX_PIPE_LPAC */ +static const u32 gen7_0_0_tpl1_cluster_sp_ps_pipe_lpac_registers[] = { + 0x0b180, 0x0b181, 0x0b300, 0x0b301, 0x0b307, 0x0b307, 0x0b309, 0x0b309, + 0x0b310, 0x0b310, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_cluster_sp_ps_pipe_lpac_registers), 8)); + +/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BR */ +static const u32 gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers[] = { + 0x0b300, 0x0b307, 0x0b309, 0x0b309, 0x0b310, 0x0b310, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers), 8)); + +/* Block: TPL1 Cluster: A7XX_CLUSTER_SP_VS Pipeline: A7XX_PIPE_BV */ +static const u32 gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers[] = { + 0x0b300, 0x0b307, 0x0b309, 0x0b309, 0x0b310, 0x0b310, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers), 8)); + +/* Block: VFD Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BR */ +static const u32 gen7_0_0_vfd_cluster_fe_pipe_br_registers[] = { + 0x0a000, 0x0a009, 0x0a00e, 0x0a0ef, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_vfd_cluster_fe_pipe_br_registers), 8)); + +/* Block: VFD Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BV */ +static const u32 gen7_0_0_vfd_cluster_fe_pipe_bv_registers[] = { + 0x0a000, 0x0a009, 0x0a00e, 0x0a0ef, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_vfd_cluster_fe_pipe_bv_registers), 8)); + +/* Block: VPC Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BR */ +static const u32 gen7_0_0_vpc_cluster_fe_pipe_br_registers[] = { + 0x09300, 0x09307, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_fe_pipe_br_registers), 8)); + +/* Block: VPC Cluster: A7XX_CLUSTER_FE Pipeline: A7XX_PIPE_BV */ +static const u32 gen7_0_0_vpc_cluster_fe_pipe_bv_registers[] = { + 0x09300, 0x09307, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_fe_pipe_bv_registers), 8)); + +/* Block: VPC Cluster: A7XX_CLUSTER_PC_VS Pipeline: A7XX_PIPE_BR */ +static const u32 gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers[] = { + 0x09101, 0x0910c, 0x09300, 0x09307, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers), 8)); + +/* Block: VPC Cluster: A7XX_CLUSTER_PC_VS Pipeline: A7XX_PIPE_BV */ +static const u32 gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers[] = { + 0x09101, 0x0910c, 0x09300, 0x09307, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers), 8)); + +/* Block: VPC Cluster: A7XX_CLUSTER_VPC_PS Pipeline: A7XX_PIPE_BR */ +static const u32 gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers[] = { + 0x09200, 0x0920f, 0x09212, 0x09216, 0x09218, 0x09236, 0x09300, 0x09307, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers), 8)); + +/* Block: VPC Cluster: A7XX_CLUSTER_VPC_PS Pipeline: A7XX_PIPE_BV */ +static const u32 gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers[] = { + 0x09200, 0x0920f, 0x09212, 0x09216, 0x09218, 0x09236, 0x09300, 0x09307, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers), 8)); + +/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_BR Location: HLSQ_STATE */ +static const u32 gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers[] = { + 0x0ae52, 0x0ae52, 0x0ae60, 0x0ae67, 0x0ae69, 0x0ae73, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers), 8)); + +/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_BR Location: SP_TOP */ +static const u32 gen7_0_0_sp_noncontext_pipe_br_sp_top_registers[] = { + 0x0ae00, 0x0ae00, 0x0ae02, 0x0ae04, 0x0ae06, 0x0ae09, 0x0ae0c, 0x0ae0c, + 0x0ae0f, 0x0ae0f, 0x0ae28, 0x0ae2b, 0x0ae35, 0x0ae35, 0x0ae3a, 0x0ae3f, + 0x0ae50, 0x0ae52, 0x0ae80, 0x0aea3, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_br_sp_top_registers), 8)); + +/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_BR Location: uSPTP */ +static const u32 gen7_0_0_sp_noncontext_pipe_br_usptp_registers[] = { + 0x0ae00, 0x0ae00, 0x0ae02, 0x0ae04, 0x0ae06, 0x0ae09, 0x0ae0c, 0x0ae0c, + 0x0ae0f, 0x0ae0f, 0x0ae30, 0x0ae32, 0x0ae35, 0x0ae35, 0x0ae3a, 0x0ae3b, + 0x0ae3e, 0x0ae3f, 0x0ae50, 0x0ae52, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_br_usptp_registers), 8)); + +/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_LPAC Location: HLSQ_STATE */ +static const u32 gen7_0_0_sp_noncontext_pipe_lpac_hlsq_state_registers[] = { + 0x0af88, 0x0af8a, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_lpac_hlsq_state_registers), 8)); + +/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_LPAC Location: SP_TOP */ +static const u32 gen7_0_0_sp_noncontext_pipe_lpac_sp_top_registers[] = { + 0x0af80, 0x0af84, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_lpac_sp_top_registers), 8)); + +/* Block: SP Cluster: noncontext Pipeline: A7XX_PIPE_LPAC Location: uSPTP */ +static const u32 gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers[] = { + 0x0af80, 0x0af84, 0x0af90, 0x0af92, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers), 8)); + +/* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_BR */ +static const u32 gen7_0_0_tpl1_noncontext_pipe_br_registers[] = { + 0x0b600, 0x0b600, 0x0b602, 0x0b602, 0x0b604, 0x0b604, 0x0b608, 0x0b60c, + 0x0b60f, 0x0b621, 0x0b630, 0x0b633, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_noncontext_pipe_br_registers), 8)); + +/* Block: TPl1 Cluster: noncontext Pipeline: A7XX_PIPE_LPAC */ +static const u32 gen7_0_0_tpl1_noncontext_pipe_lpac_registers[] = { + 0x0b780, 0x0b780, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_tpl1_noncontext_pipe_lpac_registers), 8)); + +static const struct gen7_sel_reg gen7_0_0_rb_rac_sel = { + .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, + .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, + .val = 0x0, +}; + +static const struct gen7_sel_reg gen7_0_0_rb_rbp_sel = { + .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, + .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, + .val = 0x9, +}; + +static struct gen7_cluster_registers gen7_0_0_clusters[] = { + { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT, + gen7_0_0_noncontext_pipe_br_registers, }, + { A7XX_CLUSTER_NONE, A7XX_PIPE_BV, STATE_NON_CONTEXT, + gen7_0_0_noncontext_pipe_bv_registers, }, + { A7XX_CLUSTER_NONE, A7XX_PIPE_LPAC, STATE_NON_CONTEXT, + gen7_0_0_noncontext_pipe_lpac_registers, }, + { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT, + gen7_0_0_noncontext_rb_rac_pipe_br_registers, &gen7_0_0_rb_rac_sel, }, + { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT, + gen7_0_0_noncontext_rb_rbp_pipe_br_registers, &gen7_0_0_rb_rbp_sel, }, + { A7XX_CLUSTER_GRAS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + gen7_0_0_gras_cluster_gras_pipe_br_registers, }, + { A7XX_CLUSTER_GRAS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + gen7_0_0_gras_cluster_gras_pipe_bv_registers, }, + { A7XX_CLUSTER_GRAS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + gen7_0_0_gras_cluster_gras_pipe_br_registers, }, + { A7XX_CLUSTER_GRAS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + gen7_0_0_gras_cluster_gras_pipe_bv_registers, }, + { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + gen7_0_0_pc_cluster_fe_pipe_br_registers, }, + { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + gen7_0_0_pc_cluster_fe_pipe_bv_registers, }, + { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + gen7_0_0_pc_cluster_fe_pipe_br_registers, }, + { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + gen7_0_0_pc_cluster_fe_pipe_bv_registers, }, + { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + gen7_0_0_rb_rac_cluster_ps_pipe_br_registers, &gen7_0_0_rb_rac_sel, }, + { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + gen7_0_0_rb_rac_cluster_ps_pipe_br_registers, &gen7_0_0_rb_rac_sel, }, + { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers, &gen7_0_0_rb_rbp_sel, }, + { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers, &gen7_0_0_rb_rbp_sel, }, + { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + gen7_0_0_vfd_cluster_fe_pipe_br_registers, }, + { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + gen7_0_0_vfd_cluster_fe_pipe_bv_registers, }, + { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + gen7_0_0_vfd_cluster_fe_pipe_br_registers, }, + { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + gen7_0_0_vfd_cluster_fe_pipe_bv_registers, }, + { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + gen7_0_0_vpc_cluster_fe_pipe_br_registers, }, + { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + gen7_0_0_vpc_cluster_fe_pipe_bv_registers, }, + { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + gen7_0_0_vpc_cluster_fe_pipe_br_registers, }, + { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + gen7_0_0_vpc_cluster_fe_pipe_bv_registers, }, + { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers, }, + { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers, }, + { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers, }, + { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers, }, + { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers, }, + { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, }, + { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers, }, + { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, }, +}; + +static struct gen7_sptp_cluster_registers gen7_0_0_sptp_clusters[] = { + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE, + gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers, 0xae00 }, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP, + gen7_0_0_sp_noncontext_pipe_br_sp_top_registers, 0xae00 }, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP, + gen7_0_0_sp_noncontext_pipe_br_usptp_registers, 0xae00 }, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_STATE, + gen7_0_0_sp_noncontext_pipe_lpac_hlsq_state_registers, 0xaf80 }, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_SP_TOP, + gen7_0_0_sp_noncontext_pipe_lpac_sp_top_registers, 0xaf80 }, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP, + gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers, 0xaf80 }, + { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP, + gen7_0_0_tpl1_noncontext_pipe_br_registers, 0xb600 }, + { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP, + gen7_0_0_tpl1_noncontext_pipe_lpac_registers, 0xb780 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE, + gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_DP, + gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP, + gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP, + gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_STATE, + gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_DP, + gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_SP_TOP, + gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP, + gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_HLSQ_STATE, + gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_HLSQ_DP, + gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_SP_TOP, + gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_USPTP, + gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_HLSQ_STATE, + gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_HLSQ_DP, + gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_SP_TOP, + gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_USPTP, + gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_STATE, + gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_DP, + gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_dp_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_SP_TOP, + gen7_0_0_sp_cluster_sp_ps_pipe_lpac_sp_top_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP, + gen7_0_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers, 0xa800 }, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE, + gen7_0_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers, 0xa800 }, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_HLSQ_STATE, + gen7_0_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers, 0xa800 }, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP, + gen7_0_0_sp_cluster_sp_vs_pipe_br_sp_top_registers, 0xa800 }, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_SP_TOP, + gen7_0_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers, 0xa800 }, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP, + gen7_0_0_sp_cluster_sp_vs_pipe_br_usptp_registers, 0xa800 }, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_USPTP, + gen7_0_0_sp_cluster_sp_vs_pipe_bv_usptp_registers, 0xa800 }, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_STATE, + gen7_0_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers, 0xa800 }, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_HLSQ_STATE, + gen7_0_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers, 0xa800 }, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_SP_TOP, + gen7_0_0_sp_cluster_sp_vs_pipe_br_sp_top_registers, 0xa800 }, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_SP_TOP, + gen7_0_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers, 0xa800 }, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP, + gen7_0_0_sp_cluster_sp_vs_pipe_br_usptp_registers, 0xa800 }, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_USPTP, + gen7_0_0_sp_cluster_sp_vs_pipe_bv_usptp_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP, + gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 }, + { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP, + gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 }, + { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_USPTP, + gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 }, + { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_USPTP, + gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 }, + { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP, + gen7_0_0_tpl1_cluster_sp_ps_pipe_lpac_registers, 0xb000 }, + { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP, + gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers, 0xb000 }, + { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_USPTP, + gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers, 0xb000 }, + { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP, + gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers, 0xb000 }, + { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_USPTP, + gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers, 0xb000 }, +}; + +static const u32 gen7_0_0_rscc_registers[] = { + 0x14000, 0x14036, 0x14040, 0x14042, 0x14080, 0x14084, 0x14089, 0x1408c, + 0x14091, 0x14094, 0x14099, 0x1409c, 0x140a1, 0x140a4, 0x140a9, 0x140ac, + 0x14100, 0x14102, 0x14114, 0x14119, 0x14124, 0x1412e, 0x14140, 0x14143, + 0x14180, 0x14197, 0x14340, 0x14342, 0x14344, 0x14347, 0x1434c, 0x14373, + 0x143ec, 0x143ef, 0x143f4, 0x1441b, 0x14494, 0x14497, 0x1449c, 0x144c3, + 0x1453c, 0x1453f, 0x14544, 0x1456b, 0x145e4, 0x145e7, 0x145ec, 0x14613, + 0x1468c, 0x1468f, 0x14694, 0x146bb, 0x14734, 0x14737, 0x1473c, 0x14763, + 0x147dc, 0x147df, 0x147e4, 0x1480b, 0x14884, 0x14887, 0x1488c, 0x148b3, + 0x1492c, 0x1492f, 0x14934, 0x1495b, 0x14f51, 0x14f54, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_rscc_registers), 8)); + +static const u32 gen7_0_0_cpr_registers[] = { + 0x26800, 0x26805, 0x26808, 0x2680c, 0x26814, 0x26814, 0x2681c, 0x2681c, + 0x26820, 0x26838, 0x26840, 0x26840, 0x26848, 0x26848, 0x26850, 0x26850, + 0x26880, 0x26898, 0x26980, 0x269b0, 0x269c0, 0x269c8, 0x269e0, 0x269ee, + 0x269fb, 0x269ff, 0x26a02, 0x26a07, 0x26a09, 0x26a0b, 0x26a10, 0x26b0f, + 0x27440, 0x27441, 0x27444, 0x27444, 0x27480, 0x274a2, 0x274ac, 0x274ac, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_cpr_registers), 8)); + +static const u32 gen7_0_0_gpucc_registers[] = { + 0x24000, 0x2400e, 0x24400, 0x2440e, 0x24800, 0x24805, 0x24c00, 0x24cff, + 0x25800, 0x25804, 0x25c00, 0x25c04, 0x26000, 0x26004, 0x26400, 0x26405, + 0x26414, 0x2641d, 0x2642a, 0x26430, 0x26432, 0x26432, 0x26441, 0x26455, + 0x26466, 0x26468, 0x26478, 0x2647a, 0x26489, 0x2648a, 0x2649c, 0x2649e, + 0x264a0, 0x264a3, 0x264b3, 0x264b5, 0x264c5, 0x264c7, 0x264d6, 0x264d8, + 0x264e8, 0x264e9, 0x264f9, 0x264fc, 0x2650b, 0x2650c, 0x2651c, 0x2651e, + 0x26540, 0x26570, 0x26600, 0x26616, 0x26620, 0x2662d, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_gpucc_registers), 8)); + +static const u32 gen7_0_0_cx_misc_registers[] = { + 0x27800, 0x27800, 0x27810, 0x27814, 0x27820, 0x27824, 0x27832, 0x27857, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_cx_misc_registers), 8)); + +static const u32 gen7_0_0_dpm_registers[] = { + 0x1aa00, 0x1aa06, 0x1aa09, 0x1aa0a, 0x1aa0c, 0x1aa0d, 0x1aa0f, 0x1aa12, + 0x1aa14, 0x1aa47, 0x1aa50, 0x1aa51, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_0_0_dpm_registers), 8)); + +static struct gen7_reg_list gen7_0_0_reg_list[] = { + { gen7_0_0_gpu_registers, NULL }, + { gen7_0_0_cx_misc_registers, NULL }, + { gen7_0_0_dpm_registers, NULL }, + { NULL, NULL }, +}; + +static const u32 *gen7_0_0_external_core_regs[] = { + gen7_0_0_gpucc_registers, + gen7_0_0_cpr_registers, +}; +#endif /*_ADRENO_GEN7_0_0_SNAPSHOT_H */ diff --git a/drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h b/drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h new file mode 100644 index 000000000000..6f8ad50f32ce --- /dev/null +++ b/drivers/gpu/drm/msm/adreno/adreno_gen7_2_0_snapshot.h @@ -0,0 +1,753 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. + * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved. + */ +#ifndef __ADRENO_GEN7_2_0_SNAPSHOT_H +#define __ADRENO_GEN7_2_0_SNAPSHOT_H + +#include "a6xx_gpu_state.h" + +static const u32 gen7_2_0_debugbus_blocks[] = { + A7XX_DBGBUS_CP_0_0, + A7XX_DBGBUS_CP_0_1, + A7XX_DBGBUS_RBBM, + A7XX_DBGBUS_HLSQ, + A7XX_DBGBUS_UCHE_0, + A7XX_DBGBUS_UCHE_1, + A7XX_DBGBUS_TESS_BR, + A7XX_DBGBUS_TESS_BV, + A7XX_DBGBUS_PC_BR, + A7XX_DBGBUS_PC_BV, + A7XX_DBGBUS_VFDP_BR, + A7XX_DBGBUS_VFDP_BV, + A7XX_DBGBUS_VPC_BR, + A7XX_DBGBUS_VPC_BV, + A7XX_DBGBUS_TSE_BR, + A7XX_DBGBUS_TSE_BV, + A7XX_DBGBUS_RAS_BR, + A7XX_DBGBUS_RAS_BV, + A7XX_DBGBUS_VSC, + A7XX_DBGBUS_COM_0, + A7XX_DBGBUS_LRZ_BR, + A7XX_DBGBUS_LRZ_BV, + A7XX_DBGBUS_UFC_0, + A7XX_DBGBUS_UFC_1, + A7XX_DBGBUS_GMU_GX, + A7XX_DBGBUS_DBGC, + A7XX_DBGBUS_GPC_BR, + A7XX_DBGBUS_GPC_BV, + A7XX_DBGBUS_LARC, + A7XX_DBGBUS_HLSQ_SPTP, + A7XX_DBGBUS_RB_0, + A7XX_DBGBUS_RB_1, + A7XX_DBGBUS_RB_2, + A7XX_DBGBUS_RB_3, + A7XX_DBGBUS_RB_4, + A7XX_DBGBUS_RB_5, + A7XX_DBGBUS_UCHE_WRAPPER, + A7XX_DBGBUS_CCU_0, + A7XX_DBGBUS_CCU_1, + A7XX_DBGBUS_CCU_2, + A7XX_DBGBUS_CCU_3, + A7XX_DBGBUS_CCU_4, + A7XX_DBGBUS_CCU_5, + A7XX_DBGBUS_VFD_BR_0, + A7XX_DBGBUS_VFD_BR_1, + A7XX_DBGBUS_VFD_BR_2, + A7XX_DBGBUS_VFD_BR_3, + A7XX_DBGBUS_VFD_BR_4, + A7XX_DBGBUS_VFD_BR_5, + A7XX_DBGBUS_VFD_BV_0, + A7XX_DBGBUS_VFD_BV_1, + A7XX_DBGBUS_USP_0, + A7XX_DBGBUS_USP_1, + A7XX_DBGBUS_USP_2, + A7XX_DBGBUS_USP_3, + A7XX_DBGBUS_USP_4, + A7XX_DBGBUS_USP_5, + A7XX_DBGBUS_TP_0, + A7XX_DBGBUS_TP_1, + A7XX_DBGBUS_TP_2, + A7XX_DBGBUS_TP_3, + A7XX_DBGBUS_TP_4, + A7XX_DBGBUS_TP_5, + A7XX_DBGBUS_TP_6, + A7XX_DBGBUS_TP_7, + A7XX_DBGBUS_TP_8, + A7XX_DBGBUS_TP_9, + A7XX_DBGBUS_TP_10, + A7XX_DBGBUS_TP_11, + A7XX_DBGBUS_USPTP_0, + A7XX_DBGBUS_USPTP_1, + A7XX_DBGBUS_USPTP_2, + A7XX_DBGBUS_USPTP_3, + A7XX_DBGBUS_USPTP_4, + A7XX_DBGBUS_USPTP_5, + A7XX_DBGBUS_USPTP_6, + A7XX_DBGBUS_USPTP_7, + A7XX_DBGBUS_USPTP_8, + A7XX_DBGBUS_USPTP_9, + A7XX_DBGBUS_USPTP_10, + A7XX_DBGBUS_USPTP_11, + A7XX_DBGBUS_CCHE_0, + A7XX_DBGBUS_CCHE_1, + A7XX_DBGBUS_CCHE_2, +}; + +static struct gen7_shader_block gen7_2_0_shader_blocks[] = { + {A7XX_TP0_TMO_DATA, 0x200, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_TP0_SMO_DATA, 0x80, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_TP0_MIPMAP_BASE_DATA, 0x3c0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_INST_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_INST_DATA_1, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_0_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_1_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_2_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_3_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_4_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_5_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_6_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_7_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_CB_RAM, 0x390, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_13_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_14_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_INST_TAG, 0xc0, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_INST_DATA_2, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_TMO_TAG, 0x80, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_SMO_TAG, 0x80, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_STATE_DATA, 0x40, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_HWAVE_RAM, 0x100, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_L0_INST_BUF, 0x50, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_8_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_9_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_10_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_11_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_SP_LB_12_DATA, 0x800, 6, 2, A7XX_PIPE_BR, A7XX_USPTP}, + {A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CHUNK_CVS_RAM, 0x1c0, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CHUNK_CPS_RAM, 0x300, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CHUNK_CPS_RAM, 0x180, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x40, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x10, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CVS_MISC_RAM, 0x280, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CVS_MISC_RAM, 0x280, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CPS_MISC_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CPS_MISC_RAM, 0x200, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CPS_MISC_RAM_1, 0x1c0, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_INST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_INST_RAM, 0x800, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_INST_RAM, 0x200, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_INST_RAM_TAG, 0x80, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x38, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x64, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x10, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x800, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_INST_RAM_1, 0x800, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_STPROC_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_BV_BE_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_BV_BE_META, 0x10, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_DATAPATH_META, 0x20, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_FRONTEND_META, 0x80, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_FRONTEND_META, 0x80, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_FRONTEND_META, 0x80, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_INDIRECT_META, 0x10, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_BR, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_BV, A7XX_HLSQ_STATE}, + {A7XX_HLSQ_BACKEND_META, 0x40, 1, 1, A7XX_PIPE_LPAC, A7XX_HLSQ_STATE}, +}; + +static const u32 gen7_2_0_gpu_registers[] = { + 0x00000, 0x00000, 0x00002, 0x00002, 0x00011, 0x00012, 0x00016, 0x0001b, + 0x0001f, 0x00032, 0x00038, 0x0003c, 0x00042, 0x00042, 0x00044, 0x00044, + 0x00047, 0x00047, 0x00049, 0x0004a, 0x0004c, 0x0004c, 0x00050, 0x00050, + 0x00056, 0x00056, 0x00073, 0x0007d, 0x000ad, 0x000ae, 0x000b0, 0x000b0, + 0x000b4, 0x000b4, 0x000b8, 0x000b8, 0x000bc, 0x000bc, 0x000c0, 0x000c0, + 0x000c4, 0x000c4, 0x000c8, 0x000c8, 0x000cc, 0x000cc, 0x000d0, 0x000d0, + 0x000d4, 0x000d4, 0x000d8, 0x000d8, 0x000dc, 0x000dc, 0x000e0, 0x000e0, + 0x000e4, 0x000e4, 0x000e8, 0x000e8, 0x000ec, 0x000ec, 0x000f0, 0x000f0, + 0x000f4, 0x000f4, 0x000f8, 0x000f8, 0x00100, 0x00100, 0x00104, 0x0010c, + 0x0010f, 0x0011d, 0x0012f, 0x0012f, 0x00200, 0x0020d, 0x00211, 0x00211, + 0x00215, 0x00253, 0x00260, 0x00270, 0x00272, 0x00274, 0x00281, 0x0028d, + 0x00300, 0x00401, 0x00410, 0x00451, 0x00460, 0x004a3, 0x004c0, 0x004d1, + 0x00500, 0x00500, 0x00507, 0x0050b, 0x0050f, 0x0050f, 0x00511, 0x00511, + 0x00533, 0x00536, 0x00540, 0x00555, 0x00564, 0x00567, 0x00574, 0x00577, + 0x00584, 0x0059b, 0x005fb, 0x005ff, 0x00800, 0x00808, 0x00810, 0x00813, + 0x00820, 0x00821, 0x00823, 0x00827, 0x00830, 0x00834, 0x0083f, 0x00841, + 0x00843, 0x00847, 0x0084f, 0x00886, 0x008a0, 0x008ab, 0x008c0, 0x008c0, + 0x008c4, 0x008c6, 0x008d0, 0x008dd, 0x008e0, 0x008e6, 0x008f0, 0x008f3, + 0x00900, 0x00903, 0x00908, 0x00911, 0x00928, 0x0093e, 0x00942, 0x0094d, + 0x00980, 0x00984, 0x0098d, 0x0098f, 0x009b0, 0x009b4, 0x009c2, 0x009c9, + 0x009ce, 0x009d7, 0x009e0, 0x009e7, 0x00a00, 0x00a00, 0x00a02, 0x00a03, + 0x00a10, 0x00a4f, 0x00a61, 0x00a9f, 0x00ad0, 0x00adb, 0x00b00, 0x00b31, + 0x00b35, 0x00b3c, 0x00b40, 0x00b40, 0x00c00, 0x00c00, 0x00c02, 0x00c04, + 0x00c06, 0x00c06, 0x00c10, 0x00cd9, 0x00ce0, 0x00d0c, 0x00df0, 0x00df4, + 0x00e01, 0x00e02, 0x00e07, 0x00e0e, 0x00e10, 0x00e13, 0x00e17, 0x00e19, + 0x00e1b, 0x00e2b, 0x00e30, 0x00e32, 0x00e38, 0x00e3c, 0x00e40, 0x00e4b, + 0x0ec00, 0x0ec01, 0x0ec05, 0x0ec05, 0x0ec07, 0x0ec07, 0x0ec0a, 0x0ec0a, + 0x0ec12, 0x0ec12, 0x0ec26, 0x0ec28, 0x0ec2b, 0x0ec2d, 0x0ec2f, 0x0ec2f, + 0x0ec40, 0x0ec41, 0x0ec45, 0x0ec45, 0x0ec47, 0x0ec47, 0x0ec4a, 0x0ec4a, + 0x0ec52, 0x0ec52, 0x0ec66, 0x0ec68, 0x0ec6b, 0x0ec6d, 0x0ec6f, 0x0ec6f, + 0x0ec80, 0x0ec81, 0x0ec85, 0x0ec85, 0x0ec87, 0x0ec87, 0x0ec8a, 0x0ec8a, + 0x0ec92, 0x0ec92, 0x0eca6, 0x0eca8, 0x0ecab, 0x0ecad, 0x0ecaf, 0x0ecaf, + 0x0ecc0, 0x0ecc1, 0x0ecc5, 0x0ecc5, 0x0ecc7, 0x0ecc7, 0x0ecca, 0x0ecca, + 0x0ecd2, 0x0ecd2, 0x0ece6, 0x0ece8, 0x0eceb, 0x0eced, 0x0ecef, 0x0ecef, + 0x0ed00, 0x0ed01, 0x0ed05, 0x0ed05, 0x0ed07, 0x0ed07, 0x0ed0a, 0x0ed0a, + 0x0ed12, 0x0ed12, 0x0ed26, 0x0ed28, 0x0ed2b, 0x0ed2d, 0x0ed2f, 0x0ed2f, + 0x0ed40, 0x0ed41, 0x0ed45, 0x0ed45, 0x0ed47, 0x0ed47, 0x0ed4a, 0x0ed4a, + 0x0ed52, 0x0ed52, 0x0ed66, 0x0ed68, 0x0ed6b, 0x0ed6d, 0x0ed6f, 0x0ed6f, + 0x0ed80, 0x0ed81, 0x0ed85, 0x0ed85, 0x0ed87, 0x0ed87, 0x0ed8a, 0x0ed8a, + 0x0ed92, 0x0ed92, 0x0eda6, 0x0eda8, 0x0edab, 0x0edad, 0x0edaf, 0x0edaf, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_gpu_registers), 8)); + +static const u32 gen7_2_0_gmu_registers[] = { + 0x10001, 0x10001, 0x10003, 0x10003, 0x10401, 0x10401, 0x10403, 0x10403, + 0x10801, 0x10801, 0x10803, 0x10803, 0x10c01, 0x10c01, 0x10c03, 0x10c03, + 0x11001, 0x11001, 0x11003, 0x11003, 0x11401, 0x11401, 0x11403, 0x11403, + 0x11801, 0x11801, 0x11803, 0x11803, 0x11c01, 0x11c01, 0x11c03, 0x11c03, + 0x1a79b, 0x1a79b, 0x1a7ac, 0x1a7b9, 0x1a7dc, 0x1a7dd, 0x1a7e0, 0x1a7e1, + 0x1a803, 0x1a803, 0x1a805, 0x1a806, 0x1a84e, 0x1a84e, 0x1a856, 0x1a856, + 0x1f400, 0x1f40d, 0x1f40f, 0x1f411, 0x1f500, 0x1f500, 0x1f507, 0x1f507, + 0x1f509, 0x1f50b, 0x1f700, 0x1f701, 0x1f704, 0x1f706, 0x1f708, 0x1f709, + 0x1f70c, 0x1f70d, 0x1f710, 0x1f711, 0x1f713, 0x1f716, 0x1f720, 0x1f724, + 0x1f729, 0x1f729, 0x1f730, 0x1f747, 0x1f760, 0x1f761, 0x1f764, 0x1f76b, + 0x1f800, 0x1f804, 0x1f807, 0x1f808, 0x1f80b, 0x1f80c, 0x1f80f, 0x1f80f, + 0x1f811, 0x1f811, 0x1f813, 0x1f817, 0x1f819, 0x1f81c, 0x1f824, 0x1f82a, + 0x1f82d, 0x1f830, 0x1f840, 0x1f853, 0x1f860, 0x1f860, 0x1f862, 0x1f864, + 0x1f868, 0x1f868, 0x1f870, 0x1f879, 0x1f87f, 0x1f87f, 0x1f888, 0x1f889, + 0x1f8a0, 0x1f8a2, 0x1f890, 0x1f892, 0x1f894, 0x1f896, 0x1f8a4, 0x1f8af, + 0x1f8b8, 0x1f8b9, 0x1f8c0, 0x1f8c1, 0x1f8c3, 0x1f8c4, 0x1f8d0, 0x1f8d0, + 0x1f8ec, 0x1f8ec, 0x1f8f0, 0x1f8f1, 0x1f910, 0x1f917, 0x1f920, 0x1f921, + 0x1f924, 0x1f925, 0x1f928, 0x1f929, 0x1f92c, 0x1f92d, 0x1f940, 0x1f940, + 0x1f942, 0x1f944, 0x1f948, 0x1f94a, 0x1f94f, 0x1f951, 0x1f954, 0x1f955, + 0x1f958, 0x1f95a, 0x1f95d, 0x1f95d, 0x1f962, 0x1f96b, 0x1f970, 0x1f979, + 0x1f97c, 0x1f97c, 0x1f980, 0x1f981, 0x1f984, 0x1f986, 0x1f992, 0x1f993, + 0x1f996, 0x1f99e, 0x1f9c0, 0x1f9c0, 0x1f9c5, 0x1f9d4, 0x1f9f0, 0x1f9f1, + 0x1f9f8, 0x1f9fa, 0x1f9fc, 0x1f9fc, 0x1fa00, 0x1fa03, 0x20000, 0x20012, + 0x20018, 0x20018, 0x2001a, 0x2001a, 0x20020, 0x20024, 0x20030, 0x20031, + 0x20034, 0x20036, 0x23801, 0x23801, 0x23803, 0x23803, 0x23805, 0x23805, + 0x23807, 0x23807, 0x23809, 0x23809, 0x2380b, 0x2380b, 0x2380d, 0x2380d, + 0x2380f, 0x2380f, 0x23811, 0x23811, 0x23813, 0x23813, 0x23815, 0x23815, + 0x23817, 0x23817, 0x23819, 0x23819, 0x2381b, 0x2381b, 0x2381d, 0x2381d, + 0x2381f, 0x23820, 0x23822, 0x23822, 0x23824, 0x23824, 0x23826, 0x23826, + 0x23828, 0x23828, 0x2382a, 0x2382a, 0x2382c, 0x2382c, 0x2382e, 0x2382e, + 0x23830, 0x23830, 0x23832, 0x23832, 0x23834, 0x23834, 0x23836, 0x23836, + 0x23838, 0x23838, 0x2383a, 0x2383a, 0x2383c, 0x2383c, 0x2383e, 0x2383e, + 0x23840, 0x23847, 0x23b00, 0x23b01, 0x23b03, 0x23b03, 0x23b05, 0x23b0e, + 0x23b10, 0x23b13, 0x23b15, 0x23b16, 0x23b20, 0x23b20, 0x23b28, 0x23b28, + 0x23b30, 0x23b30, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_gmu_registers), 8)); + +static const u32 gen7_2_0_gmugx_registers[] = { + 0x1a400, 0x1a41f, 0x1a440, 0x1a45f, 0x1a480, 0x1a49f, 0x1a4c0, 0x1a4df, + 0x1a500, 0x1a51f, 0x1a540, 0x1a55f, 0x1a580, 0x1a59f, 0x1a5c0, 0x1a5df, + 0x1a600, 0x1a61f, 0x1a640, 0x1a65f, 0x1a780, 0x1a781, 0x1a783, 0x1a785, + 0x1a787, 0x1a789, 0x1a78b, 0x1a78d, 0x1a78f, 0x1a791, 0x1a793, 0x1a795, + 0x1a797, 0x1a799, 0x1a79c, 0x1a79d, 0x1a79f, 0x1a79f, 0x1a7a0, 0x1a7a1, + 0x1a7a3, 0x1a7a3, 0x1a7a8, 0x1a7ab, 0x1a7c0, 0x1a7c1, 0x1a7c4, 0x1a7c5, + 0x1a7c8, 0x1a7c9, 0x1a7cc, 0x1a7cd, 0x1a7d0, 0x1a7d1, 0x1a7d4, 0x1a7d5, + 0x1a7d8, 0x1a7d9, 0x1a7fc, 0x1a7fd, 0x1a800, 0x1a802, 0x1a804, 0x1a804, + 0x1a816, 0x1a816, 0x1a81e, 0x1a81e, 0x1a826, 0x1a826, 0x1a82e, 0x1a82e, + 0x1a836, 0x1a836, 0x1a83e, 0x1a83e, 0x1a846, 0x1a846, 0x1a860, 0x1a862, + 0x1a864, 0x1a867, 0x1a870, 0x1a870, 0x1a883, 0x1a884, 0x1a8c0, 0x1a8c2, + 0x1a8c4, 0x1a8c7, 0x1a8d0, 0x1a8d3, 0x1a900, 0x1a92b, 0x1a940, 0x1a940, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_gmugx_registers), 8)); + +static const u32 gen7_2_0_noncontext_pipe_br_registers[] = { + 0x00887, 0x0088c, 0x08600, 0x08600, 0x08602, 0x08602, 0x08610, 0x0861b, + 0x08620, 0x08620, 0x08630, 0x08630, 0x08637, 0x08639, 0x08640, 0x08640, + 0x09600, 0x09600, 0x09602, 0x09603, 0x0960a, 0x09616, 0x09624, 0x0963a, + 0x09640, 0x09640, 0x09e00, 0x09e00, 0x09e02, 0x09e07, 0x09e0a, 0x09e16, + 0x09e19, 0x09e19, 0x09e1c, 0x09e1c, 0x09e20, 0x09e25, 0x09e30, 0x09e31, + 0x09e40, 0x09e51, 0x09e64, 0x09e64, 0x09e70, 0x09e72, 0x09e78, 0x09e79, + 0x09e80, 0x09fff, 0x0a600, 0x0a600, 0x0a603, 0x0a603, 0x0a610, 0x0a61f, + 0x0a630, 0x0a631, 0x0a638, 0x0a63c, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_noncontext_pipe_br_registers), 8)); + +static const u32 gen7_2_0_noncontext_pipe_bv_registers[] = { + 0x00887, 0x0088c, 0x08600, 0x08600, 0x08602, 0x08602, 0x08610, 0x0861b, + 0x08620, 0x08620, 0x08630, 0x08630, 0x08637, 0x08639, 0x08640, 0x08640, + 0x09600, 0x09600, 0x09602, 0x09603, 0x0960a, 0x09616, 0x09624, 0x0963a, + 0x09640, 0x09640, 0x09e00, 0x09e00, 0x09e02, 0x09e07, 0x09e0a, 0x09e16, + 0x09e19, 0x09e19, 0x09e1c, 0x09e1c, 0x09e20, 0x09e25, 0x09e30, 0x09e31, + 0x09e40, 0x09e51, 0x09e64, 0x09e64, 0x09e70, 0x09e72, 0x09e78, 0x09e79, + 0x09e80, 0x09fff, 0x0a600, 0x0a600, 0x0a603, 0x0a603, 0x0a610, 0x0a61f, + 0x0a630, 0x0a631, 0x0a638, 0x0a63c, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_noncontext_pipe_bv_registers), 8)); + +static const u32 gen7_2_0_noncontext_rb_rac_pipe_br_registers[] = { + 0x08e10, 0x08e1c, 0x08e20, 0x08e25, 0x08e51, 0x08e5a, 0x08ea0, 0x08ea3, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_noncontext_rb_rac_pipe_br_registers), 8)); + +static const u32 gen7_2_0_noncontext_rb_rbp_pipe_br_registers[] = { + 0x08e01, 0x08e01, 0x08e04, 0x08e04, 0x08e06, 0x08e09, 0x08e0c, 0x08e0c, + 0x08e28, 0x08e28, 0x08e2c, 0x08e35, 0x08e3b, 0x08e40, 0x08e50, 0x08e50, + 0x08e5b, 0x08e5d, 0x08e5f, 0x08e5f, 0x08e61, 0x08e61, 0x08e63, 0x08e66, + 0x08e68, 0x08e69, 0x08e70, 0x08e79, 0x08e80, 0x08e8f, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_noncontext_rb_rbp_pipe_br_registers), 8)); + +static const u32 gen7_2_0_gras_cluster_gras_pipe_br_registers[] = { + 0x08000, 0x0800c, 0x08010, 0x08092, 0x08094, 0x08099, 0x0809b, 0x0809d, + 0x080a0, 0x080a7, 0x080af, 0x080f1, 0x080f4, 0x080f6, 0x080f8, 0x080fa, + 0x08100, 0x08107, 0x08109, 0x0810b, 0x08110, 0x08113, 0x08120, 0x0813f, + 0x08400, 0x08406, 0x0840a, 0x0840b, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_gras_cluster_gras_pipe_br_registers), 8)); + +static const u32 gen7_2_0_gras_cluster_gras_pipe_bv_registers[] = { + 0x08000, 0x0800c, 0x08010, 0x08092, 0x08094, 0x08099, 0x0809b, 0x0809d, + 0x080a0, 0x080a7, 0x080af, 0x080f1, 0x080f4, 0x080f6, 0x080f8, 0x080fa, + 0x08100, 0x08107, 0x08109, 0x0810b, 0x08110, 0x08113, 0x08120, 0x0813f, + 0x08400, 0x08406, 0x0840a, 0x0840b, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_gras_cluster_gras_pipe_bv_registers), 8)); + +static const u32 gen7_2_0_rb_rac_cluster_ps_pipe_br_registers[] = { + 0x08802, 0x08802, 0x08804, 0x08806, 0x08809, 0x0880a, 0x0880e, 0x08811, + 0x08818, 0x0881e, 0x08821, 0x08821, 0x08823, 0x08826, 0x08829, 0x08829, + 0x0882b, 0x0882e, 0x08831, 0x08831, 0x08833, 0x08836, 0x08839, 0x08839, + 0x0883b, 0x0883e, 0x08841, 0x08841, 0x08843, 0x08846, 0x08849, 0x08849, + 0x0884b, 0x0884e, 0x08851, 0x08851, 0x08853, 0x08856, 0x08859, 0x08859, + 0x0885b, 0x0885e, 0x08860, 0x08864, 0x08870, 0x08870, 0x08873, 0x08876, + 0x08878, 0x08879, 0x08882, 0x08885, 0x08887, 0x08889, 0x08891, 0x08891, + 0x08898, 0x08899, 0x088c0, 0x088c1, 0x088e5, 0x088e5, 0x088f4, 0x088f5, + 0x08a00, 0x08a05, 0x08a10, 0x08a15, 0x08a20, 0x08a25, 0x08a30, 0x08a35, + 0x08c00, 0x08c01, 0x08c18, 0x08c1f, 0x08c26, 0x08c34, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_rb_rac_cluster_ps_pipe_br_registers), 8)); + +static const u32 gen7_2_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers[] = { + 0x0a980, 0x0a984, 0x0a99e, 0x0a99e, 0x0a9a7, 0x0a9a7, 0x0a9aa, 0x0a9aa, + 0x0a9ae, 0x0a9b0, 0x0a9b2, 0x0a9b5, 0x0a9ba, 0x0a9ba, 0x0a9bc, 0x0a9bc, + 0x0a9c4, 0x0a9c4, 0x0a9cd, 0x0a9cd, 0x0a9e0, 0x0a9fc, 0x0aa00, 0x0aa00, + 0x0aa30, 0x0aa31, 0x0aa40, 0x0aabf, 0x0ab00, 0x0ab03, 0x0ab05, 0x0ab05, + 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20, 0x0ab40, 0x0abbf, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers), 8)); + +static const u32 gen7_2_0_sp_cluster_sp_ps_pipe_br_sp_top_registers[] = { + 0x0a980, 0x0a980, 0x0a982, 0x0a984, 0x0a99e, 0x0a9a2, 0x0a9a7, 0x0a9a8, + 0x0a9aa, 0x0a9aa, 0x0a9ae, 0x0a9ae, 0x0a9b0, 0x0a9b1, 0x0a9b3, 0x0a9b5, + 0x0a9ba, 0x0a9bc, 0x0a9c5, 0x0a9c5, 0x0a9e0, 0x0a9f9, 0x0aa00, 0x0aa01, + 0x0ab00, 0x0ab00, 0x0ab02, 0x0ab02, 0x0ab04, 0x0ab05, 0x0ab0a, 0x0ab1b, + 0x0ab20, 0x0ab20, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_cluster_sp_ps_pipe_br_sp_top_registers), 8)); + +static const u32 gen7_2_0_sp_cluster_sp_ps_pipe_br_usptp_registers[] = { + 0x0a980, 0x0a982, 0x0a985, 0x0a9a6, 0x0a9a8, 0x0a9a9, 0x0a9ab, 0x0a9ae, + 0x0a9b0, 0x0a9b3, 0x0a9b6, 0x0a9b9, 0x0a9bb, 0x0a9bf, 0x0a9c2, 0x0a9c3, + 0x0a9c5, 0x0a9c5, 0x0a9cd, 0x0a9cd, 0x0a9d0, 0x0a9d3, 0x0aa01, 0x0aa01, + 0x0aa30, 0x0aa31, 0x0aa40, 0x0aabf, 0x0ab00, 0x0ab05, 0x0ab21, 0x0ab22, + 0x0ab40, 0x0abbf, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_cluster_sp_ps_pipe_br_usptp_registers), 8)); + +static const u32 gen7_2_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers[] = { + 0x0a9b0, 0x0a9b0, 0x0a9b2, 0x0a9b5, 0x0a9ba, 0x0a9ba, 0x0a9bc, 0x0a9bc, + 0x0a9c4, 0x0a9c4, 0x0a9cd, 0x0a9cd, 0x0a9e2, 0x0a9e3, 0x0a9e6, 0x0a9fc, + 0x0aa00, 0x0aa00, 0x0aa31, 0x0aa31, 0x0ab00, 0x0ab01, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers), 8)); + +static const u32 gen7_2_0_sp_cluster_sp_ps_pipe_lpac_sp_top_registers[] = { + 0x0a9b0, 0x0a9b1, 0x0a9b3, 0x0a9b5, 0x0a9ba, 0x0a9bc, 0x0a9c5, 0x0a9c5, + 0x0a9e2, 0x0a9e3, 0x0a9e6, 0x0a9f9, 0x0aa00, 0x0aa00, 0x0ab00, 0x0ab00, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_cluster_sp_ps_pipe_lpac_sp_top_registers), 8)); + +static const u32 gen7_2_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers[] = { + 0x0a9b0, 0x0a9b3, 0x0a9b6, 0x0a9b9, 0x0a9bb, 0x0a9be, 0x0a9c2, 0x0a9c3, + 0x0a9c5, 0x0a9c5, 0x0a9cd, 0x0a9cd, 0x0a9d0, 0x0a9d3, 0x0aa31, 0x0aa31, + 0x0ab00, 0x0ab01, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers), 8)); + +static const u32 gen7_2_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers[] = { + 0x0a800, 0x0a801, 0x0a81b, 0x0a81d, 0x0a822, 0x0a822, 0x0a824, 0x0a824, + 0x0a827, 0x0a82a, 0x0a830, 0x0a830, 0x0a832, 0x0a835, 0x0a83a, 0x0a83a, + 0x0a83c, 0x0a83c, 0x0a83f, 0x0a841, 0x0a85b, 0x0a85d, 0x0a862, 0x0a862, + 0x0a864, 0x0a864, 0x0a867, 0x0a867, 0x0a870, 0x0a870, 0x0a872, 0x0a872, + 0x0a88c, 0x0a88e, 0x0a893, 0x0a893, 0x0a895, 0x0a895, 0x0a898, 0x0a898, + 0x0a89a, 0x0a89d, 0x0a8a0, 0x0a8af, 0x0a8c0, 0x0a8c3, 0x0ab00, 0x0ab03, + 0x0ab05, 0x0ab05, 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20, 0x0ab40, 0x0abbf, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers), 8)); + +static const u32 gen7_2_0_sp_cluster_sp_vs_pipe_br_sp_top_registers[] = { + 0x0a800, 0x0a800, 0x0a81c, 0x0a81d, 0x0a822, 0x0a824, 0x0a82d, 0x0a82d, + 0x0a82f, 0x0a831, 0x0a834, 0x0a835, 0x0a83a, 0x0a83c, 0x0a840, 0x0a840, + 0x0a85c, 0x0a85d, 0x0a862, 0x0a864, 0x0a868, 0x0a868, 0x0a870, 0x0a871, + 0x0a88d, 0x0a88e, 0x0a893, 0x0a895, 0x0a899, 0x0a899, 0x0a8a0, 0x0a8af, + 0x0ab00, 0x0ab00, 0x0ab02, 0x0ab02, 0x0ab04, 0x0ab05, 0x0ab0a, 0x0ab1b, + 0x0ab20, 0x0ab20, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_cluster_sp_vs_pipe_br_sp_top_registers), 8)); + +static const u32 gen7_2_0_sp_cluster_sp_vs_pipe_br_usptp_registers[] = { + 0x0a800, 0x0a81b, 0x0a81e, 0x0a821, 0x0a823, 0x0a827, 0x0a82d, 0x0a82d, + 0x0a82f, 0x0a833, 0x0a836, 0x0a839, 0x0a83b, 0x0a85b, 0x0a85e, 0x0a861, + 0x0a863, 0x0a868, 0x0a870, 0x0a88c, 0x0a88f, 0x0a892, 0x0a894, 0x0a899, + 0x0a8c0, 0x0a8c3, 0x0ab00, 0x0ab05, 0x0ab21, 0x0ab22, 0x0ab40, 0x0abbf, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_cluster_sp_vs_pipe_br_usptp_registers), 8)); + +static const u32 gen7_2_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers[] = { + 0x0a800, 0x0a801, 0x0a81b, 0x0a81d, 0x0a822, 0x0a822, 0x0a824, 0x0a824, + 0x0a827, 0x0a82a, 0x0a830, 0x0a830, 0x0a832, 0x0a835, 0x0a83a, 0x0a83a, + 0x0a83c, 0x0a83c, 0x0a83f, 0x0a841, 0x0a85b, 0x0a85d, 0x0a862, 0x0a862, + 0x0a864, 0x0a864, 0x0a867, 0x0a867, 0x0a870, 0x0a870, 0x0a872, 0x0a872, + 0x0a88c, 0x0a88e, 0x0a893, 0x0a893, 0x0a895, 0x0a895, 0x0a898, 0x0a898, + 0x0a89a, 0x0a89d, 0x0a8a0, 0x0a8af, 0x0a8c0, 0x0a8c3, 0x0ab00, 0x0ab02, + 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20, 0x0ab40, 0x0abbf, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers), 8)); + +static const u32 gen7_2_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers[] = { + 0x0a800, 0x0a800, 0x0a81c, 0x0a81d, 0x0a822, 0x0a824, 0x0a82d, 0x0a82d, + 0x0a82f, 0x0a831, 0x0a834, 0x0a835, 0x0a83a, 0x0a83c, 0x0a840, 0x0a840, + 0x0a85c, 0x0a85d, 0x0a862, 0x0a864, 0x0a868, 0x0a868, 0x0a870, 0x0a871, + 0x0a88d, 0x0a88e, 0x0a893, 0x0a895, 0x0a899, 0x0a899, 0x0a8a0, 0x0a8af, + 0x0ab00, 0x0ab00, 0x0ab02, 0x0ab02, 0x0ab0a, 0x0ab1b, 0x0ab20, 0x0ab20, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers), 8)); + +static const u32 gen7_2_0_sp_cluster_sp_vs_pipe_bv_usptp_registers[] = { + 0x0a800, 0x0a81b, 0x0a81e, 0x0a821, 0x0a823, 0x0a827, 0x0a82d, 0x0a82d, + 0x0a82f, 0x0a833, 0x0a836, 0x0a839, 0x0a83b, 0x0a85b, 0x0a85e, 0x0a861, + 0x0a863, 0x0a868, 0x0a870, 0x0a88c, 0x0a88f, 0x0a892, 0x0a894, 0x0a899, + 0x0a8c0, 0x0a8c3, 0x0ab00, 0x0ab02, 0x0ab21, 0x0ab22, 0x0ab40, 0x0abbf, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_cluster_sp_vs_pipe_bv_usptp_registers), 8)); + +static const u32 gen7_2_0_sp_noncontext_pipe_lpac_hlsq_state_registers[] = { + 0x0af88, 0x0af8b, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_sp_noncontext_pipe_lpac_hlsq_state_registers), 8)); + +static const struct gen7_sel_reg gen7_2_0_rb_rac_sel = { + .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, + .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, + .val = 0x0, +}; + +static const struct gen7_sel_reg gen7_2_0_rb_rbp_sel = { + .host_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_HOST, + .cd_reg = REG_A6XX_RB_RB_SUB_BLOCK_SEL_CNTL_CD, + .val = 0x9, +}; + +static struct gen7_cluster_registers gen7_2_0_clusters[] = { + { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT, + gen7_2_0_noncontext_pipe_br_registers, }, + { A7XX_CLUSTER_NONE, A7XX_PIPE_BV, STATE_NON_CONTEXT, + gen7_2_0_noncontext_pipe_bv_registers, }, + { A7XX_CLUSTER_NONE, A7XX_PIPE_LPAC, STATE_NON_CONTEXT, + gen7_0_0_noncontext_pipe_lpac_registers, }, + { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT, + gen7_2_0_noncontext_rb_rac_pipe_br_registers, &gen7_2_0_rb_rac_sel, }, + { A7XX_CLUSTER_NONE, A7XX_PIPE_BR, STATE_NON_CONTEXT, + gen7_2_0_noncontext_rb_rbp_pipe_br_registers, &gen7_2_0_rb_rbp_sel, }, + { A7XX_CLUSTER_GRAS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + gen7_2_0_gras_cluster_gras_pipe_br_registers, }, + { A7XX_CLUSTER_GRAS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + gen7_2_0_gras_cluster_gras_pipe_bv_registers, }, + { A7XX_CLUSTER_GRAS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + gen7_2_0_gras_cluster_gras_pipe_br_registers, }, + { A7XX_CLUSTER_GRAS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + gen7_2_0_gras_cluster_gras_pipe_bv_registers, }, + { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + gen7_0_0_pc_cluster_fe_pipe_br_registers, }, + { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + gen7_0_0_pc_cluster_fe_pipe_bv_registers, }, + { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + gen7_0_0_pc_cluster_fe_pipe_br_registers, }, + { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + gen7_0_0_pc_cluster_fe_pipe_bv_registers, }, + { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + gen7_2_0_rb_rac_cluster_ps_pipe_br_registers, &gen7_2_0_rb_rac_sel, }, + { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + gen7_2_0_rb_rac_cluster_ps_pipe_br_registers, &gen7_2_0_rb_rac_sel, }, + { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers, &gen7_2_0_rb_rbp_sel, }, + { A7XX_CLUSTER_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers, &gen7_2_0_rb_rbp_sel, }, + { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + gen7_0_0_vfd_cluster_fe_pipe_br_registers, }, + { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + gen7_0_0_vfd_cluster_fe_pipe_bv_registers, }, + { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + gen7_0_0_vfd_cluster_fe_pipe_br_registers, }, + { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + gen7_0_0_vfd_cluster_fe_pipe_bv_registers, }, + { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + gen7_0_0_vpc_cluster_fe_pipe_br_registers, }, + { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + gen7_0_0_vpc_cluster_fe_pipe_bv_registers, }, + { A7XX_CLUSTER_FE, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + gen7_0_0_vpc_cluster_fe_pipe_br_registers, }, + { A7XX_CLUSTER_FE, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + gen7_0_0_vpc_cluster_fe_pipe_bv_registers, }, + { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers, }, + { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers, }, + { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers, }, + { A7XX_CLUSTER_PC_VS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + gen7_0_0_vpc_cluster_pc_vs_pipe_bv_registers, }, + { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_0, + gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers, }, + { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BV, STATE_FORCE_CTXT_0, + gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, }, + { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BR, STATE_FORCE_CTXT_1, + gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers, }, + { A7XX_CLUSTER_VPC_PS, A7XX_PIPE_BV, STATE_FORCE_CTXT_1, + gen7_0_0_vpc_cluster_vpc_ps_pipe_bv_registers, }, +}; + +static struct gen7_sptp_cluster_registers gen7_2_0_sptp_clusters[] = { + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE, + gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers, 0xae00 }, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP, + gen7_0_0_sp_noncontext_pipe_br_sp_top_registers, 0xae00 }, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP, + gen7_0_0_sp_noncontext_pipe_br_usptp_registers, 0xae00 }, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_STATE, + gen7_2_0_sp_noncontext_pipe_lpac_hlsq_state_registers, 0xaf80 }, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_SP_TOP, + gen7_0_0_sp_noncontext_pipe_lpac_sp_top_registers, 0xaf80 }, + { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP, + gen7_0_0_sp_noncontext_pipe_lpac_usptp_registers, 0xaf80 }, + { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_BR, 0, A7XX_USPTP, + gen7_0_0_tpl1_noncontext_pipe_br_registers, 0xb600 }, + { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP, + gen7_0_0_tpl1_noncontext_pipe_lpac_registers, 0xb780 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE, + gen7_2_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_DP, + gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP, + gen7_2_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP, + gen7_2_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_STATE, + gen7_2_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_DP, + gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_SP_TOP, + gen7_2_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP, + gen7_2_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_HLSQ_DP, + gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_HLSQ_DP, + gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_SP_TOP, + gen7_2_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_USPTP, + gen7_2_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_SP_TOP, + gen7_2_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_USPTP, + gen7_2_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_STATE, + gen7_2_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_HLSQ_DP, + gen7_0_0_sp_cluster_sp_ps_pipe_lpac_hlsq_dp_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_SP_TOP, + gen7_2_0_sp_cluster_sp_ps_pipe_lpac_sp_top_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP, + gen7_2_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers, 0xa800 }, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_HLSQ_STATE, + gen7_2_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers, 0xa800 }, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_HLSQ_STATE, + gen7_2_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers, 0xa800 }, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_SP_TOP, + gen7_2_0_sp_cluster_sp_vs_pipe_br_sp_top_registers, 0xa800 }, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_SP_TOP, + gen7_2_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers, 0xa800 }, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP, + gen7_2_0_sp_cluster_sp_vs_pipe_br_usptp_registers, 0xa800 }, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_USPTP, + gen7_2_0_sp_cluster_sp_vs_pipe_bv_usptp_registers, 0xa800 }, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_HLSQ_STATE, + gen7_2_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers, 0xa800 }, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_HLSQ_STATE, + gen7_2_0_sp_cluster_sp_vs_pipe_bv_hlsq_state_registers, 0xa800 }, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_SP_TOP, + gen7_2_0_sp_cluster_sp_vs_pipe_br_sp_top_registers, 0xa800 }, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_SP_TOP, + gen7_2_0_sp_cluster_sp_vs_pipe_bv_sp_top_registers, 0xa800 }, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP, + gen7_2_0_sp_cluster_sp_vs_pipe_br_usptp_registers, 0xa800 }, + { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_USPTP, + gen7_2_0_sp_cluster_sp_vs_pipe_bv_usptp_registers, 0xa800 }, + { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP, + gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 }, + { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX1_3D_CPS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP, + gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 }, + { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX2_3D_CPS_REG, A7XX_PIPE_BR, 2, A7XX_USPTP, + gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 }, + { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX3_3D_CPS_REG, A7XX_PIPE_BR, 3, A7XX_USPTP, + gen7_0_0_tpl1_cluster_sp_ps_pipe_br_registers, 0xb000 }, + { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, A7XX_PIPE_LPAC, 0, A7XX_USPTP, + gen7_0_0_tpl1_cluster_sp_ps_pipe_lpac_registers, 0xb000 }, + { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, A7XX_PIPE_BR, 0, A7XX_USPTP, + gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers, 0xb000 }, + { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, A7XX_PIPE_BV, 0, A7XX_USPTP, + gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers, 0xb000 }, + { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, A7XX_PIPE_BR, 1, A7XX_USPTP, + gen7_0_0_tpl1_cluster_sp_vs_pipe_br_registers, 0xb000 }, + { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, A7XX_PIPE_BV, 1, A7XX_USPTP, + gen7_0_0_tpl1_cluster_sp_vs_pipe_bv_registers, 0xb000 }, +}; + +static const u32 gen7_2_0_dbgc_registers[] = { + 0x005ff, 0x0061c, 0x0061e, 0x00634, 0x00640, 0x0065e, 0x00679, 0x0067e, + 0x00699, 0x00699, 0x0069b, 0x0069e, 0x006a0, 0x006a3, 0x006c0, 0x006c1, + 0x18400, 0x1841c, 0x1841e, 0x18434, 0x18440, 0x1845c, 0x18479, 0x1847c, + 0x18580, 0x18581, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_dbgc_registers), 8)); + +static const u32 gen7_2_0_rscc_registers[] = { + 0x14000, 0x14036, 0x14040, 0x14047, 0x14080, 0x14084, 0x14089, 0x1408c, + 0x14091, 0x14094, 0x14099, 0x1409c, 0x140a1, 0x140a4, 0x140a9, 0x140ac, + 0x14100, 0x14104, 0x14114, 0x14119, 0x14124, 0x14132, 0x14154, 0x1416b, + 0x14340, 0x14342, 0x14344, 0x1437c, 0x143f0, 0x143f8, 0x143fa, 0x143fe, + 0x14400, 0x14404, 0x14406, 0x1440a, 0x1440c, 0x14410, 0x14412, 0x14416, + 0x14418, 0x1441c, 0x1441e, 0x14422, 0x14424, 0x14424, 0x14498, 0x144a0, + 0x144a2, 0x144a6, 0x144a8, 0x144ac, 0x144ae, 0x144b2, 0x144b4, 0x144b8, + 0x144ba, 0x144be, 0x144c0, 0x144c4, 0x144c6, 0x144ca, 0x144cc, 0x144cc, + 0x14540, 0x14548, 0x1454a, 0x1454e, 0x14550, 0x14554, 0x14556, 0x1455a, + 0x1455c, 0x14560, 0x14562, 0x14566, 0x14568, 0x1456c, 0x1456e, 0x14572, + 0x14574, 0x14574, 0x145e8, 0x145f0, 0x145f2, 0x145f6, 0x145f8, 0x145fc, + 0x145fe, 0x14602, 0x14604, 0x14608, 0x1460a, 0x1460e, 0x14610, 0x14614, + 0x14616, 0x1461a, 0x1461c, 0x1461c, 0x14690, 0x14698, 0x1469a, 0x1469e, + 0x146a0, 0x146a4, 0x146a6, 0x146aa, 0x146ac, 0x146b0, 0x146b2, 0x146b6, + 0x146b8, 0x146bc, 0x146be, 0x146c2, 0x146c4, 0x146c4, 0x14738, 0x14740, + 0x14742, 0x14746, 0x14748, 0x1474c, 0x1474e, 0x14752, 0x14754, 0x14758, + 0x1475a, 0x1475e, 0x14760, 0x14764, 0x14766, 0x1476a, 0x1476c, 0x1476c, + 0x147e0, 0x147e8, 0x147ea, 0x147ee, 0x147f0, 0x147f4, 0x147f6, 0x147fa, + 0x147fc, 0x14800, 0x14802, 0x14806, 0x14808, 0x1480c, 0x1480e, 0x14812, + 0x14814, 0x14814, 0x14888, 0x14890, 0x14892, 0x14896, 0x14898, 0x1489c, + 0x1489e, 0x148a2, 0x148a4, 0x148a8, 0x148aa, 0x148ae, 0x148b0, 0x148b4, + 0x148b6, 0x148ba, 0x148bc, 0x148bc, 0x14930, 0x14938, 0x1493a, 0x1493e, + 0x14940, 0x14944, 0x14946, 0x1494a, 0x1494c, 0x14950, 0x14952, 0x14956, + 0x14958, 0x1495c, 0x1495e, 0x14962, 0x14964, 0x14964, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_rscc_registers), 8)); + +static const u32 gen7_2_0_cpr_registers[] = { + 0x26800, 0x26805, 0x26808, 0x2680c, 0x26814, 0x26814, 0x2681c, 0x2681c, + 0x26820, 0x26838, 0x26840, 0x26840, 0x26848, 0x26848, 0x26850, 0x26850, + 0x26880, 0x2689e, 0x26980, 0x269b0, 0x269c0, 0x269c8, 0x269e0, 0x269ee, + 0x269fb, 0x269ff, 0x26a02, 0x26a07, 0x26a09, 0x26a0b, 0x26a10, 0x26b0f, + 0x27440, 0x27441, 0x27444, 0x27444, 0x27480, 0x274a2, 0x274ac, 0x274ad, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_cpr_registers), 8)); + +static const u32 gen7_2_0_dpm_lkg_registers[] = { + 0x21c00, 0x21c00, 0x21c08, 0x21c09, 0x21c0e, 0x21c0f, 0x21c4f, 0x21c50, + 0x21c52, 0x21c52, 0x21c54, 0x21c56, 0x21c58, 0x21c5a, 0x21c5c, 0x21c60, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_dpm_lkg_registers), 8)); + +static const u32 gen7_2_0_gpucc_registers[] = { + 0x24000, 0x2400f, 0x24400, 0x2440f, 0x24800, 0x24805, 0x24c00, 0x24cff, + 0x25400, 0x25404, 0x25800, 0x25804, 0x25c00, 0x25c04, 0x26000, 0x26004, + 0x26400, 0x26405, 0x26414, 0x2641d, 0x2642a, 0x26430, 0x26432, 0x26433, + 0x26441, 0x2644b, 0x2644d, 0x26457, 0x26466, 0x26468, 0x26478, 0x2647a, + 0x26489, 0x2648a, 0x2649c, 0x2649e, 0x264a0, 0x264a4, 0x264c5, 0x264c7, + 0x264d6, 0x264d8, 0x264e8, 0x264e9, 0x264f9, 0x264fc, 0x2651c, 0x2651e, + 0x26540, 0x26576, 0x26600, 0x26616, 0x26620, 0x2662d, 0x26630, 0x26631, + 0x26635, 0x26635, 0x26637, 0x26637, 0x2663a, 0x2663a, 0x26642, 0x26642, + 0x26656, 0x26658, 0x2665b, 0x2665d, 0x2665f, 0x26662, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_gpucc_registers), 8)); + +static const u32 gen7_2_0_cx_misc_registers[] = { + 0x27800, 0x27800, 0x27810, 0x27814, 0x27820, 0x27824, 0x27832, 0x27857, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_cx_misc_registers), 8)); + +static const u32 gen7_2_0_dpm_registers[] = { + 0x1aa00, 0x1aa06, 0x1aa09, 0x1aa0a, 0x1aa0c, 0x1aa0d, 0x1aa0f, 0x1aa12, + 0x1aa14, 0x1aa47, 0x1aa50, 0x1aa51, + UINT_MAX, UINT_MAX, +}; +static_assert(IS_ALIGNED(sizeof(gen7_2_0_dpm_registers), 8)); + +static struct gen7_reg_list gen7_2_0_reg_list[] = { + { gen7_2_0_gpu_registers, NULL }, + { gen7_2_0_cx_misc_registers, NULL }, + { gen7_2_0_dpm_registers, NULL }, + { gen7_2_0_dbgc_registers, NULL }, + { NULL, NULL }, +}; + +static const u32 *gen7_2_0_external_core_regs[] = { + gen7_2_0_gpucc_registers, + gen7_2_0_cpr_registers, + gen7_2_0_dpm_lkg_registers, +}; +#endif /*_ADRENO_GEN7_2_0_SNAPSHOT_H */ diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index bc14df96feb0..77526892eb8c 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -48,6 +48,7 @@ enum adreno_family { ADRENO_6XX_GEN4, /* a660 family */ ADRENO_7XX_GEN1, /* a730 family */ ADRENO_7XX_GEN2, /* a740 family */ + ADRENO_7XX_GEN3, /* a750 family */ }; #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) @@ -77,7 +78,7 @@ struct adreno_reglist { }; extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[]; -extern const struct adreno_reglist a660_hwcg[], a690_hwcg[], a730_hwcg[], a740_hwcg[]; +extern const struct adreno_reglist a660_hwcg[], a690_hwcg[], a702_hwcg[], a730_hwcg[], a740_hwcg[]; struct adreno_speedbin { uint16_t fuse; @@ -256,6 +257,11 @@ static inline bool adreno_is_a305(const struct adreno_gpu *gpu) return adreno_is_revn(gpu, 305); } +static inline bool adreno_is_a305b(const struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] == 0x03000512; +} + static inline bool adreno_is_a306(const struct adreno_gpu *gpu) { /* yes, 307, because a305c is 306 */ @@ -382,6 +388,20 @@ static inline int adreno_is_a690(const struct adreno_gpu *gpu) return gpu->info->chip_ids[0] == 0x06090000; } +static inline int adreno_is_a702(const struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] == 0x07000200; +} + +static inline int adreno_is_a610_family(const struct adreno_gpu *gpu) +{ + if (WARN_ON_ONCE(!gpu->info)) + return false; + + /* TODO: A612 */ + return adreno_is_a610(gpu) || adreno_is_a702(gpu); +} + /* check for a615, a616, a618, a619 or any a630 derivatives */ static inline int adreno_is_a630_family(const struct adreno_gpu *gpu) { @@ -423,12 +443,17 @@ static inline int adreno_is_a740(struct adreno_gpu *gpu) return gpu->info->chip_ids[0] == 0x43050a01; } -/* Placeholder to make future diffs smaller */ +static inline int adreno_is_a750(struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] == 0x43051401; +} + static inline int adreno_is_a740_family(struct adreno_gpu *gpu) { if (WARN_ON_ONCE(!gpu->info)) return false; - return gpu->info->family == ADRENO_7XX_GEN2; + return gpu->info->family == ADRENO_7XX_GEN2 || + gpu->info->family == ADRENO_7XX_GEN3; } static inline int adreno_is_a7xx(struct adreno_gpu *gpu) diff --git a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h index 8a4a2d161a29..7067376e25e1 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h +++ b/drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h @@ -3,50 +3,28 @@ /* Autogenerated file, DO NOT EDIT manually! -This file was generated by the rules-ng-ng headergen tool in this git repository: -http://github.com/freedreno/envytools/ -git clone https://github.com/freedreno/envytools.git +This file was generated by the rules-ng-ng gen_header.py tool in this git repository: +http://gitlab.freedesktop.org/mesa/mesa/ +git clone https://gitlab.freedesktop.org/mesa/mesa.git The rules-ng-ng source files this header was generated from are: -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno.xml ( 594 bytes, from 2023-03-10 18:32:52) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml ( 1572 bytes, from 2022-07-23 20:21:46) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a2xx.xml ( 91929 bytes, from 2023-02-28 23:52:27) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from 2023-03-10 18:32:53) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 74995 bytes, from 2023-03-20 18:06:23) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a3xx.xml ( 84231 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a4xx.xml ( 113474 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a5xx.xml ( 149590 bytes, from 2023-02-14 19:37:12) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx.xml ( 198949 bytes, from 2023-03-20 18:06:23) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/a6xx_gmu.xml ( 11404 bytes, from 2023-03-10 18:32:53) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/ocmem.xml ( 1773 bytes, from 2022-08-02 16:38:43) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_control_regs.xml ( 9055 bytes, from 2023-03-10 18:32:52) -- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pipe_regs.xml ( 2976 bytes, from 2023-03-10 18:32:52) - -Copyright (C) 2013-2023 by the following authors: -- Rob Clark <robdclark@gmail.com> (robclark) -- Ilia Mirkin <imirkin@alum.mit.edu> (imirkin) - -Permission is hereby granted, free of charge, to any person obtaining -a copy of this software and associated documentation files (the -"Software"), to deal in the Software without restriction, including -without limitation the rights to use, copy, modify, merge, publish, -distribute, sublicense, and/or sell copies of the Software, and to -permit persons to whom the Software is furnished to do so, subject to -the following conditions: - -The above copyright notice and this permission notice (including the -next paragraph) shall be included in all copies or substantial -portions of the Software. - -THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF -MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE -LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION -OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION -WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_pm4.xml ( 85856 bytes, from Fri Feb 23 13:07:00 2024) +- /home/robclark/src/mesa/mesa/src/freedreno/registers/adreno/adreno_common.xml ( 15434 bytes, from Fri Jun 2 14:59:26 2023) */ +#ifdef __KERNEL__ +#include <linux/bug.h> +#define assert(x) BUG_ON(!(x)) +#else +#include <assert.h> +#endif + +#ifdef __cplusplus +#define __struct_cast(X) +#else +#define __struct_cast(X) (struct X) +#endif enum vgt_event_type { VS_DEALLOC = 0, @@ -94,12 +72,14 @@ enum vgt_event_type { LRZ_FLUSH = 38, BLIT_OP_FILL_2D = 39, BLIT_OP_COPY_2D = 40, + UNK_40 = 40, BLIT_OP_SCALE_2D = 42, CONTEXT_DONE_2D = 43, UNK_2C = 44, UNK_2D = 45, CACHE_INVALIDATE = 49, LABEL = 63, + DUMMY_EVENT = 1, CCU_INVALIDATE_DEPTH = 24, CCU_INVALIDATE_COLOR = 25, CCU_RESOLVE_CLEAN = 26, @@ -192,7 +172,7 @@ enum pc_di_vis_cull_mode { }; enum adreno_pm4_packet_type { - CP_TYPE0_PKT = 0, + CP_TYPE0_PKT = 0x00000000, CP_TYPE1_PKT = 0x40000000, CP_TYPE2_PKT = 0x80000000, CP_TYPE3_PKT = 0xc0000000, @@ -224,6 +204,7 @@ enum adreno_pm4_type3_packets { CP_COND_WRITE = 69, CP_COND_WRITE5 = 69, CP_EVENT_WRITE = 70, + CP_EVENT_WRITE7 = 70, CP_EVENT_WRITE_SHD = 88, CP_EVENT_WRITE_CFL = 89, CP_EVENT_WRITE_ZPD = 91, @@ -318,6 +299,7 @@ enum adreno_pm4_type3_packets { CP_WAIT_TWO_REGS = 112, CP_MEMCPY = 117, CP_SET_BIN_DATA5_OFFSET = 46, + CP_SET_UNK_BIN_DATA = 45, CP_CONTEXT_SWITCH = 84, CP_SET_CTXSWITCH_IB = 85, CP_REG_WRITE = 109, @@ -325,13 +307,16 @@ enum adreno_pm4_type3_packets { CP_END_BIN = 81, CP_PREEMPT_DISABLE = 108, CP_WAIT_TIMESTAMP = 20, + CP_GLOBAL_TIMESTAMP = 21, + CP_LOCAL_TIMESTAMP = 22, CP_THREAD_CONTROL = 23, + CP_RESOURCE_LIST = 24, + CP_BV_BR_COUNT_OPS = 27, + CP_MODIFY_TIMESTAMP = 28, CP_CONTEXT_REG_BUNCH2 = 93, - CP_UNK15 = 21, - CP_UNK16 = 22, - CP_UNK18 = 24, - CP_UNK1B = 27, - CP_UNK49 = 73, + CP_MEM_TO_SCRATCH_MEM = 73, + CP_FIXED_STRIDE_DRAW_TABLE = 127, + CP_RESET_CONTEXT_STATE = 31, }; enum adreno_state_block { @@ -456,6 +441,13 @@ enum cp_cond_function { WRITE_GT = 6, }; +enum poll_memory_type { + POLL_REGISTER = 0, + POLL_MEMORY = 1, + POLL_SCRATCH = 2, + POLL_ON_CHIP = 3, +}; + enum render_mode_cmd { BYPASS = 1, BINNING = 2, @@ -465,6 +457,19 @@ enum render_mode_cmd { END2D = 8, }; +enum event_write_src { + EV_WRITE_USER_32B = 0, + EV_WRITE_USER_64B = 1, + EV_WRITE_TIMESTAMP_SUM = 2, + EV_WRITE_ALWAYSON = 3, + EV_WRITE_REGS_CONTENT = 4, +}; + +enum event_write_dst { + EV_DST_RAM = 0, + EV_DST_ONCHIP = 1, +}; + enum cp_blit_cmd { BLIT_OP_FILL = 0, BLIT_OP_COPY = 1, @@ -492,12 +497,31 @@ enum pseudo_reg { SECURE_SAVE_ADDR = 2, NON_PRIV_SAVE_ADDR = 3, COUNTER = 4, + DRAW_STRM_ADDRESS = 8, + DRAW_STRM_SIZE_ADDRESS = 9, + PRIM_STRM_ADDRESS = 10, + UNK_STRM_ADDRESS = 11, + UNK_STRM_SIZE_ADDRESS = 12, + BINDLESS_BASE_0_ADDR = 16, + BINDLESS_BASE_1_ADDR = 17, + BINDLESS_BASE_2_ADDR = 18, + BINDLESS_BASE_3_ADDR = 19, + BINDLESS_BASE_4_ADDR = 20, + BINDLESS_BASE_5_ADDR = 21, + BINDLESS_BASE_6_ADDR = 22, +}; + +enum source_type { + SOURCE_REG = 0, + SOURCE_SCRATCH_MEM = 1, }; enum compare_mode { PRED_TEST = 1, REG_COMPARE = 2, RENDER_MODE = 3, + REG_COMPARE_IMM = 4, + THREAD_MODE = 5, }; enum ctxswitch_ib { @@ -514,6 +538,30 @@ enum reg_tracker { TRACK_LRZ = 8, }; +enum ts_wait_value_src { + TS_WAIT_GE_32B = 0, + TS_WAIT_GE_64B = 1, + TS_WAIT_GE_TIMESTAMP_SUM = 2, +}; + +enum ts_wait_type { + TS_WAIT_RAM = 0, + TS_WAIT_ONCHIP = 1, +}; + +enum pipe_count_op { + PIPE_CLEAR_BV_BR = 1, + PIPE_SET_BR_OFFSET = 2, + PIPE_BR_WAIT_FOR_BV = 3, + PIPE_BV_WAIT_FOR_BR = 4, +}; + +enum timestamp_op { + MODIFY_TIMESTAMP_CLEAR = 0, + MODIFY_TIMESTAMP_ADD_GLOBAL = 1, + MODIFY_TIMESTAMP_ADD_LOCAL = 2, +}; + enum cp_thread { CP_SET_THREAD_BR = 1, CP_SET_THREAD_BV = 2, @@ -557,7 +605,8 @@ static inline uint32_t CP_LOAD_STATE_1_STATE_TYPE(enum adreno_state_type val) #define CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT 2 static inline uint32_t CP_LOAD_STATE_1_EXT_SRC_ADDR(uint32_t val) { - return ((val >> 2) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << CP_LOAD_STATE_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE_1_EXT_SRC_ADDR__MASK; } #define REG_CP_LOAD_STATE4_0 0x00000000 @@ -597,7 +646,8 @@ static inline uint32_t CP_LOAD_STATE4_1_STATE_TYPE(enum a4xx_state_type val) #define CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT 2 static inline uint32_t CP_LOAD_STATE4_1_EXT_SRC_ADDR(uint32_t val) { - return ((val >> 2) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << CP_LOAD_STATE4_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE4_1_EXT_SRC_ADDR__MASK; } #define REG_CP_LOAD_STATE4_2 0x00000002 @@ -645,7 +695,8 @@ static inline uint32_t CP_LOAD_STATE6_0_NUM_UNIT(uint32_t val) #define CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT 2 static inline uint32_t CP_LOAD_STATE6_1_EXT_SRC_ADDR(uint32_t val) { - return ((val >> 2) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK; + assert(!(val & 0x3)); + return (((val >> 2)) << CP_LOAD_STATE6_1_EXT_SRC_ADDR__SHIFT) & CP_LOAD_STATE6_1_EXT_SRC_ADDR__MASK; } #define REG_CP_LOAD_STATE6_2 0x00000002 @@ -834,37 +885,36 @@ static inline uint32_t CP_DRAW_INDX_OFFSET_3_FIRST_INDX(uint32_t val) return ((val) << CP_DRAW_INDX_OFFSET_3_FIRST_INDX__SHIFT) & CP_DRAW_INDX_OFFSET_3_FIRST_INDX__MASK; } - -#define REG_CP_DRAW_INDX_OFFSET_4 0x00000004 -#define CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK 0xffffffff -#define CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT 0 -static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(uint32_t val) +#define REG_A5XX_CP_DRAW_INDX_OFFSET_4 0x00000004 +#define A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK 0xffffffff +#define A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT 0 +static inline uint32_t A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO(uint32_t val) { - return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK; + return ((val) << A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_4_INDX_BASE_LO__MASK; } -#define REG_CP_DRAW_INDX_OFFSET_5 0x00000005 -#define CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK 0xffffffff -#define CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT 0 -static inline uint32_t CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(uint32_t val) +#define REG_A5XX_CP_DRAW_INDX_OFFSET_5 0x00000005 +#define A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK 0xffffffff +#define A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT 0 +static inline uint32_t A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI(uint32_t val) { - return ((val) << CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT) & CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK; + return ((val) << A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_5_INDX_BASE_HI__MASK; } -#define REG_CP_DRAW_INDX_OFFSET_INDX_BASE 0x00000004 +#define REG_A5XX_CP_DRAW_INDX_OFFSET_INDX_BASE 0x00000004 -#define REG_CP_DRAW_INDX_OFFSET_6 0x00000006 -#define CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK 0xffffffff -#define CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT 0 -static inline uint32_t CP_DRAW_INDX_OFFSET_6_MAX_INDICES(uint32_t val) +#define REG_A5XX_CP_DRAW_INDX_OFFSET_6 0x00000006 +#define A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK 0xffffffff +#define A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT 0 +static inline uint32_t A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES(uint32_t val) { - return ((val) << CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT) & CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK; + return ((val) << A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__SHIFT) & A5XX_CP_DRAW_INDX_OFFSET_6_MAX_INDICES__MASK; } #define REG_CP_DRAW_INDX_OFFSET_4 0x00000004 #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK 0xffffffff #define CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT 0 -static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint32_t val) +static inline uint32_t CP_DRAW_INDX_OFFSET_4_INDX_BASE(uint64_t val) { return ((val) << CP_DRAW_INDX_OFFSET_4_INDX_BASE__SHIFT) & CP_DRAW_INDX_OFFSET_4_INDX_BASE__MASK; } @@ -911,7 +961,6 @@ static inline uint32_t A4XX_CP_DRAW_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_type v #define A4XX_CP_DRAW_INDIRECT_0_GS_ENABLE 0x00010000 #define A4XX_CP_DRAW_INDIRECT_0_TESS_ENABLE 0x00020000 - #define REG_A4XX_CP_DRAW_INDIRECT_1 0x00000001 #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK 0xffffffff #define A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT 0 @@ -920,7 +969,6 @@ static inline uint32_t A4XX_CP_DRAW_INDIRECT_1_INDIRECT(uint32_t val) return ((val) << A4XX_CP_DRAW_INDIRECT_1_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDIRECT_1_INDIRECT__MASK; } - #define REG_A5XX_CP_DRAW_INDIRECT_1 0x00000001 #define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__MASK 0xffffffff #define A5XX_CP_DRAW_INDIRECT_1_INDIRECT_LO__SHIFT 0 @@ -973,7 +1021,6 @@ static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_0_PATCH_TYPE(enum a6xx_patch_t #define A4XX_CP_DRAW_INDX_INDIRECT_0_GS_ENABLE 0x00010000 #define A4XX_CP_DRAW_INDX_INDIRECT_0_TESS_ENABLE 0x00020000 - #define REG_A4XX_CP_DRAW_INDX_INDIRECT_1 0x00000001 #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__MASK 0xffffffff #define A4XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE__SHIFT 0 @@ -998,7 +1045,6 @@ static inline uint32_t A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT(uint32_t val) return ((val) << A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__SHIFT) & A4XX_CP_DRAW_INDX_INDIRECT_3_INDIRECT__MASK; } - #define REG_A5XX_CP_DRAW_INDX_INDIRECT_1 0x00000001 #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__MASK 0xffffffff #define A5XX_CP_DRAW_INDX_INDIRECT_1_INDX_BASE_LO__SHIFT 0 @@ -1093,37 +1139,93 @@ static inline uint32_t A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(uint32_t val) #define REG_A6XX_CP_DRAW_INDIRECT_MULTI_DRAW_COUNT 0x00000002 +#define REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000003 -#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000003 +#define REG_INDIRECT_OP_NORMAL_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000005 -#define REG_A6XX_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000005 +#define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX 0x00000003 +#define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES 0x00000005 -#define REG_CP_DRAW_INDIRECT_MULTI_INDEX_INDEXED 0x00000003 +#define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000006 -#define REG_CP_DRAW_INDIRECT_MULTI_MAX_INDICES_INDEXED 0x00000005 +#define REG_INDIRECT_OP_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000008 -#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDEXED 0x00000006 +#define REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000003 -#define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDEXED 0x00000008 +#define REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT 0x00000005 +#define REG_INDIRECT_OP_INDIRECT_COUNT_CP_DRAW_INDIRECT_MULTI_STRIDE 0x00000007 -#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDIRECT 0x00000003 +#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDEX 0x00000003 -#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT_INDIRECT 0x00000005 +#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_MAX_INDICES 0x00000005 -#define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDIRECT 0x00000007 +#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT 0x00000006 +#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT 0x00000008 -#define REG_CP_DRAW_INDIRECT_MULTI_INDEX_INDIRECT_INDEXED 0x00000003 +#define REG_INDIRECT_OP_INDIRECT_COUNT_INDEXED_CP_DRAW_INDIRECT_MULTI_STRIDE 0x0000000a -#define REG_CP_DRAW_INDIRECT_MULTI_MAX_INDICES_INDIRECT_INDEXED 0x00000005 +#define REG_CP_DRAW_AUTO_0 0x00000000 +#define CP_DRAW_AUTO_0_PRIM_TYPE__MASK 0x0000003f +#define CP_DRAW_AUTO_0_PRIM_TYPE__SHIFT 0 +static inline uint32_t CP_DRAW_AUTO_0_PRIM_TYPE(enum pc_di_primtype val) +{ + return ((val) << CP_DRAW_AUTO_0_PRIM_TYPE__SHIFT) & CP_DRAW_AUTO_0_PRIM_TYPE__MASK; +} +#define CP_DRAW_AUTO_0_SOURCE_SELECT__MASK 0x000000c0 +#define CP_DRAW_AUTO_0_SOURCE_SELECT__SHIFT 6 +static inline uint32_t CP_DRAW_AUTO_0_SOURCE_SELECT(enum pc_di_src_sel val) +{ + return ((val) << CP_DRAW_AUTO_0_SOURCE_SELECT__SHIFT) & CP_DRAW_AUTO_0_SOURCE_SELECT__MASK; +} +#define CP_DRAW_AUTO_0_VIS_CULL__MASK 0x00000300 +#define CP_DRAW_AUTO_0_VIS_CULL__SHIFT 8 +static inline uint32_t CP_DRAW_AUTO_0_VIS_CULL(enum pc_di_vis_cull_mode val) +{ + return ((val) << CP_DRAW_AUTO_0_VIS_CULL__SHIFT) & CP_DRAW_AUTO_0_VIS_CULL__MASK; +} +#define CP_DRAW_AUTO_0_INDEX_SIZE__MASK 0x00000c00 +#define CP_DRAW_AUTO_0_INDEX_SIZE__SHIFT 10 +static inline uint32_t CP_DRAW_AUTO_0_INDEX_SIZE(enum a4xx_index_size val) +{ + return ((val) << CP_DRAW_AUTO_0_INDEX_SIZE__SHIFT) & CP_DRAW_AUTO_0_INDEX_SIZE__MASK; +} +#define CP_DRAW_AUTO_0_PATCH_TYPE__MASK 0x00003000 +#define CP_DRAW_AUTO_0_PATCH_TYPE__SHIFT 12 +static inline uint32_t CP_DRAW_AUTO_0_PATCH_TYPE(enum a6xx_patch_type val) +{ + return ((val) << CP_DRAW_AUTO_0_PATCH_TYPE__SHIFT) & CP_DRAW_AUTO_0_PATCH_TYPE__MASK; +} +#define CP_DRAW_AUTO_0_GS_ENABLE 0x00010000 +#define CP_DRAW_AUTO_0_TESS_ENABLE 0x00020000 -#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_INDIRECT_INDEXED 0x00000006 +#define REG_CP_DRAW_AUTO_1 0x00000001 +#define CP_DRAW_AUTO_1_NUM_INSTANCES__MASK 0xffffffff +#define CP_DRAW_AUTO_1_NUM_INSTANCES__SHIFT 0 +static inline uint32_t CP_DRAW_AUTO_1_NUM_INSTANCES(uint32_t val) +{ + return ((val) << CP_DRAW_AUTO_1_NUM_INSTANCES__SHIFT) & CP_DRAW_AUTO_1_NUM_INSTANCES__MASK; +} -#define REG_CP_DRAW_INDIRECT_MULTI_INDIRECT_COUNT_INDIRECT_INDEXED 0x00000008 +#define REG_CP_DRAW_AUTO_NUM_VERTICES_BASE 0x00000002 -#define REG_CP_DRAW_INDIRECT_MULTI_STRIDE_INDIRECT_INDEXED 0x0000000a +#define REG_CP_DRAW_AUTO_4 0x00000004 +#define CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__MASK 0xffffffff +#define CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__SHIFT 0 +static inline uint32_t CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET(uint32_t val) +{ + return ((val) << CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__SHIFT) & CP_DRAW_AUTO_4_NUM_VERTICES_OFFSET__MASK; +} + +#define REG_CP_DRAW_AUTO_5 0x00000005 +#define CP_DRAW_AUTO_5_STRIDE__MASK 0xffffffff +#define CP_DRAW_AUTO_5_STRIDE__SHIFT 0 +static inline uint32_t CP_DRAW_AUTO_5_STRIDE(uint32_t val) +{ + return ((val) << CP_DRAW_AUTO_5_STRIDE__SHIFT) & CP_DRAW_AUTO_5_STRIDE__MASK; +} #define REG_CP_DRAW_PRED_ENABLE_GLOBAL_0 0x00000000 #define CP_DRAW_PRED_ENABLE_GLOBAL_0_ENABLE 0x00000001 @@ -1147,7 +1249,7 @@ static inline uint32_t CP_DRAW_PRED_SET_0_TEST(enum cp_draw_pred_test val) #define REG_CP_DRAW_PRED_SET_MEM_ADDR 0x00000001 -static inline uint32_t REG_CP_SET_DRAW_STATE_(uint32_t i0) { return 0x00000000 + 0x3*i0; } +#define REG_CP_SET_DRAW_STATE_(i0) (0x00000000 + 0x3*(i0)) static inline uint32_t REG_CP_SET_DRAW_STATE__0(uint32_t i0) { return 0x00000000 + 0x3*i0; } #define CP_SET_DRAW_STATE__0_COUNT__MASK 0x0000ffff @@ -1693,8 +1795,12 @@ static inline uint32_t CP_COND_WRITE5_0_FUNCTION(enum cp_cond_function val) return ((val) << CP_COND_WRITE5_0_FUNCTION__SHIFT) & CP_COND_WRITE5_0_FUNCTION__MASK; } #define CP_COND_WRITE5_0_SIGNED_COMPARE 0x00000008 -#define CP_COND_WRITE5_0_POLL_MEMORY 0x00000010 -#define CP_COND_WRITE5_0_POLL_SCRATCH 0x00000020 +#define CP_COND_WRITE5_0_POLL__MASK 0x00000030 +#define CP_COND_WRITE5_0_POLL__SHIFT 4 +static inline uint32_t CP_COND_WRITE5_0_POLL(enum poll_memory_type val) +{ + return ((val) << CP_COND_WRITE5_0_POLL__SHIFT) & CP_COND_WRITE5_0_POLL__MASK; +} #define CP_COND_WRITE5_0_WRITE_MEMORY 0x00000100 #define REG_CP_COND_WRITE5_1 0x00000001 @@ -1793,8 +1899,12 @@ static inline uint32_t CP_WAIT_REG_MEM_0_FUNCTION(enum cp_cond_function val) return ((val) << CP_WAIT_REG_MEM_0_FUNCTION__SHIFT) & CP_WAIT_REG_MEM_0_FUNCTION__MASK; } #define CP_WAIT_REG_MEM_0_SIGNED_COMPARE 0x00000008 -#define CP_WAIT_REG_MEM_0_POLL_MEMORY 0x00000010 -#define CP_WAIT_REG_MEM_0_POLL_SCRATCH 0x00000020 +#define CP_WAIT_REG_MEM_0_POLL__MASK 0x00000030 +#define CP_WAIT_REG_MEM_0_POLL__SHIFT 4 +static inline uint32_t CP_WAIT_REG_MEM_0_POLL(enum poll_memory_type val) +{ + return ((val) << CP_WAIT_REG_MEM_0_POLL__SHIFT) & CP_WAIT_REG_MEM_0_POLL__MASK; +} #define CP_WAIT_REG_MEM_0_WRITE_MEMORY 0x00000100 #define REG_CP_WAIT_REG_MEM_1 0x00000001 @@ -1960,14 +2070,14 @@ static inline uint32_t CP_COMPUTE_CHECKPOINT_1_ADDR_0_HI(uint32_t val) #define REG_CP_COMPUTE_CHECKPOINT_2 0x00000002 #define REG_CP_COMPUTE_CHECKPOINT_3 0x00000003 -#define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK 0xffffffff -#define CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT 0 -static inline uint32_t CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN(uint32_t val) -{ - return ((val) << CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_3_ADDR_1_LEN__MASK; -} #define REG_CP_COMPUTE_CHECKPOINT_4 0x00000004 +#define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK 0xffffffff +#define CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT 0 +static inline uint32_t CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN(uint32_t val) +{ + return ((val) << CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__SHIFT) & CP_COMPUTE_CHECKPOINT_4_ADDR_1_LEN__MASK; +} #define REG_CP_COMPUTE_CHECKPOINT_5 0x00000005 #define CP_COMPUTE_CHECKPOINT_5_ADDR_1_LO__MASK 0xffffffff @@ -2033,6 +2143,90 @@ static inline uint32_t CP_EVENT_WRITE_2_ADDR_0_HI(uint32_t val) #define REG_CP_EVENT_WRITE_3 0x00000003 +#define REG_CP_EVENT_WRITE7_0 0x00000000 +#define CP_EVENT_WRITE7_0_EVENT__MASK 0x000000ff +#define CP_EVENT_WRITE7_0_EVENT__SHIFT 0 +static inline uint32_t CP_EVENT_WRITE7_0_EVENT(enum vgt_event_type val) +{ + return ((val) << CP_EVENT_WRITE7_0_EVENT__SHIFT) & CP_EVENT_WRITE7_0_EVENT__MASK; +} +#define CP_EVENT_WRITE7_0_WRITE_SAMPLE_COUNT 0x00001000 +#define CP_EVENT_WRITE7_0_SAMPLE_COUNT_END_OFFSET 0x00002000 +#define CP_EVENT_WRITE7_0_WRITE_SAMPLE_COUNT_DIFF 0x00004000 +#define CP_EVENT_WRITE7_0_INC_BV_COUNT 0x00010000 +#define CP_EVENT_WRITE7_0_INC_BR_COUNT 0x00020000 +#define CP_EVENT_WRITE7_0_CLEAR_RENDER_RESOURCE 0x00040000 +#define CP_EVENT_WRITE7_0_CLEAR_LRZ_RESOURCE 0x00080000 +#define CP_EVENT_WRITE7_0_WRITE_SRC__MASK 0x00700000 +#define CP_EVENT_WRITE7_0_WRITE_SRC__SHIFT 20 +static inline uint32_t CP_EVENT_WRITE7_0_WRITE_SRC(enum event_write_src val) +{ + return ((val) << CP_EVENT_WRITE7_0_WRITE_SRC__SHIFT) & CP_EVENT_WRITE7_0_WRITE_SRC__MASK; +} +#define CP_EVENT_WRITE7_0_WRITE_DST__MASK 0x01000000 +#define CP_EVENT_WRITE7_0_WRITE_DST__SHIFT 24 +static inline uint32_t CP_EVENT_WRITE7_0_WRITE_DST(enum event_write_dst val) +{ + return ((val) << CP_EVENT_WRITE7_0_WRITE_DST__SHIFT) & CP_EVENT_WRITE7_0_WRITE_DST__MASK; +} +#define CP_EVENT_WRITE7_0_WRITE_ENABLED 0x08000000 + +#define REG_EV_DST_RAM_CP_EVENT_WRITE7_1 0x00000001 +#define EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__MASK 0xffffffff +#define EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__SHIFT 0 +static inline uint32_t EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO(uint32_t val) +{ + return ((val) << EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_1_ADDR_0_LO__MASK; +} + +#define REG_EV_DST_RAM_CP_EVENT_WRITE7_2 0x00000002 +#define EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__MASK 0xffffffff +#define EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__SHIFT 0 +static inline uint32_t EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI(uint32_t val) +{ + return ((val) << EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_2_ADDR_0_HI__MASK; +} + +#define REG_EV_DST_RAM_CP_EVENT_WRITE7_3 0x00000003 +#define EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK 0xffffffff +#define EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT 0 +static inline uint32_t EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0(uint32_t val) +{ + return ((val) << EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK; +} + +#define REG_EV_DST_RAM_CP_EVENT_WRITE7_4 0x00000004 +#define EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK 0xffffffff +#define EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT 0 +static inline uint32_t EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1(uint32_t val) +{ + return ((val) << EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT) & EV_DST_RAM_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK; +} + +#define REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_1 0x00000001 +#define EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__MASK 0xffffffff +#define EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__SHIFT 0 +static inline uint32_t EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0(uint32_t val) +{ + return ((val) << EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_1_ONCHIP_ADDR_0__MASK; +} + +#define REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_3 0x00000003 +#define EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK 0xffffffff +#define EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT 0 +static inline uint32_t EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0(uint32_t val) +{ + return ((val) << EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_3_PAYLOAD_0__MASK; +} + +#define REG_EV_DST_ONCHIP_CP_EVENT_WRITE7_4 0x00000004 +#define EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK 0xffffffff +#define EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT 0 +static inline uint32_t EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1(uint32_t val) +{ + return ((val) << EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__SHIFT) & EV_DST_ONCHIP_CP_EVENT_WRITE7_4_PAYLOAD_1__MASK; +} + #define REG_CP_BLIT_0 0x00000000 #define CP_BLIT_0_OP__MASK 0x0000000f #define CP_BLIT_0_OP__SHIFT 0 @@ -2125,7 +2319,6 @@ static inline uint32_t CP_EXEC_CS_3_NGROUPS_Z(uint32_t val) #define REG_A4XX_CP_EXEC_CS_INDIRECT_0 0x00000000 - #define REG_A4XX_CP_EXEC_CS_INDIRECT_1 0x00000001 #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__MASK 0xffffffff #define A4XX_CP_EXEC_CS_INDIRECT_1_ADDR__SHIFT 0 @@ -2154,7 +2347,6 @@ static inline uint32_t A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ(uint32_t val) return ((val) << A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__SHIFT) & A4XX_CP_EXEC_CS_INDIRECT_2_LOCALSIZEZ__MASK; } - #define REG_A5XX_CP_EXEC_CS_INDIRECT_1 0x00000001 #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__MASK 0xffffffff #define A5XX_CP_EXEC_CS_INDIRECT_1_ADDR_LO__SHIFT 0 @@ -2205,10 +2397,10 @@ static inline uint32_t A6XX_CP_SET_MARKER_0_MARKER(enum a6xx_marker val) return ((val) << A6XX_CP_SET_MARKER_0_MARKER__SHIFT) & A6XX_CP_SET_MARKER_0_MARKER__MASK; } -static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG_(uint32_t i0) { return 0x00000000 + 0x3*i0; } +#define REG_A6XX_CP_SET_PSEUDO_REG_(i0) (0x00000000 + 0x3*(i0)) static inline uint32_t REG_A6XX_CP_SET_PSEUDO_REG__0(uint32_t i0) { return 0x00000000 + 0x3*i0; } -#define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK 0x00000007 +#define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__MASK 0x000007ff #define A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG__SHIFT 0 static inline uint32_t A6XX_CP_SET_PSEUDO_REG__0_PSEUDO_REG(enum pseudo_reg val) { @@ -2238,6 +2430,18 @@ static inline uint32_t A6XX_CP_REG_TEST_0_REG(uint32_t val) { return ((val) << A6XX_CP_REG_TEST_0_REG__SHIFT) & A6XX_CP_REG_TEST_0_REG__MASK; } +#define A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__MASK 0x0003ffff +#define A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__SHIFT 0 +static inline uint32_t A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET(uint32_t val) +{ + return ((val) << A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__SHIFT) & A6XX_CP_REG_TEST_0_SCRATCH_MEM_OFFSET__MASK; +} +#define A6XX_CP_REG_TEST_0_SOURCE__MASK 0x00040000 +#define A6XX_CP_REG_TEST_0_SOURCE__SHIFT 18 +static inline uint32_t A6XX_CP_REG_TEST_0_SOURCE(enum source_type val) +{ + return ((val) << A6XX_CP_REG_TEST_0_SOURCE__SHIFT) & A6XX_CP_REG_TEST_0_SOURCE__MASK; +} #define A6XX_CP_REG_TEST_0_BIT__MASK 0x01f00000 #define A6XX_CP_REG_TEST_0_BIT__SHIFT 20 static inline uint32_t A6XX_CP_REG_TEST_0_BIT(uint32_t val) @@ -2270,9 +2474,14 @@ static inline uint32_t CP_COND_REG_EXEC_0_PRED_BIT(uint32_t val) { return ((val) << CP_COND_REG_EXEC_0_PRED_BIT__SHIFT) & CP_COND_REG_EXEC_0_PRED_BIT__MASK; } +#define CP_COND_REG_EXEC_0_SKIP_WAIT_FOR_ME 0x00800000 +#define CP_COND_REG_EXEC_0_ONCHIP_MEM 0x01000000 #define CP_COND_REG_EXEC_0_BINNING 0x02000000 #define CP_COND_REG_EXEC_0_GMEM 0x04000000 #define CP_COND_REG_EXEC_0_SYSMEM 0x08000000 +#define CP_COND_REG_EXEC_0_BV 0x02000000 +#define CP_COND_REG_EXEC_0_BR 0x04000000 +#define CP_COND_REG_EXEC_0_LPAC 0x08000000 #define CP_COND_REG_EXEC_0_MODE__MASK 0xf0000000 #define CP_COND_REG_EXEC_0_MODE__SHIFT 28 static inline uint32_t CP_COND_REG_EXEC_0_MODE(enum compare_mode val) @@ -2280,12 +2489,53 @@ static inline uint32_t CP_COND_REG_EXEC_0_MODE(enum compare_mode val) return ((val) << CP_COND_REG_EXEC_0_MODE__SHIFT) & CP_COND_REG_EXEC_0_MODE__MASK; } -#define REG_CP_COND_REG_EXEC_1 0x00000001 -#define CP_COND_REG_EXEC_1_DWORDS__MASK 0xffffffff -#define CP_COND_REG_EXEC_1_DWORDS__SHIFT 0 -static inline uint32_t CP_COND_REG_EXEC_1_DWORDS(uint32_t val) +#define REG_PRED_TEST_CP_COND_REG_EXEC_1 0x00000001 +#define PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__MASK 0x00ffffff +#define PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__SHIFT 0 +static inline uint32_t PRED_TEST_CP_COND_REG_EXEC_1_DWORDS(uint32_t val) +{ + return ((val) << PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & PRED_TEST_CP_COND_REG_EXEC_1_DWORDS__MASK; +} + +#define REG_REG_COMPARE_CP_COND_REG_EXEC_1 0x00000001 +#define REG_COMPARE_CP_COND_REG_EXEC_1_REG1__MASK 0x0003ffff +#define REG_COMPARE_CP_COND_REG_EXEC_1_REG1__SHIFT 0 +static inline uint32_t REG_COMPARE_CP_COND_REG_EXEC_1_REG1(uint32_t val) { - return ((val) << CP_COND_REG_EXEC_1_DWORDS__SHIFT) & CP_COND_REG_EXEC_1_DWORDS__MASK; + return ((val) << REG_COMPARE_CP_COND_REG_EXEC_1_REG1__SHIFT) & REG_COMPARE_CP_COND_REG_EXEC_1_REG1__MASK; +} +#define REG_COMPARE_CP_COND_REG_EXEC_1_ONCHIP_MEM 0x01000000 + +#define REG_RENDER_MODE_CP_COND_REG_EXEC_1 0x00000001 +#define RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK 0x00ffffff +#define RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT 0 +static inline uint32_t RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS(uint32_t val) +{ + return ((val) << RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & RENDER_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK; +} + +#define REG_REG_COMPARE_IMM_CP_COND_REG_EXEC_1 0x00000001 +#define REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__MASK 0xffffffff +#define REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__SHIFT 0 +static inline uint32_t REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM(uint32_t val) +{ + return ((val) << REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__SHIFT) & REG_COMPARE_IMM_CP_COND_REG_EXEC_1_IMM__MASK; +} + +#define REG_THREAD_MODE_CP_COND_REG_EXEC_1 0x00000001 +#define THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK 0x00ffffff +#define THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT 0 +static inline uint32_t THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS(uint32_t val) +{ + return ((val) << THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__SHIFT) & THREAD_MODE_CP_COND_REG_EXEC_1_DWORDS__MASK; +} + +#define REG_CP_COND_REG_EXEC_2 0x00000002 +#define CP_COND_REG_EXEC_2_DWORDS__MASK 0x00ffffff +#define CP_COND_REG_EXEC_2_DWORDS__SHIFT 0 +static inline uint32_t CP_COND_REG_EXEC_2_DWORDS(uint32_t val) +{ + return ((val) << CP_COND_REG_EXEC_2_DWORDS__SHIFT) & CP_COND_REG_EXEC_2_DWORDS__MASK; } #define REG_CP_COND_EXEC_0 0x00000000 @@ -2425,10 +2675,88 @@ static inline uint32_t CP_SMMU_TABLE_UPDATE_3_CONTEXTBANK(uint32_t val) #define REG_CP_START_BIN_BODY_DWORDS 0x00000004 #define REG_CP_WAIT_TIMESTAMP_0 0x00000000 +#define CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__MASK 0x00000003 +#define CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__SHIFT 0 +static inline uint32_t CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC(enum ts_wait_value_src val) +{ + return ((val) << CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__SHIFT) & CP_WAIT_TIMESTAMP_0_WAIT_VALUE_SRC__MASK; +} +#define CP_WAIT_TIMESTAMP_0_WAIT_DST__MASK 0x00000010 +#define CP_WAIT_TIMESTAMP_0_WAIT_DST__SHIFT 4 +static inline uint32_t CP_WAIT_TIMESTAMP_0_WAIT_DST(enum ts_wait_type val) +{ + return ((val) << CP_WAIT_TIMESTAMP_0_WAIT_DST__SHIFT) & CP_WAIT_TIMESTAMP_0_WAIT_DST__MASK; +} + +#define REG_TS_WAIT_RAM_CP_WAIT_TIMESTAMP_ADDR 0x00000001 -#define REG_CP_WAIT_TIMESTAMP_ADDR 0x00000001 +#define REG_TS_WAIT_ONCHIP_CP_WAIT_TIMESTAMP_ONCHIP_ADDR_0 0x00000001 -#define REG_CP_WAIT_TIMESTAMP_TIMESTAMP 0x00000003 +#define REG_CP_WAIT_TIMESTAMP_SRC_0 0x00000003 + +#define REG_CP_WAIT_TIMESTAMP_SRC_1 0x00000004 + +#define REG_CP_BV_BR_COUNT_OPS_0 0x00000000 +#define CP_BV_BR_COUNT_OPS_0_OP__MASK 0x0000000f +#define CP_BV_BR_COUNT_OPS_0_OP__SHIFT 0 +static inline uint32_t CP_BV_BR_COUNT_OPS_0_OP(enum pipe_count_op val) +{ + return ((val) << CP_BV_BR_COUNT_OPS_0_OP__SHIFT) & CP_BV_BR_COUNT_OPS_0_OP__MASK; +} + +#define REG_CP_BV_BR_COUNT_OPS_1 0x00000001 +#define CP_BV_BR_COUNT_OPS_1_BR_OFFSET__MASK 0x0000ffff +#define CP_BV_BR_COUNT_OPS_1_BR_OFFSET__SHIFT 0 +static inline uint32_t CP_BV_BR_COUNT_OPS_1_BR_OFFSET(uint32_t val) +{ + return ((val) << CP_BV_BR_COUNT_OPS_1_BR_OFFSET__SHIFT) & CP_BV_BR_COUNT_OPS_1_BR_OFFSET__MASK; +} + +#define REG_CP_MODIFY_TIMESTAMP_0 0x00000000 +#define CP_MODIFY_TIMESTAMP_0_ADD__MASK 0x000000ff +#define CP_MODIFY_TIMESTAMP_0_ADD__SHIFT 0 +static inline uint32_t CP_MODIFY_TIMESTAMP_0_ADD(uint32_t val) +{ + return ((val) << CP_MODIFY_TIMESTAMP_0_ADD__SHIFT) & CP_MODIFY_TIMESTAMP_0_ADD__MASK; +} +#define CP_MODIFY_TIMESTAMP_0_OP__MASK 0xf0000000 +#define CP_MODIFY_TIMESTAMP_0_OP__SHIFT 28 +static inline uint32_t CP_MODIFY_TIMESTAMP_0_OP(enum timestamp_op val) +{ + return ((val) << CP_MODIFY_TIMESTAMP_0_OP__SHIFT) & CP_MODIFY_TIMESTAMP_0_OP__MASK; +} + +#define REG_CP_MEM_TO_SCRATCH_MEM_0 0x00000000 +#define CP_MEM_TO_SCRATCH_MEM_0_CNT__MASK 0x0000003f +#define CP_MEM_TO_SCRATCH_MEM_0_CNT__SHIFT 0 +static inline uint32_t CP_MEM_TO_SCRATCH_MEM_0_CNT(uint32_t val) +{ + return ((val) << CP_MEM_TO_SCRATCH_MEM_0_CNT__SHIFT) & CP_MEM_TO_SCRATCH_MEM_0_CNT__MASK; +} + +#define REG_CP_MEM_TO_SCRATCH_MEM_1 0x00000001 +#define CP_MEM_TO_SCRATCH_MEM_1_OFFSET__MASK 0x0000003f +#define CP_MEM_TO_SCRATCH_MEM_1_OFFSET__SHIFT 0 +static inline uint32_t CP_MEM_TO_SCRATCH_MEM_1_OFFSET(uint32_t val) +{ + return ((val) << CP_MEM_TO_SCRATCH_MEM_1_OFFSET__SHIFT) & CP_MEM_TO_SCRATCH_MEM_1_OFFSET__MASK; +} + +#define REG_CP_MEM_TO_SCRATCH_MEM_2 0x00000002 +#define CP_MEM_TO_SCRATCH_MEM_2_SRC__MASK 0xffffffff +#define CP_MEM_TO_SCRATCH_MEM_2_SRC__SHIFT 0 +static inline uint32_t CP_MEM_TO_SCRATCH_MEM_2_SRC(uint32_t val) +{ + return ((val) << CP_MEM_TO_SCRATCH_MEM_2_SRC__SHIFT) & CP_MEM_TO_SCRATCH_MEM_2_SRC__MASK; +} + +#define REG_CP_MEM_TO_SCRATCH_MEM_3 0x00000003 +#define CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__MASK 0xffffffff +#define CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__SHIFT 0 +static inline uint32_t CP_MEM_TO_SCRATCH_MEM_3_SRC_HI(uint32_t val) +{ + return ((val) << CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__SHIFT) & CP_MEM_TO_SCRATCH_MEM_3_SRC_HI__MASK; +} #define REG_CP_THREAD_CONTROL_0 0x00000000 #define CP_THREAD_CONTROL_0_THREAD__MASK 0x00000003 @@ -2440,5 +2768,36 @@ static inline uint32_t CP_THREAD_CONTROL_0_THREAD(enum cp_thread val) #define CP_THREAD_CONTROL_0_CONCURRENT_BIN_DISABLE 0x08000000 #define CP_THREAD_CONTROL_0_SYNC_THREADS 0x80000000 +#define REG_CP_FIXED_STRIDE_DRAW_TABLE_IB_BASE 0x00000000 + +#define REG_CP_FIXED_STRIDE_DRAW_TABLE_2 0x00000002 +#define CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__MASK 0x00000fff +#define CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__SHIFT 0 +static inline uint32_t CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE(uint32_t val) +{ + return ((val) << CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_2_IB_SIZE__MASK; +} +#define CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__MASK 0xfff00000 +#define CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__SHIFT 20 +static inline uint32_t CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE(uint32_t val) +{ + return ((val) << CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_2_STRIDE__MASK; +} + +#define REG_CP_FIXED_STRIDE_DRAW_TABLE_3 0x00000003 +#define CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__MASK 0xffffffff +#define CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__SHIFT 0 +static inline uint32_t CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT(uint32_t val) +{ + return ((val) << CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__SHIFT) & CP_FIXED_STRIDE_DRAW_TABLE_3_COUNT__MASK; +} + +#define REG_CP_RESET_CONTEXT_STATE_0 0x00000000 +#define CP_RESET_CONTEXT_STATE_0_CLEAR_ON_CHIP_TS 0x00000001 +#define CP_RESET_CONTEXT_STATE_0_CLEAR_RESOURCE_TABLE 0x00000002 +#define CP_RESET_CONTEXT_STATE_0_CLEAR_GLOBAL_LOCAL_TS 0x00000004 + +#ifdef __cplusplus +#endif #endif /* ADRENO_PM4_XML */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h new file mode 100644 index 000000000000..424815e7fb7d --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h @@ -0,0 +1,291 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023. Linaro Inc. All rights reserved. + */ + +#ifndef _DPU_3_2_SDM660_H +#define _DPU_3_2_SDM660_H + +static const struct dpu_caps sdm660_dpu_caps = { + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages = 0x7, + .has_src_split = true, + .has_dim_layer = true, + .has_idle_pc = true, + .has_3d_merge = true, + .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, + .max_hdeci_exp = MAX_HORZ_DECIMATION, + .max_vdeci_exp = MAX_VERT_DECIMATION, +}; + +static const struct dpu_mdp_cfg sdm660_mdp = { + .name = "top_0", + .base = 0x0, .len = 0x458, + .features = BIT(DPU_MDP_VSYNC_SEL), + .clk_ctrls = { + [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, + [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, + [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 }, + }, +}; + +static const struct dpu_ctl_cfg sdm660_ctl[] = { + { + .name = "ctl_0", .id = CTL_0, + .base = 0x1000, .len = 0x94, + .features = BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name = "ctl_1", .id = CTL_1, + .base = 0x1200, .len = 0x94, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name = "ctl_2", .id = CTL_2, + .base = 0x1400, .len = 0x94, + .features = BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name = "ctl_3", .id = CTL_3, + .base = 0x1600, .len = 0x94, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name = "ctl_4", .id = CTL_4, + .base = 0x1800, .len = 0x94, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, +}; + +static const struct dpu_sspp_cfg sdm660_sspp[] = { + { + .name = "sspp_0", .id = SSPP_VIG0, + .base = 0x4000, .len = 0x1ac, + .features = VIG_MSM8998_MASK, + .sblk = &dpu_vig_sblk_qseed3_1_2, + .xin_id = 0, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, + }, { + .name = "sspp_1", .id = SSPP_VIG1, + .base = 0x6000, .len = 0x1ac, + .features = VIG_MSM8998_MASK, + .sblk = &dpu_vig_sblk_qseed3_1_2, + .xin_id = 4, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG1, + }, { + .name = "sspp_8", .id = SSPP_DMA0, + .base = 0x24000, .len = 0x1ac, + .features = DMA_MSM8998_MASK, + .sblk = &dpu_dma_sblk, + .xin_id = 1, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA0, + }, { + .name = "sspp_9", .id = SSPP_DMA1, + .base = 0x26000, .len = 0x1ac, + .features = DMA_MSM8998_MASK, + .sblk = &dpu_dma_sblk, + .xin_id = 5, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA1, + }, { + .name = "sspp_10", .id = SSPP_DMA2, + .base = 0x28000, .len = 0x1ac, + .features = DMA_CURSOR_MSM8998_MASK, + .sblk = &dpu_dma_sblk, + .xin_id = 9, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA2, + }, +}; + +static const struct dpu_lm_cfg sdm660_lm[] = { + { + .name = "lm_0", .id = LM_0, + .base = 0x44000, .len = 0x320, + .features = MIXER_MSM8998_MASK, + .sblk = &msm8998_lm_sblk, + .lm_pair = LM_1, + .pingpong = PINGPONG_0, + .dspp = DSPP_0, + }, { + .name = "lm_1", .id = LM_1, + .base = 0x45000, .len = 0x320, + .features = MIXER_MSM8998_MASK, + .sblk = &msm8998_lm_sblk, + .lm_pair = LM_0, + .pingpong = PINGPONG_1, + .dspp = DSPP_1, + }, { + .name = "lm_2", .id = LM_2, + .base = 0x46000, .len = 0x320, + .features = MIXER_MSM8998_MASK, + .sblk = &msm8998_lm_sblk, + .lm_pair = LM_5, + .pingpong = PINGPONG_2, + }, { + .name = "lm_5", .id = LM_5, + .base = 0x49000, .len = 0x320, + .features = MIXER_MSM8998_MASK, + .sblk = &msm8998_lm_sblk, + .lm_pair = LM_2, + .pingpong = PINGPONG_3, + }, +}; + +static const struct dpu_pingpong_cfg sdm660_pp[] = { + { + .name = "pingpong_0", .id = PINGPONG_0, + .base = 0x70000, .len = 0xd4, + .features = PINGPONG_SDM845_TE2_MASK, + .sblk = &sdm845_pp_sblk_te, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), + }, { + .name = "pingpong_1", .id = PINGPONG_1, + .base = 0x70800, .len = 0xd4, + .features = PINGPONG_SDM845_TE2_MASK, + .sblk = &sdm845_pp_sblk_te, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), + }, { + .name = "pingpong_2", .id = PINGPONG_2, + .base = 0x71000, .len = 0xd4, + .features = PINGPONG_SDM845_MASK, + .sblk = &sdm845_pp_sblk, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14), + }, { + .name = "pingpong_3", .id = PINGPONG_3, + .base = 0x71800, .len = 0xd4, + .features = PINGPONG_SDM845_MASK, + .sblk = &sdm845_pp_sblk, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15), + }, +}; + +static const struct dpu_dsc_cfg sdm660_dsc[] = { + { + .name = "dsc_0", .id = DSC_0, + .base = 0x80000, .len = 0x140, + }, { + .name = "dsc_1", .id = DSC_1, + .base = 0x80400, .len = 0x140, + }, +}; + +static const struct dpu_dspp_cfg sdm660_dspp[] = { + { + .name = "dspp_0", .id = DSPP_0, + .base = 0x54000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &msm8998_dspp_sblk, + }, { + .name = "dspp_1", .id = DSPP_1, + .base = 0x56000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &msm8998_dspp_sblk, + }, +}; + +static const struct dpu_intf_cfg sdm660_intf[] = { + { + .name = "intf_0", .id = INTF_0, + .base = 0x6a000, .len = 0x280, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case = 21, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + .intr_tear_rd_ptr = -1, + }, { + .name = "intf_1", .id = INTF_1, + .base = 0x6a800, .len = 0x280, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case = 21, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr = -1, + }, { + .name = "intf_2", .id = INTF_2, + .base = 0x6b000, .len = 0x280, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_1, + .prog_fetch_lines_worst_case = 21, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + .intr_tear_rd_ptr = -1, + }, +}; + +static const struct dpu_perf_cfg sdm660_perf_data = { + .max_bw_low = 6600000, + .max_bw_high = 6600000, + .min_core_ib = 3100000, + .min_llcc_ib = 800000, + .min_dram_ib = 800000, + .undersized_prefill_lines = 2, + .xtra_prefill_lines = 2, + .dest_scale_prefill_lines = 3, + .macrotile_prefill_lines = 4, + .yuv_nv12_prefill_lines = 8, + .linear_prefill_lines = 1, + .downscaling_prefill_lines = 1, + .amortizable_threshold = 25, + .min_prefill_lines = 25, + .danger_lut_tbl = {0xf, 0xffff, 0x0}, + .safe_lut_tbl = {0xfffc, 0xff00, 0xffff}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(msm8998_qos_linear), + .entries = msm8998_qos_linear + }, + {.nentry = ARRAY_SIZE(msm8998_qos_macrotile), + .entries = msm8998_qos_macrotile + }, + {.nentry = ARRAY_SIZE(msm8998_qos_nrt), + .entries = msm8998_qos_nrt + }, + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, + .clk_inefficiency_factor = 200, + .bw_inefficiency_factor = 120, +}; + +static const struct dpu_mdss_version sdm660_mdss_ver = { + .core_major_ver = 3, + .core_minor_ver = 2, +}; + +const struct dpu_mdss_cfg dpu_sdm660_cfg = { + .mdss_ver = &sdm660_mdss_ver, + .caps = &sdm660_dpu_caps, + .mdp = &sdm660_mdp, + .ctl_count = ARRAY_SIZE(sdm660_ctl), + .ctl = sdm660_ctl, + .sspp_count = ARRAY_SIZE(sdm660_sspp), + .sspp = sdm660_sspp, + .mixer_count = ARRAY_SIZE(sdm660_lm), + .mixer = sdm660_lm, + .dspp_count = ARRAY_SIZE(sdm660_dspp), + .dspp = sdm660_dspp, + .pingpong_count = ARRAY_SIZE(sdm660_pp), + .pingpong = sdm660_pp, + .dsc_count = ARRAY_SIZE(sdm660_dsc), + .dsc = sdm660_dsc, + .intf_count = ARRAY_SIZE(sdm660_intf), + .intf = sdm660_intf, + .vbif_count = ARRAY_SIZE(msm8998_vbif), + .vbif = msm8998_vbif, + .perf = &sdm660_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h new file mode 100644 index 000000000000..df01227fc364 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h @@ -0,0 +1,225 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023. Linaro Inc. All rights reserved. + */ + +#ifndef _DPU_3_3_SDM630_H +#define _DPU_3_3_SDM630_H + +static const struct dpu_caps sdm630_dpu_caps = { + .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, + .max_mixer_blendstages = 0x7, + .has_src_split = true, + .has_dim_layer = true, + .has_idle_pc = true, + .has_3d_merge = true, + .max_linewidth = DEFAULT_DPU_LINE_WIDTH, + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, + .max_hdeci_exp = MAX_HORZ_DECIMATION, + .max_vdeci_exp = MAX_VERT_DECIMATION, +}; + +static const struct dpu_mdp_cfg sdm630_mdp = { + .name = "top_0", + .base = 0x0, .len = 0x458, + .features = BIT(DPU_MDP_VSYNC_SEL), + .clk_ctrls = { + [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, + [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, + [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, + [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 }, + }, +}; + +static const struct dpu_ctl_cfg sdm630_ctl[] = { + { + .name = "ctl_0", .id = CTL_0, + .base = 0x1000, .len = 0x94, + .features = BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name = "ctl_1", .id = CTL_1, + .base = 0x1200, .len = 0x94, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name = "ctl_2", .id = CTL_2, + .base = 0x1400, .len = 0x94, + .features = BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name = "ctl_3", .id = CTL_3, + .base = 0x1600, .len = 0x94, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name = "ctl_4", .id = CTL_4, + .base = 0x1800, .len = 0x94, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, +}; + +static const struct dpu_sspp_cfg sdm630_sspp[] = { + { + .name = "sspp_0", .id = SSPP_VIG0, + .base = 0x4000, .len = 0x1ac, + .features = VIG_MSM8998_MASK, + .sblk = &dpu_vig_sblk_qseed3_1_2, + .xin_id = 0, + .type = SSPP_TYPE_VIG, + .clk_ctrl = DPU_CLK_CTRL_VIG0, + }, { + .name = "sspp_8", .id = SSPP_DMA0, + .base = 0x24000, .len = 0x1ac, + .features = DMA_MSM8998_MASK, + .sblk = &dpu_dma_sblk, + .xin_id = 1, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA0, + }, { + .name = "sspp_9", .id = SSPP_DMA1, + .base = 0x26000, .len = 0x1ac, + .features = DMA_MSM8998_MASK, + .sblk = &dpu_dma_sblk, + .xin_id = 5, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA1, + }, { + .name = "sspp_10", .id = SSPP_DMA2, + .base = 0x28000, .len = 0x1ac, + .features = DMA_CURSOR_MSM8998_MASK, + .sblk = &dpu_dma_sblk, + .xin_id = 9, + .type = SSPP_TYPE_DMA, + .clk_ctrl = DPU_CLK_CTRL_DMA2, + }, +}; + +static const struct dpu_lm_cfg sdm630_lm[] = { + { + .name = "lm_0", .id = LM_0, + .base = 0x44000, .len = 0x320, + .features = MIXER_MSM8998_MASK, + .sblk = &msm8998_lm_sblk, + .pingpong = PINGPONG_0, + .dspp = DSPP_0, + }, { + .name = "lm_2", .id = LM_2, + .base = 0x46000, .len = 0x320, + .features = MIXER_MSM8998_MASK, + .sblk = &msm8998_lm_sblk, + .pingpong = PINGPONG_2, + }, +}; + +static const struct dpu_pingpong_cfg sdm630_pp[] = { + { + .name = "pingpong_0", .id = PINGPONG_0, + .base = 0x70000, .len = 0xd4, + .features = PINGPONG_SDM845_TE2_MASK, + .sblk = &sdm845_pp_sblk_te, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), + }, { + .name = "pingpong_2", .id = PINGPONG_2, + .base = 0x71000, .len = 0xd4, + .features = PINGPONG_SDM845_MASK, + .sblk = &sdm845_pp_sblk, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14), + }, +}; + +static const struct dpu_dspp_cfg sdm630_dspp[] = { + { + .name = "dspp_0", .id = DSPP_0, + .base = 0x54000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &msm8998_dspp_sblk, + }, +}; + +static const struct dpu_intf_cfg sdm630_intf[] = { + { + .name = "intf_0", .id = INTF_0, + .base = 0x6a000, .len = 0x280, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case = 21, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + .intr_tear_rd_ptr = -1, + }, { + .name = "intf_1", .id = INTF_1, + .base = 0x6a800, .len = 0x280, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case = 21, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr = -1, + }, +}; + +static const struct dpu_perf_cfg sdm630_perf_data = { + .max_bw_low = 4100000, + .max_bw_high = 4100000, + .min_core_ib = 3200000, + .min_llcc_ib = 800000, + .min_dram_ib = 800000, + .undersized_prefill_lines = 2, + .xtra_prefill_lines = 2, + .dest_scale_prefill_lines = 3, + .macrotile_prefill_lines = 4, + .yuv_nv12_prefill_lines = 8, + .linear_prefill_lines = 1, + .downscaling_prefill_lines = 1, + .amortizable_threshold = 25, + .min_prefill_lines = 25, + .danger_lut_tbl = {0xf, 0xffff, 0x0}, + .safe_lut_tbl = {0xfffc, 0xff00, 0xffff}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(msm8998_qos_linear), + .entries = msm8998_qos_linear + }, + {.nentry = ARRAY_SIZE(msm8998_qos_macrotile), + .entries = msm8998_qos_macrotile + }, + {.nentry = ARRAY_SIZE(msm8998_qos_nrt), + .entries = msm8998_qos_nrt + }, + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, + .clk_inefficiency_factor = 200, + .bw_inefficiency_factor = 120, +}; + +static const struct dpu_mdss_version sdm630_mdss_ver = { + .core_major_ver = 3, + .core_minor_ver = 3, +}; + +const struct dpu_mdss_cfg dpu_sdm630_cfg = { + .mdss_ver = &sdm630_mdss_ver, + .caps = &sdm630_dpu_caps, + .mdp = &sdm630_mdp, + .ctl_count = ARRAY_SIZE(sdm630_ctl), + .ctl = sdm630_ctl, + .sspp_count = ARRAY_SIZE(sdm630_sspp), + .sspp = sdm630_sspp, + .mixer_count = ARRAY_SIZE(sdm630_lm), + .mixer = sdm630_lm, + .dspp_count = ARRAY_SIZE(sdm630_dspp), + .dspp = sdm630_dspp, + .pingpong_count = ARRAY_SIZE(sdm630_pp), + .pingpong = sdm630_pp, + .intf_count = ARRAY_SIZE(sdm630_intf), + .intf = sdm630_intf, + .vbif_count = ARRAY_SIZE(msm8998_vbif), + .vbif = msm8998_vbif, + .perf = &sdm630_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h new file mode 100644 index 000000000000..9a9f7092c526 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -0,0 +1,449 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023, Linaro Limited + */ + +#ifndef _DPU_9_2_X1E80100_H +#define _DPU_9_2_X1E80100_H + +static const struct dpu_caps x1e80100_dpu_caps = { + .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages = 0xb, + .has_src_split = true, + .has_dim_layer = true, + .has_idle_pc = true, + .has_3d_merge = true, + .max_linewidth = 5120, + .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_mdp_cfg x1e80100_mdp = { + .name = "top_0", + .base = 0, .len = 0x494, + .features = BIT(DPU_MDP_PERIPH_0_REMOVED), + .clk_ctrls = { + [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, + }, +}; + +/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ +static const struct dpu_ctl_cfg x1e80100_ctl[] = { + { + .name = "ctl_0", .id = CTL_0, + .base = 0x15000, .len = 0x290, + .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name = "ctl_1", .id = CTL_1, + .base = 0x16000, .len = 0x290, + .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY), + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name = "ctl_2", .id = CTL_2, + .base = 0x17000, .len = 0x290, + .features = CTL_SM8550_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name = "ctl_3", .id = CTL_3, + .base = 0x18000, .len = 0x290, + .features = CTL_SM8550_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name = "ctl_4", .id = CTL_4, + .base = 0x19000, .len = 0x290, + .features = CTL_SM8550_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, { + .name = "ctl_5", .id = CTL_5, + .base = 0x1a000, .len = 0x290, + .features = CTL_SM8550_MASK, + .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + +static const struct dpu_sspp_cfg x1e80100_sspp[] = { + { + .name = "sspp_0", .id = SSPP_VIG0, + .base = 0x4000, .len = 0x344, + .features = VIG_SDM845_MASK_SDMA, + .sblk = &dpu_vig_sblk_qseed3_3_3, + .xin_id = 0, + .type = SSPP_TYPE_VIG, + }, { + .name = "sspp_1", .id = SSPP_VIG1, + .base = 0x6000, .len = 0x344, + .features = VIG_SDM845_MASK_SDMA, + .sblk = &dpu_vig_sblk_qseed3_3_3, + .xin_id = 4, + .type = SSPP_TYPE_VIG, + }, { + .name = "sspp_2", .id = SSPP_VIG2, + .base = 0x8000, .len = 0x344, + .features = VIG_SDM845_MASK_SDMA, + .sblk = &dpu_vig_sblk_qseed3_3_3, + .xin_id = 8, + .type = SSPP_TYPE_VIG, + }, { + .name = "sspp_3", .id = SSPP_VIG3, + .base = 0xa000, .len = 0x344, + .features = VIG_SDM845_MASK_SDMA, + .sblk = &dpu_vig_sblk_qseed3_3_3, + .xin_id = 12, + .type = SSPP_TYPE_VIG, + }, { + .name = "sspp_8", .id = SSPP_DMA0, + .base = 0x24000, .len = 0x344, + .features = DMA_SDM845_MASK_SDMA, + .sblk = &dpu_dma_sblk, + .xin_id = 1, + .type = SSPP_TYPE_DMA, + }, { + .name = "sspp_9", .id = SSPP_DMA1, + .base = 0x26000, .len = 0x344, + .features = DMA_SDM845_MASK_SDMA, + .sblk = &dpu_dma_sblk, + .xin_id = 5, + .type = SSPP_TYPE_DMA, + }, { + .name = "sspp_10", .id = SSPP_DMA2, + .base = 0x28000, .len = 0x344, + .features = DMA_SDM845_MASK_SDMA, + .sblk = &dpu_dma_sblk, + .xin_id = 9, + .type = SSPP_TYPE_DMA, + }, { + .name = "sspp_11", .id = SSPP_DMA3, + .base = 0x2a000, .len = 0x344, + .features = DMA_SDM845_MASK_SDMA, + .sblk = &dpu_dma_sblk, + .xin_id = 13, + .type = SSPP_TYPE_DMA, + }, { + .name = "sspp_12", .id = SSPP_DMA4, + .base = 0x2c000, .len = 0x344, + .features = DMA_CURSOR_SDM845_MASK_SDMA, + .sblk = &dpu_dma_sblk, + .xin_id = 14, + .type = SSPP_TYPE_DMA, + }, { + .name = "sspp_13", .id = SSPP_DMA5, + .base = 0x2e000, .len = 0x344, + .features = DMA_CURSOR_SDM845_MASK_SDMA, + .sblk = &dpu_dma_sblk, + .xin_id = 15, + .type = SSPP_TYPE_DMA, + }, +}; + +static const struct dpu_lm_cfg x1e80100_lm[] = { + { + .name = "lm_0", .id = LM_0, + .base = 0x44000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_1, + .pingpong = PINGPONG_0, + .dspp = DSPP_0, + }, { + .name = "lm_1", .id = LM_1, + .base = 0x45000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_0, + .pingpong = PINGPONG_1, + .dspp = DSPP_1, + }, { + .name = "lm_2", .id = LM_2, + .base = 0x46000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_3, + .pingpong = PINGPONG_2, + }, { + .name = "lm_3", .id = LM_3, + .base = 0x47000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_2, + .pingpong = PINGPONG_3, + }, { + .name = "lm_4", .id = LM_4, + .base = 0x48000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_5, + .pingpong = PINGPONG_4, + }, { + .name = "lm_5", .id = LM_5, + .base = 0x49000, .len = 0x320, + .features = MIXER_SDM845_MASK, + .sblk = &sdm845_lm_sblk, + .lm_pair = LM_4, + .pingpong = PINGPONG_5, + }, +}; + +static const struct dpu_dspp_cfg x1e80100_dspp[] = { + { + .name = "dspp_0", .id = DSPP_0, + .base = 0x54000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, { + .name = "dspp_1", .id = DSPP_1, + .base = 0x56000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, { + .name = "dspp_2", .id = DSPP_2, + .base = 0x58000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, { + .name = "dspp_3", .id = DSPP_3, + .base = 0x5a000, .len = 0x1800, + .features = DSPP_SC7180_MASK, + .sblk = &sdm845_dspp_sblk, + }, +}; + +static const struct dpu_pingpong_cfg x1e80100_pp[] = { + { + .name = "pingpong_0", .id = PINGPONG_0, + .base = 0x69000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_0, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + }, { + .name = "pingpong_1", .id = PINGPONG_1, + .base = 0x6a000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_0, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + }, { + .name = "pingpong_2", .id = PINGPONG_2, + .base = 0x6b000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_1, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + }, { + .name = "pingpong_3", .id = PINGPONG_3, + .base = 0x6c000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_1, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + }, { + .name = "pingpong_4", .id = PINGPONG_4, + .base = 0x6d000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_2, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + }, { + .name = "pingpong_5", .id = PINGPONG_5, + .base = 0x6e000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_2, + .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + }, { + .name = "pingpong_6", .id = PINGPONG_6, + .base = 0x66000, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_3, + }, { + .name = "pingpong_7", .id = PINGPONG_7, + .base = 0x66400, .len = 0, + .features = BIT(DPU_PINGPONG_DITHER), + .sblk = &sc7280_pp_sblk, + .merge_3d = MERGE_3D_3, + }, +}; + +static const struct dpu_merge_3d_cfg x1e80100_merge_3d[] = { + { + .name = "merge_3d_0", .id = MERGE_3D_0, + .base = 0x4e000, .len = 0x8, + }, { + .name = "merge_3d_1", .id = MERGE_3D_1, + .base = 0x4f000, .len = 0x8, + }, { + .name = "merge_3d_2", .id = MERGE_3D_2, + .base = 0x50000, .len = 0x8, + }, { + .name = "merge_3d_3", .id = MERGE_3D_3, + .base = 0x66700, .len = 0x8, + }, +}; + +/* + * NOTE: Each display compression engine (DCE) contains dual hard + * slice DSC encoders so both share same base address but with + * its own different sub block address. + */ +static const struct dpu_dsc_cfg x1e80100_dsc[] = { + { + .name = "dce_0_0", .id = DSC_0, + .base = 0x80000, .len = 0x4, + .features = BIT(DPU_DSC_HW_REV_1_2), + .sblk = &dsc_sblk_0, + }, { + .name = "dce_0_1", .id = DSC_1, + .base = 0x80000, .len = 0x4, + .features = BIT(DPU_DSC_HW_REV_1_2), + .sblk = &dsc_sblk_1, + }, { + .name = "dce_1_0", .id = DSC_2, + .base = 0x81000, .len = 0x4, + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .sblk = &dsc_sblk_0, + }, { + .name = "dce_1_1", .id = DSC_3, + .base = 0x81000, .len = 0x4, + .features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN), + .sblk = &dsc_sblk_1, + }, +}; + +static const struct dpu_wb_cfg x1e80100_wb[] = { + { + .name = "wb_2", .id = WB_2, + .base = 0x65000, .len = 0x2c8, + .features = WB_SM8250_MASK, + .format_list = wb2_formats_rgb, + .num_formats = ARRAY_SIZE(wb2_formats_rgb), + .xin_id = 6, + .vbif_idx = VBIF_RT, + .maxlinewidth = 4096, + .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), + }, +}; + +static const struct dpu_intf_cfg x1e80100_intf[] = { + { + .name = "intf_0", .id = INTF_0, + .base = 0x34000, .len = 0x280, + .features = INTF_SC7280_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + }, { + .name = "intf_1", .id = INTF_1, + .base = 0x35000, .len = 0x300, + .features = INTF_SC7280_MASK, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), + }, { + .name = "intf_2", .id = INTF_2, + .base = 0x36000, .len = 0x300, + .features = INTF_SC7280_MASK, + .type = INTF_DSI, + .controller_id = MSM_DSI_CONTROLLER_1, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), + }, { + .name = "intf_3", .id = INTF_3, + .base = 0x37000, .len = 0x280, + .features = INTF_SC7280_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_1, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), + }, { + .name = "intf_4", .id = INTF_4, + .base = 0x38000, .len = 0x280, + .features = INTF_SC7280_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_2, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21), + }, { + .name = "intf_5", .id = INTF_5, + .base = 0x39000, .len = 0x280, + .features = INTF_SC7280_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_3, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23), + }, +}; + +static const struct dpu_perf_cfg x1e80100_perf_data = { + .max_bw_low = 13600000, + .max_bw_high = 18200000, + .min_core_ib = 2500000, + .min_llcc_ib = 0, + .min_dram_ib = 800000, + .min_prefill_lines = 35, + /* FIXME: lut tables */ + .danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0}, + .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, + .qos_lut_tbl = { + {.nentry = ARRAY_SIZE(sc7180_qos_linear), + .entries = sc7180_qos_linear + }, + {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), + .entries = sc7180_qos_macrotile + }, + {.nentry = ARRAY_SIZE(sc7180_qos_nrt), + .entries = sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg = { + {.rd_enable = 1, .wr_enable = 1}, + {.rd_enable = 1, .wr_enable = 0} + }, + .clk_inefficiency_factor = 105, + .bw_inefficiency_factor = 120, +}; + +static const struct dpu_mdss_version x1e80100_mdss_ver = { + .core_major_ver = 9, + .core_minor_ver = 2, +}; + +const struct dpu_mdss_cfg dpu_x1e80100_cfg = { + .mdss_ver = &x1e80100_mdss_ver, + .caps = &x1e80100_dpu_caps, + .mdp = &x1e80100_mdp, + .ctl_count = ARRAY_SIZE(x1e80100_ctl), + .ctl = x1e80100_ctl, + .sspp_count = ARRAY_SIZE(x1e80100_sspp), + .sspp = x1e80100_sspp, + .mixer_count = ARRAY_SIZE(x1e80100_lm), + .mixer = x1e80100_lm, + .dspp_count = ARRAY_SIZE(x1e80100_dspp), + .dspp = x1e80100_dspp, + .pingpong_count = ARRAY_SIZE(x1e80100_pp), + .pingpong = x1e80100_pp, + .dsc_count = ARRAY_SIZE(x1e80100_dsc), + .dsc = x1e80100_dsc, + .merge_3d_count = ARRAY_SIZE(x1e80100_merge_3d), + .merge_3d = x1e80100_merge_3d, + .wb_count = ARRAY_SIZE(x1e80100_wb), + .wb = x1e80100_wb, + .intf_count = ARRAY_SIZE(x1e80100_intf), + .intf = x1e80100_intf, + .vbif_count = ARRAY_SIZE(sm8550_vbif), + .vbif = sm8550_vbif, + .perf = &x1e80100_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 6a4b489d44e5..9a14d2232e4a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -126,6 +126,8 @@ enum dpu_enc_rc_states { * @base: drm_encoder base class for registration with DRM * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes * @enabled: True if the encoder is active, protected by enc_lock + * @commit_done_timedout: True if there has been a timeout on commit after + * enabling the encoder. * @num_phys_encs: Actual number of physical encoders contained. * @phys_encs: Container of physical encoders managed. * @cur_master: Pointer to the current master in this mode. Optimization @@ -172,6 +174,7 @@ struct dpu_encoder_virt { spinlock_t enc_spinlock; bool enabled; + bool commit_done_timedout; unsigned int num_phys_encs; struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL]; @@ -218,12 +221,66 @@ static u32 dither_matrix[DITHER_MATRIX_SZ] = { 15, 7, 13, 5, 3, 11, 1, 9, 12, 4, 14, 6, 0, 8, 2, 10 }; +u32 dpu_encoder_get_drm_fmt(struct dpu_encoder_phys *phys_enc) +{ + struct drm_encoder *drm_enc; + struct dpu_encoder_virt *dpu_enc; + struct drm_display_info *info; + struct drm_display_mode *mode; + + drm_enc = phys_enc->parent; + dpu_enc = to_dpu_encoder_virt(drm_enc); + info = &dpu_enc->connector->display_info; + mode = &phys_enc->cached_mode; + + if (drm_mode_is_420_only(info, mode)) + return DRM_FORMAT_YUV420; + + return DRM_FORMAT_RGB888; +} + +bool dpu_encoder_needs_periph_flush(struct dpu_encoder_phys *phys_enc) +{ + struct drm_encoder *drm_enc; + struct dpu_encoder_virt *dpu_enc; + struct msm_display_info *disp_info; + struct msm_drm_private *priv; + struct drm_display_mode *mode; + + drm_enc = phys_enc->parent; + dpu_enc = to_dpu_encoder_virt(drm_enc); + disp_info = &dpu_enc->disp_info; + priv = drm_enc->dev->dev_private; + mode = &phys_enc->cached_mode; + + return phys_enc->hw_intf->cap->type == INTF_DP && + msm_dp_needs_periph_flush(priv->dp[disp_info->h_tile_instance[0]], mode); +} bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc) { + const struct dpu_encoder_virt *dpu_enc; + struct msm_drm_private *priv = drm_enc->dev->dev_private; + const struct msm_display_info *disp_info; + int index; + + dpu_enc = to_dpu_encoder_virt(drm_enc); + disp_info = &dpu_enc->disp_info; + index = disp_info->h_tile_instance[0]; + + if (disp_info->intf_type == INTF_DP) + return msm_dp_wide_bus_available(priv->dp[index]); + else if (disp_info->intf_type == INTF_DSI) + return msm_dsi_wide_bus_enabled(priv->dsi[index]); + + return false; +} + +bool dpu_encoder_is_dsc_enabled(const struct drm_encoder *drm_enc) +{ const struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc); - return dpu_enc->wide_bus_en; + return dpu_enc->dsc ? true : false; } int dpu_encoder_get_crc_values_cnt(const struct drm_encoder *drm_enc) @@ -581,10 +638,10 @@ static int dpu_encoder_virt_atomic_check( struct dpu_kms *dpu_kms; struct drm_display_mode *adj_mode; struct msm_display_topology topology; + struct msm_display_info *disp_info; struct dpu_global_state *global_state; struct drm_framebuffer *fb; struct drm_dsc_config *dsc; - int i = 0; int ret = 0; if (!drm_enc || !crtc_state || !conn_state) { @@ -597,6 +654,7 @@ static int dpu_encoder_virt_atomic_check( DPU_DEBUG_ENC(dpu_enc, "\n"); priv = drm_enc->dev->dev_private; + disp_info = &dpu_enc->disp_info; dpu_kms = to_dpu_kms(priv->kms); adj_mode = &crtc_state->adjusted_mode; global_state = dpu_kms_get_global_state(crtc_state->state); @@ -605,40 +663,29 @@ static int dpu_encoder_virt_atomic_check( trace_dpu_enc_atomic_check(DRMID(drm_enc)); - /* perform atomic check on the first physical encoder (master) */ - for (i = 0; i < dpu_enc->num_phys_encs; i++) { - struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; - - if (phys->ops.atomic_check) - ret = phys->ops.atomic_check(phys, crtc_state, - conn_state); - if (ret) { - DPU_ERROR_ENC(dpu_enc, - "mode unsupported, phys idx %d\n", i); - return ret; - } - } - dsc = dpu_encoder_get_dsc_config(drm_enc); topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode, crtc_state, dsc); /* - * Use CDM only for writeback at the moment as other interfaces cannot handle it. - * if writeback itself cannot handle cdm for some reason it will fail in its atomic_check() + * Use CDM only for writeback or DP at the moment as other interfaces cannot handle it. + * If writeback itself cannot handle cdm for some reason it will fail in its atomic_check() * earlier. */ - if (dpu_enc->disp_info.intf_type == INTF_WB && conn_state->writeback_job) { + if (disp_info->intf_type == INTF_WB && conn_state->writeback_job) { fb = conn_state->writeback_job->fb; if (fb && DPU_FORMAT_IS_YUV(to_dpu_format(msm_framebuffer_format(fb)))) topology.needs_cdm = true; - if (topology.needs_cdm && !dpu_enc->cur_master->hw_cdm) - crtc_state->mode_changed = true; - else if (!topology.needs_cdm && dpu_enc->cur_master->hw_cdm) - crtc_state->mode_changed = true; + } else if (disp_info->intf_type == INTF_DP) { + if (msm_dp_is_yuv_420_enabled(priv->dp[disp_info->h_tile_instance[0]], adj_mode)) + topology.needs_cdm = true; } + if (topology.needs_cdm && !dpu_enc->cur_master->hw_cdm) + crtc_state->mode_changed = true; + else if (!topology.needs_cdm && dpu_enc->cur_master->hw_cdm) + crtc_state->mode_changed = true; /* * Release and Allocate resources on every modeset * Dont allocate when active is false. @@ -714,7 +761,7 @@ static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc, } } -static void _dpu_encoder_irq_control(struct drm_encoder *drm_enc, bool enable) +static void _dpu_encoder_irq_enable(struct drm_encoder *drm_enc) { struct dpu_encoder_virt *dpu_enc; int i; @@ -726,18 +773,35 @@ static void _dpu_encoder_irq_control(struct drm_encoder *drm_enc, bool enable) dpu_enc = to_dpu_encoder_virt(drm_enc); - DPU_DEBUG_ENC(dpu_enc, "enable:%d\n", enable); + DPU_DEBUG_ENC(dpu_enc, "\n"); for (i = 0; i < dpu_enc->num_phys_encs; i++) { struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; - if (phys->ops.irq_control) - phys->ops.irq_control(phys, enable); + phys->ops.irq_enable(phys); + } +} + +static void _dpu_encoder_irq_disable(struct drm_encoder *drm_enc) +{ + struct dpu_encoder_virt *dpu_enc; + int i; + + if (!drm_enc) { + DPU_ERROR("invalid encoder\n"); + return; } + dpu_enc = to_dpu_encoder_virt(drm_enc); + + DPU_DEBUG_ENC(dpu_enc, "\n"); + for (i = 0; i < dpu_enc->num_phys_encs; i++) { + struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; + + phys->ops.irq_disable(phys); + } } -static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc, - bool enable) +static void _dpu_encoder_resource_enable(struct drm_encoder *drm_enc) { struct msm_drm_private *priv; struct dpu_kms *dpu_kms; @@ -747,28 +811,42 @@ static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc, priv = drm_enc->dev->dev_private; dpu_kms = to_dpu_kms(priv->kms); - trace_dpu_enc_rc_helper(DRMID(drm_enc), enable); + trace_dpu_enc_rc_enable(DRMID(drm_enc)); if (!dpu_enc->cur_master) { DPU_ERROR("encoder master not set\n"); return; } - if (enable) { - /* enable DPU core clks */ - pm_runtime_get_sync(&dpu_kms->pdev->dev); + /* enable DPU core clks */ + pm_runtime_get_sync(&dpu_kms->pdev->dev); - /* enable all the irq */ - _dpu_encoder_irq_control(drm_enc, true); + /* enable all the irq */ + _dpu_encoder_irq_enable(drm_enc); +} - } else { - /* disable all the irq */ - _dpu_encoder_irq_control(drm_enc, false); +static void _dpu_encoder_resource_disable(struct drm_encoder *drm_enc) +{ + struct msm_drm_private *priv; + struct dpu_kms *dpu_kms; + struct dpu_encoder_virt *dpu_enc; + + dpu_enc = to_dpu_encoder_virt(drm_enc); + priv = drm_enc->dev->dev_private; + dpu_kms = to_dpu_kms(priv->kms); - /* disable DPU core clks */ - pm_runtime_put_sync(&dpu_kms->pdev->dev); + trace_dpu_enc_rc_disable(DRMID(drm_enc)); + + if (!dpu_enc->cur_master) { + DPU_ERROR("encoder master not set\n"); + return; } + /* disable all the irq */ + _dpu_encoder_irq_disable(drm_enc); + + /* disable DPU core clks */ + pm_runtime_put_sync(&dpu_kms->pdev->dev); } static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, @@ -824,9 +902,9 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, } if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) - _dpu_encoder_irq_control(drm_enc, true); + _dpu_encoder_irq_enable(drm_enc); else - _dpu_encoder_resource_control_helper(drm_enc, true); + _dpu_encoder_resource_enable(drm_enc); dpu_enc->rc_state = DPU_ENC_RC_STATE_ON; @@ -879,7 +957,7 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, if (is_vid_mode && dpu_enc->rc_state == DPU_ENC_RC_STATE_IDLE) { - _dpu_encoder_irq_control(drm_enc, true); + _dpu_encoder_irq_enable(drm_enc); } /* skip if is already OFF or IDLE, resources are off already */ else if (dpu_enc->rc_state == DPU_ENC_RC_STATE_OFF || @@ -921,7 +999,7 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, * and in IDLE state the resources are already disabled */ if (dpu_enc->rc_state == DPU_ENC_RC_STATE_PRE_OFF) - _dpu_encoder_resource_control_helper(drm_enc, false); + _dpu_encoder_resource_disable(drm_enc); dpu_enc->rc_state = DPU_ENC_RC_STATE_OFF; @@ -954,9 +1032,9 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, } if (is_vid_mode) - _dpu_encoder_irq_control(drm_enc, false); + _dpu_encoder_irq_disable(drm_enc); else - _dpu_encoder_resource_control_helper(drm_enc, false); + _dpu_encoder_resource_disable(drm_enc); dpu_enc->rc_state = DPU_ENC_RC_STATE_IDLE; @@ -1079,7 +1157,8 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, dpu_enc->dsc_mask = dsc_mask; - if (dpu_enc->disp_info.intf_type == INTF_WB && conn_state->writeback_job) { + if ((dpu_enc->disp_info.intf_type == INTF_WB && conn_state->writeback_job) || + dpu_enc->disp_info.intf_type == INTF_DP) { struct dpu_hw_blk *hw_cdm = NULL; dpu_rm_get_assigned_resources(&dpu_kms->rm, global_state, @@ -1121,8 +1200,6 @@ static void dpu_encoder_virt_atomic_mode_set(struct drm_encoder *drm_enc, phys->hw_ctl = to_dpu_hw_ctl(hw_ctl[i]); phys->cached_mode = crtc_state->adjusted_mode; - if (phys->ops.atomic_mode_set) - phys->ops.atomic_mode_set(phys, crtc_state, conn_state); } } @@ -1188,26 +1265,20 @@ static void dpu_encoder_virt_atomic_enable(struct drm_encoder *drm_enc, struct dpu_encoder_virt *dpu_enc = NULL; int ret = 0; struct drm_display_mode *cur_mode = NULL; - struct msm_drm_private *priv = drm_enc->dev->dev_private; - struct msm_display_info *disp_info; - int index; dpu_enc = to_dpu_encoder_virt(drm_enc); - disp_info = &dpu_enc->disp_info; - index = disp_info->h_tile_instance[0]; - dpu_enc->dsc = dpu_encoder_get_dsc_config(drm_enc); atomic_set(&dpu_enc->frame_done_timeout_cnt, 0); - if (disp_info->intf_type == INTF_DP) - dpu_enc->wide_bus_en = msm_dp_wide_bus_available(priv->dp[index]); - else if (disp_info->intf_type == INTF_DSI) - dpu_enc->wide_bus_en = msm_dsi_wide_bus_enabled(priv->dsi[index]); - mutex_lock(&dpu_enc->enc_lock); + + dpu_enc->commit_done_timedout = false; + cur_mode = &dpu_enc->base.crtc->state->adjusted_mode; + dpu_enc->wide_bus_en = dpu_encoder_is_widebus_enabled(drm_enc); + trace_dpu_enc_enable(DRMID(drm_enc), cur_mode->hdisplay, cur_mode->vdisplay); @@ -1261,7 +1332,7 @@ static void dpu_encoder_virt_atomic_disable(struct drm_encoder *drm_enc, trace_dpu_enc_disable(DRMID(drm_enc)); /* wait for idle */ - dpu_encoder_wait_for_event(drm_enc, MSM_ENC_TX_COMPLETE); + dpu_encoder_wait_for_tx_complete(drm_enc); dpu_encoder_resource_control(drm_enc, DPU_ENC_RC_EVENT_PRE_STOP); @@ -1853,7 +1924,9 @@ static void dpu_encoder_prep_dsc(struct dpu_encoder_virt *dpu_enc, dsc_common_mode = 0; pic_width = dsc->pic_width; - dsc_common_mode = DSC_MODE_MULTIPLEX | DSC_MODE_SPLIT_PANEL; + dsc_common_mode = DSC_MODE_SPLIT_PANEL; + if (dpu_encoder_use_dsc_merge(enc_master->parent)) + dsc_common_mode |= DSC_MODE_MULTIPLEX; if (enc_master->intf_mode == INTF_MODE_VIDEO) dsc_common_mode |= DSC_MODE_VIDEO; @@ -2110,6 +2183,84 @@ void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc) ctl->ops.clear_pending_flush(ctl); } +void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc, + const struct dpu_format *dpu_fmt, + u32 output_type) +{ + struct dpu_hw_cdm *hw_cdm; + struct dpu_hw_cdm_cfg *cdm_cfg; + struct dpu_hw_pingpong *hw_pp; + int ret; + + if (!phys_enc) + return; + + cdm_cfg = &phys_enc->cdm_cfg; + hw_pp = phys_enc->hw_pp; + hw_cdm = phys_enc->hw_cdm; + + if (!hw_cdm) + return; + + if (!DPU_FORMAT_IS_YUV(dpu_fmt)) { + DPU_DEBUG("[enc:%d] cdm_disable fmt:%x\n", DRMID(phys_enc->parent), + dpu_fmt->base.pixel_format); + if (hw_cdm->ops.bind_pingpong_blk) + hw_cdm->ops.bind_pingpong_blk(hw_cdm, PINGPONG_NONE); + + return; + } + + memset(cdm_cfg, 0, sizeof(struct dpu_hw_cdm_cfg)); + + cdm_cfg->output_width = phys_enc->cached_mode.hdisplay; + cdm_cfg->output_height = phys_enc->cached_mode.vdisplay; + cdm_cfg->output_fmt = dpu_fmt; + cdm_cfg->output_type = output_type; + cdm_cfg->output_bit_depth = DPU_FORMAT_IS_DX(dpu_fmt) ? + CDM_CDWN_OUTPUT_10BIT : CDM_CDWN_OUTPUT_8BIT; + cdm_cfg->csc_cfg = &dpu_csc10_rgb2yuv_601l; + + /* enable 10 bit logic */ + switch (cdm_cfg->output_fmt->chroma_sample) { + case DPU_CHROMA_RGB: + cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE; + cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE; + break; + case DPU_CHROMA_H2V1: + cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE; + cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE; + break; + case DPU_CHROMA_420: + cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE; + cdm_cfg->v_cdwn_type = CDM_CDWN_OFFSITE; + break; + case DPU_CHROMA_H1V2: + default: + DPU_ERROR("[enc:%d] unsupported chroma sampling type\n", + DRMID(phys_enc->parent)); + cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE; + cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE; + break; + } + + DPU_DEBUG("[enc:%d] cdm_enable:%d,%d,%X,%d,%d,%d,%d]\n", + DRMID(phys_enc->parent), cdm_cfg->output_width, + cdm_cfg->output_height, cdm_cfg->output_fmt->base.pixel_format, + cdm_cfg->output_type, cdm_cfg->output_bit_depth, + cdm_cfg->h_cdwn_type, cdm_cfg->v_cdwn_type); + + if (hw_cdm->ops.enable) { + cdm_cfg->pp_id = hw_pp->idx; + ret = hw_cdm->ops.enable(hw_cdm, cdm_cfg); + if (ret < 0) { + DPU_ERROR("[enc:%d] failed to enable CDM; ret:%d\n", + DRMID(phys_enc->parent), ret); + return; + } + } +} + #ifdef CONFIG_DEBUG_FS static int _dpu_encoder_status_show(struct seq_file *s, void *data) { @@ -2379,10 +2530,18 @@ struct drm_encoder *dpu_encoder_init(struct drm_device *dev, return &dpu_enc->base; } -int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc, - enum msm_event_wait event) +/** + * dpu_encoder_wait_for_commit_done() - Wait for encoder to flush pending state + * @drm_enc: encoder pointer + * + * Wait for hardware to have flushed the current pending changes to hardware at + * a vblank or CTL_START. Physical encoders will map this differently depending + * on the type: vid mode -> vsync_irq, cmd mode -> CTL_START. + * + * Return: 0 on success, -EWOULDBLOCK if already signaled, error otherwise + */ +int dpu_encoder_wait_for_commit_done(struct drm_encoder *drm_enc) { - int (*fn_wait)(struct dpu_encoder_phys *phys_enc) = NULL; struct dpu_encoder_virt *dpu_enc = NULL; int i, ret = 0; @@ -2396,23 +2555,51 @@ int dpu_encoder_wait_for_event(struct drm_encoder *drm_enc, for (i = 0; i < dpu_enc->num_phys_encs; i++) { struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; - switch (event) { - case MSM_ENC_COMMIT_DONE: - fn_wait = phys->ops.wait_for_commit_done; - break; - case MSM_ENC_TX_COMPLETE: - fn_wait = phys->ops.wait_for_tx_complete; - break; - default: - DPU_ERROR_ENC(dpu_enc, "unknown wait event %d\n", - event); - return -EINVAL; + if (phys->ops.wait_for_commit_done) { + DPU_ATRACE_BEGIN("wait_for_commit_done"); + ret = phys->ops.wait_for_commit_done(phys); + DPU_ATRACE_END("wait_for_commit_done"); + if (ret == -ETIMEDOUT && !dpu_enc->commit_done_timedout) { + dpu_enc->commit_done_timedout = true; + msm_disp_snapshot_state(drm_enc->dev); + } + if (ret) + return ret; } + } + + return ret; +} + +/** + * dpu_encoder_wait_for_tx_complete() - Wait for encoder to transfer pixels to panel + * @drm_enc: encoder pointer + * + * Wait for the hardware to transfer all the pixels to the panel. Physical + * encoders will map this differently depending on the type: vid mode -> vsync_irq, + * cmd mode -> pp_done. + * + * Return: 0 on success, -EWOULDBLOCK if already signaled, error otherwise + */ +int dpu_encoder_wait_for_tx_complete(struct drm_encoder *drm_enc) +{ + struct dpu_encoder_virt *dpu_enc = NULL; + int i, ret = 0; + + if (!drm_enc) { + DPU_ERROR("invalid encoder\n"); + return -EINVAL; + } + dpu_enc = to_dpu_encoder_virt(drm_enc); + DPU_DEBUG_ENC(dpu_enc, "\n"); + + for (i = 0; i < dpu_enc->num_phys_encs; i++) { + struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i]; - if (fn_wait) { - DPU_ATRACE_BEGIN("wait_for_completion_event"); - ret = fn_wait(phys); - DPU_ATRACE_END("wait_for_completion_event"); + if (phys->ops.wait_for_tx_complete) { + DPU_ATRACE_BEGIN("wait_for_tx_complete"); + ret = phys->ops.wait_for_tx_complete(phys); + DPU_ATRACE_END("wait_for_tx_complete"); if (ret) return ret; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h index 4c05fd5e9ed1..76be77e30954 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h @@ -93,25 +93,9 @@ void dpu_encoder_kickoff(struct drm_encoder *encoder); */ int dpu_encoder_vsync_time(struct drm_encoder *drm_enc, ktime_t *wakeup_time); -/** - * dpu_encoder_wait_for_event - Waits for encoder events - * @encoder: encoder pointer - * @event: event to wait for - * MSM_ENC_COMMIT_DONE - Wait for hardware to have flushed the current pending - * frames to hardware at a vblank or ctl_start - * Encoders will map this differently depending on the - * panel type. - * vid mode -> vsync_irq - * cmd mode -> ctl_start - * MSM_ENC_TX_COMPLETE - Wait for the hardware to transfer all the pixels to - * the panel. Encoders will map this differently - * depending on the panel type. - * vid mode -> vsync_irq - * cmd mode -> pp_done - * Returns: 0 on success, -EWOULDBLOCK if already signaled, error otherwise - */ -int dpu_encoder_wait_for_event(struct drm_encoder *drm_encoder, - enum msm_event_wait event); +int dpu_encoder_wait_for_commit_done(struct drm_encoder *drm_encoder); + +int dpu_encoder_wait_for_tx_complete(struct drm_encoder *drm_encoder); /* * dpu_encoder_get_intf_mode - get interface mode of the given encoder @@ -156,9 +140,20 @@ int dpu_encoder_get_linecount(struct drm_encoder *drm_enc); */ int dpu_encoder_get_vsync_count(struct drm_encoder *drm_enc); +/** + * dpu_encoder_is_widebus_enabled - return bool value if widebus is enabled + * @drm_enc: Pointer to previously created drm encoder structure + */ bool dpu_encoder_is_widebus_enabled(const struct drm_encoder *drm_enc); /** + * dpu_encoder_is_dsc_enabled - indicate whether dsc is enabled + * for the encoder. + * @drm_enc: Pointer to previously created drm encoder structure + */ +bool dpu_encoder_is_dsc_enabled(const struct drm_encoder *drm_enc); + +/** * dpu_encoder_get_crc_values_cnt - get number of physical encoders contained * in virtual encoder that can collect CRC values * @drm_enc: Pointer to previously created drm encoder structure diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index 993f26343331..98d1b64a43e8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -69,11 +69,8 @@ struct dpu_encoder_phys; * @is_master: Whether this phys_enc is the current master * encoder. Can be switched at enable time. Based * on split_role and current mode (CMD/VID). - * @atomic_mode_set: DRM Call. Set a DRM mode. - * This likely caches the mode, for use at enable. * @enable: DRM Call. Enable a DRM mode. * @disable: DRM Call. Disable mode. - * @atomic_check: DRM Call. Atomic check new DRM state. * @control_vblank_irq Register/Deregister for VBLANK IRQ * @wait_for_commit_done: Wait for hardware to have flushed the * current pending frames to hardware @@ -85,7 +82,8 @@ struct dpu_encoder_phys; * @handle_post_kickoff: Do any work necessary post-kickoff work * @trigger_start: Process start event on physical encoder * @needs_single_flush: Whether encoder slaves need to be flushed - * @irq_control: Handler to enable/disable all the encoder IRQs + * @irq_enable: Handler to enable all the encoder IRQs + * @irq_disable: Handler to disable all the encoder IRQs * @prepare_idle_pc: phys encoder can update the vsync_enable status * on idle power collapse prepare * @restore: Restore all the encoder configs. @@ -95,14 +93,8 @@ struct dpu_encoder_phys; struct dpu_encoder_phys_ops { void (*prepare_commit)(struct dpu_encoder_phys *encoder); bool (*is_master)(struct dpu_encoder_phys *encoder); - void (*atomic_mode_set)(struct dpu_encoder_phys *encoder, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state); void (*enable)(struct dpu_encoder_phys *encoder); void (*disable)(struct dpu_encoder_phys *encoder); - int (*atomic_check)(struct dpu_encoder_phys *encoder, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state); int (*control_vblank_irq)(struct dpu_encoder_phys *enc, bool enable); int (*wait_for_commit_done)(struct dpu_encoder_phys *phys_enc); int (*wait_for_tx_complete)(struct dpu_encoder_phys *phys_enc); @@ -110,7 +102,8 @@ struct dpu_encoder_phys_ops { void (*handle_post_kickoff)(struct dpu_encoder_phys *phys_enc); void (*trigger_start)(struct dpu_encoder_phys *phys_enc); bool (*needs_single_flush)(struct dpu_encoder_phys *phys_enc); - void (*irq_control)(struct dpu_encoder_phys *phys, bool enable); + void (*irq_enable)(struct dpu_encoder_phys *phys); + void (*irq_disable)(struct dpu_encoder_phys *phys); void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc); void (*restore)(struct dpu_encoder_phys *phys); int (*get_line_count)(struct dpu_encoder_phys *phys); @@ -154,6 +147,7 @@ enum dpu_intr_idx { * @hw_wb: Hardware interface to the wb registers * @hw_cdm: Hardware interface to the CDM registers * @dpu_kms: Pointer to the dpu_kms top level + * @cdm_cfg: CDM block config needed to store WB/DP block's CDM configuration * @cached_mode: DRM mode cached at mode_set time, acted on in enable * @vblank_ctl_lock: Vblank ctl mutex lock to protect vblank_refcount * @enabled: Whether the encoder has enabled and running a mode @@ -184,6 +178,7 @@ struct dpu_encoder_phys { struct dpu_hw_wb *hw_wb; struct dpu_hw_cdm *hw_cdm; struct dpu_kms *dpu_kms; + struct dpu_hw_cdm_cfg cdm_cfg; struct drm_display_mode cached_mode; struct mutex vblank_ctl_lock; enum dpu_enc_split_role split_role; @@ -213,7 +208,6 @@ static inline int dpu_encoder_phys_inc_pending(struct dpu_encoder_phys *phys) * @wbirq_refcount: Reference count of writeback interrupt * @wb_done_timeout_cnt: number of wb done irq timeout errors * @wb_cfg: writeback block config to store fb related details - * @cdm_cfg: cdm block config needed to store writeback block's CDM configuration * @wb_conn: backpointer to writeback connector * @wb_job: backpointer to current writeback job * @dest: dpu buffer layout for current writeback output buffer @@ -223,7 +217,6 @@ struct dpu_encoder_phys_wb { atomic_t wbirq_refcount; int wb_done_timeout_cnt; struct dpu_hw_wb_cfg wb_cfg; - struct dpu_hw_cdm_cfg cdm_cfg; struct drm_writeback_connector *wb_conn; struct drm_writeback_job *wb_job; struct dpu_hw_fmt_layout dest; @@ -342,6 +335,19 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode( unsigned int dpu_encoder_helper_get_dsc(struct dpu_encoder_phys *phys_enc); /** + * dpu_encoder_get_drm_fmt - return DRM fourcc format + * @phys_enc: Pointer to physical encoder structure + */ +u32 dpu_encoder_get_drm_fmt(struct dpu_encoder_phys *phys_enc); + +/** + * dpu_encoder_needs_periph_flush - return true if physical encoder requires + * peripheral flush + * @phys_enc: Pointer to physical encoder structure + */ +bool dpu_encoder_needs_periph_flush(struct dpu_encoder_phys *phys_enc); + +/** * dpu_encoder_helper_split_config - split display configuration helper function * This helper function may be used by physical encoders to configure * the split display related registers. @@ -382,6 +388,15 @@ int dpu_encoder_helper_wait_for_irq(struct dpu_encoder_phys *phys_enc, void dpu_encoder_helper_phys_cleanup(struct dpu_encoder_phys *phys_enc); /** + * dpu_encoder_helper_phys_setup_cdm - setup chroma down sampling block + * @phys_enc: Pointer to physical encoder + * @output_type: HDMI/WB + */ +void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc, + const struct dpu_format *dpu_fmt, + u32 output_type); + +/** * dpu_encoder_vblank_callback - Notify virtual encoder of vblank IRQ reception * @drm_enc: Pointer to drm encoder structure * @phys_enc: Pointer to physical encoder diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index a301e2833177..fc1d5736d7fc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -142,23 +142,6 @@ static void dpu_encoder_phys_cmd_underrun_irq(void *arg) dpu_encoder_underrun_callback(phys_enc->parent, phys_enc); } -static void dpu_encoder_phys_cmd_atomic_mode_set( - struct dpu_encoder_phys *phys_enc, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) -{ - phys_enc->irq[INTR_IDX_CTL_START] = phys_enc->hw_ctl->caps->intr_start; - - phys_enc->irq[INTR_IDX_PINGPONG] = phys_enc->hw_pp->caps->intr_done; - - if (phys_enc->has_intf_te) - phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_intf->cap->intr_tear_rd_ptr; - else - phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_pp->caps->intr_rdptr; - - phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun; -} - static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( struct dpu_encoder_phys *phys_enc) { @@ -291,40 +274,54 @@ end: return ret; } -static void dpu_encoder_phys_cmd_irq_control(struct dpu_encoder_phys *phys_enc, - bool enable) +static void dpu_encoder_phys_cmd_irq_enable(struct dpu_encoder_phys *phys_enc) { - trace_dpu_enc_phys_cmd_irq_ctrl(DRMID(phys_enc->parent), - phys_enc->hw_pp->idx - PINGPONG_0, - enable, phys_enc->vblank_refcount); + trace_dpu_enc_phys_cmd_irq_enable(DRMID(phys_enc->parent), + phys_enc->hw_pp->idx - PINGPONG_0, + phys_enc->vblank_refcount); - if (enable) { - dpu_core_irq_register_callback(phys_enc->dpu_kms, - phys_enc->irq[INTR_IDX_PINGPONG], - dpu_encoder_phys_cmd_pp_tx_done_irq, - phys_enc); + phys_enc->irq[INTR_IDX_CTL_START] = phys_enc->hw_ctl->caps->intr_start; + phys_enc->irq[INTR_IDX_PINGPONG] = phys_enc->hw_pp->caps->intr_done; + + if (phys_enc->has_intf_te) + phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_intf->cap->intr_tear_rd_ptr; + else + phys_enc->irq[INTR_IDX_RDPTR] = phys_enc->hw_pp->caps->intr_rdptr; + + dpu_core_irq_register_callback(phys_enc->dpu_kms, + phys_enc->irq[INTR_IDX_PINGPONG], + dpu_encoder_phys_cmd_pp_tx_done_irq, + phys_enc); + dpu_core_irq_register_callback(phys_enc->dpu_kms, + phys_enc->irq[INTR_IDX_UNDERRUN], + dpu_encoder_phys_cmd_underrun_irq, + phys_enc); + dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, true); + + if (dpu_encoder_phys_cmd_is_master(phys_enc)) dpu_core_irq_register_callback(phys_enc->dpu_kms, - phys_enc->irq[INTR_IDX_UNDERRUN], - dpu_encoder_phys_cmd_underrun_irq, - phys_enc); - dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, true); - - if (dpu_encoder_phys_cmd_is_master(phys_enc)) - dpu_core_irq_register_callback(phys_enc->dpu_kms, - phys_enc->irq[INTR_IDX_CTL_START], - dpu_encoder_phys_cmd_ctl_start_irq, - phys_enc); - } else { - if (dpu_encoder_phys_cmd_is_master(phys_enc)) - dpu_core_irq_unregister_callback(phys_enc->dpu_kms, - phys_enc->irq[INTR_IDX_CTL_START]); + phys_enc->irq[INTR_IDX_CTL_START], + dpu_encoder_phys_cmd_ctl_start_irq, + phys_enc); +} +static void dpu_encoder_phys_cmd_irq_disable(struct dpu_encoder_phys *phys_enc) +{ + trace_dpu_enc_phys_cmd_irq_disable(DRMID(phys_enc->parent), + phys_enc->hw_pp->idx - PINGPONG_0, + phys_enc->vblank_refcount); + + if (dpu_encoder_phys_cmd_is_master(phys_enc)) dpu_core_irq_unregister_callback(phys_enc->dpu_kms, - phys_enc->irq[INTR_IDX_UNDERRUN]); - dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, false); - dpu_core_irq_unregister_callback(phys_enc->dpu_kms, - phys_enc->irq[INTR_IDX_PINGPONG]); - } + phys_enc->irq[INTR_IDX_CTL_START]); + + dpu_core_irq_unregister_callback(phys_enc->dpu_kms, phys_enc->irq[INTR_IDX_UNDERRUN]); + dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, false); + dpu_core_irq_unregister_callback(phys_enc->dpu_kms, phys_enc->irq[INTR_IDX_PINGPONG]); + + phys_enc->irq[INTR_IDX_CTL_START] = 0; + phys_enc->irq[INTR_IDX_PINGPONG] = 0; + phys_enc->irq[INTR_IDX_RDPTR] = 0; } static void dpu_encoder_phys_cmd_tearcheck_config( @@ -704,7 +701,6 @@ static void dpu_encoder_phys_cmd_init_ops( struct dpu_encoder_phys_ops *ops) { ops->is_master = dpu_encoder_phys_cmd_is_master; - ops->atomic_mode_set = dpu_encoder_phys_cmd_atomic_mode_set; ops->enable = dpu_encoder_phys_cmd_enable; ops->disable = dpu_encoder_phys_cmd_disable; ops->control_vblank_irq = dpu_encoder_phys_cmd_control_vblank_irq; @@ -713,7 +709,8 @@ static void dpu_encoder_phys_cmd_init_ops( ops->wait_for_tx_complete = dpu_encoder_phys_cmd_wait_for_tx_complete; ops->trigger_start = dpu_encoder_phys_cmd_trigger_start; ops->needs_single_flush = dpu_encoder_phys_cmd_needs_single_flush; - ops->irq_control = dpu_encoder_phys_cmd_irq_control; + ops->irq_enable = dpu_encoder_phys_cmd_irq_enable; + ops->irq_disable = dpu_encoder_phys_cmd_irq_disable; ops->restore = dpu_encoder_phys_cmd_enable_helper; ops->prepare_idle_pc = dpu_encoder_phys_cmd_prepare_idle_pc; ops->handle_post_kickoff = dpu_encoder_phys_cmd_handle_post_kickoff; @@ -742,6 +739,8 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(struct drm_device *dev, dpu_encoder_phys_cmd_init_ops(&phys_enc->ops); phys_enc->intf_mode = INTF_MODE_CMD; + phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun; + cmd_enc->stream_sel = 0; if (!phys_enc->hw_intf) { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c index d0f56c5c4cce..d9e7dbf0499c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c @@ -102,6 +102,7 @@ static void drm_mode_to_intf_timing_params( } timing->wide_bus_en = dpu_encoder_is_widebus_enabled(phys_enc->parent); + timing->compression_en = dpu_encoder_is_dsc_enabled(phys_enc->parent); /* * for DP, divide the horizonal parameters by 2 when @@ -235,7 +236,7 @@ static void dpu_encoder_phys_vid_setup_timing_engine( struct drm_display_mode mode; struct dpu_hw_intf_timing_params timing_params = { 0 }; const struct dpu_format *fmt = NULL; - u32 fmt_fourcc = DRM_FORMAT_RGB888; + u32 fmt_fourcc; unsigned long lock_flags; struct dpu_hw_intf_cfg intf_cfg = { 0 }; @@ -254,17 +255,21 @@ static void dpu_encoder_phys_vid_setup_timing_engine( DPU_DEBUG_VIDENC(phys_enc, "enabling mode:\n"); drm_mode_debug_printmodeline(&mode); - if (phys_enc->split_role != ENC_ROLE_SOLO) { + fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc); + + if (phys_enc->split_role != ENC_ROLE_SOLO || fmt_fourcc == DRM_FORMAT_YUV420) { mode.hdisplay >>= 1; mode.htotal >>= 1; mode.hsync_start >>= 1; mode.hsync_end >>= 1; + mode.hskew >>= 1; DPU_DEBUG_VIDENC(phys_enc, - "split_role %d, halve horizontal %d %d %d %d\n", + "split_role %d, halve horizontal %d %d %d %d %d\n", phys_enc->split_role, mode.hdisplay, mode.htotal, - mode.hsync_start, mode.hsync_end); + mode.hsync_start, mode.hsync_end, + mode.hskew); } drm_mode_to_intf_timing_params(phys_enc, &mode, &timing_params); @@ -272,6 +277,8 @@ static void dpu_encoder_phys_vid_setup_timing_engine( fmt = dpu_get_dpu_format(fmt_fourcc); DPU_DEBUG_VIDENC(phys_enc, "fmt_fourcc 0x%X\n", fmt_fourcc); + if (phys_enc->hw_cdm) + intf_cfg.cdm = phys_enc->hw_cdm->idx; intf_cfg.intf = phys_enc->hw_intf->idx; intf_cfg.intf_mode_sel = DPU_CTL_MODE_SEL_VID; intf_cfg.stream_sel = 0; /* Don't care value for video mode */ @@ -349,16 +356,6 @@ static bool dpu_encoder_phys_vid_needs_single_flush( return phys_enc->split_role != ENC_ROLE_SOLO; } -static void dpu_encoder_phys_vid_atomic_mode_set( - struct dpu_encoder_phys *phys_enc, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) -{ - phys_enc->irq[INTR_IDX_VSYNC] = phys_enc->hw_intf->cap->intr_vsync; - - phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun; -} - static int dpu_encoder_phys_vid_control_vblank_irq( struct dpu_encoder_phys *phys_enc, bool enable) @@ -412,8 +409,12 @@ end: static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc) { struct dpu_hw_ctl *ctl; + const struct dpu_format *fmt; + u32 fmt_fourcc; ctl = phys_enc->hw_ctl; + fmt_fourcc = dpu_encoder_get_drm_fmt(phys_enc); + fmt = dpu_get_dpu_format(fmt_fourcc); DPU_DEBUG_VIDENC(phys_enc, "\n"); @@ -422,6 +423,8 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc) dpu_encoder_helper_split_config(phys_enc, phys_enc->hw_intf->idx); + dpu_encoder_helper_phys_setup_cdm(phys_enc, fmt, CDM_CDWN_OUTPUT_HDMI); + dpu_encoder_phys_vid_setup_timing_engine(phys_enc); /* @@ -437,6 +440,16 @@ static void dpu_encoder_phys_vid_enable(struct dpu_encoder_phys *phys_enc) if (ctl->ops.update_pending_flush_merge_3d && phys_enc->hw_pp->merge_3d) ctl->ops.update_pending_flush_merge_3d(ctl, phys_enc->hw_pp->merge_3d->idx); + if (ctl->ops.update_pending_flush_cdm && phys_enc->hw_cdm) + ctl->ops.update_pending_flush_cdm(ctl, phys_enc->hw_cdm->idx); + + /* + * Peripheral flush must be updated whenever flushing SDP packets is needed. + * SDP packets are required for any YUV format (YUV420, YUV422, YUV444). + */ + if (ctl->ops.update_pending_flush_periph && dpu_encoder_needs_periph_flush(phys_enc)) + ctl->ops.update_pending_flush_periph(ctl, phys_enc->hw_intf->idx); + skip_flush: DPU_DEBUG_VIDENC(phys_enc, "update pending flush ctl %d intf %d\n", @@ -489,7 +502,7 @@ static int dpu_encoder_phys_vid_wait_for_commit_done( (hw_ctl->ops.get_flush_register(hw_ctl) == 0), msecs_to_jiffies(50)); if (ret <= 0) { - DPU_ERROR("vblank timeout\n"); + DPU_ERROR("vblank timeout: %x\n", hw_ctl->ops.get_flush_register(hw_ctl)); return -ETIMEDOUT; } @@ -615,30 +628,33 @@ static void dpu_encoder_phys_vid_handle_post_kickoff( } } -static void dpu_encoder_phys_vid_irq_control(struct dpu_encoder_phys *phys_enc, - bool enable) +static void dpu_encoder_phys_vid_irq_enable(struct dpu_encoder_phys *phys_enc) { int ret; - trace_dpu_enc_phys_vid_irq_ctrl(DRMID(phys_enc->parent), - phys_enc->hw_intf->idx - INTF_0, - enable, - phys_enc->vblank_refcount); + trace_dpu_enc_phys_vid_irq_enable(DRMID(phys_enc->parent), + phys_enc->hw_intf->idx - INTF_0, + phys_enc->vblank_refcount); - if (enable) { - ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true); - if (WARN_ON(ret)) - return; - - dpu_core_irq_register_callback(phys_enc->dpu_kms, - phys_enc->irq[INTR_IDX_UNDERRUN], - dpu_encoder_phys_vid_underrun_irq, - phys_enc); - } else { - dpu_encoder_phys_vid_control_vblank_irq(phys_enc, false); - dpu_core_irq_unregister_callback(phys_enc->dpu_kms, - phys_enc->irq[INTR_IDX_UNDERRUN]); - } + ret = dpu_encoder_phys_vid_control_vblank_irq(phys_enc, true); + if (WARN_ON(ret)) + return; + + dpu_core_irq_register_callback(phys_enc->dpu_kms, + phys_enc->irq[INTR_IDX_UNDERRUN], + dpu_encoder_phys_vid_underrun_irq, + phys_enc); +} + +static void dpu_encoder_phys_vid_irq_disable(struct dpu_encoder_phys *phys_enc) +{ + trace_dpu_enc_phys_vid_irq_disable(DRMID(phys_enc->parent), + phys_enc->hw_intf->idx - INTF_0, + phys_enc->vblank_refcount); + + dpu_encoder_phys_vid_control_vblank_irq(phys_enc, false); + dpu_core_irq_unregister_callback(phys_enc->dpu_kms, + phys_enc->irq[INTR_IDX_UNDERRUN]); } static int dpu_encoder_phys_vid_get_line_count( @@ -683,13 +699,13 @@ static int dpu_encoder_phys_vid_get_frame_count( static void dpu_encoder_phys_vid_init_ops(struct dpu_encoder_phys_ops *ops) { ops->is_master = dpu_encoder_phys_vid_is_master; - ops->atomic_mode_set = dpu_encoder_phys_vid_atomic_mode_set; ops->enable = dpu_encoder_phys_vid_enable; ops->disable = dpu_encoder_phys_vid_disable; ops->control_vblank_irq = dpu_encoder_phys_vid_control_vblank_irq; ops->wait_for_commit_done = dpu_encoder_phys_vid_wait_for_commit_done; ops->wait_for_tx_complete = dpu_encoder_phys_vid_wait_for_tx_complete; - ops->irq_control = dpu_encoder_phys_vid_irq_control; + ops->irq_enable = dpu_encoder_phys_vid_irq_enable; + ops->irq_disable = dpu_encoder_phys_vid_irq_disable; ops->prepare_for_kickoff = dpu_encoder_phys_vid_prepare_for_kickoff; ops->handle_post_kickoff = dpu_encoder_phys_vid_handle_post_kickoff; ops->needs_single_flush = dpu_encoder_phys_vid_needs_single_flush; @@ -721,6 +737,8 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(struct drm_device *dev, dpu_encoder_phys_vid_init_ops(&phys_enc->ops); phys_enc->intf_mode = INTF_MODE_VIDEO; + phys_enc->irq[INTR_IDX_VSYNC] = phys_enc->hw_intf->cap->intr_vsync; + phys_enc->irq[INTR_IDX_UNDERRUN] = phys_enc->hw_intf->cap->intr_underrun; DPU_DEBUG_VIDENC(phys_enc, "created intf idx:%d\n", p->hw_intf->idx); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c index 4cd2d9e3131a..1924a2b28e53 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c @@ -265,149 +265,6 @@ static void dpu_encoder_phys_wb_setup_ctl(struct dpu_encoder_phys *phys_enc) } /** - * dpu_encoder_helper_phys_setup_cdm - setup chroma down sampling block - * This API does not handle DPU_CHROMA_H1V2. - * @phys_enc:Pointer to physical encoder - */ -static void dpu_encoder_helper_phys_setup_cdm(struct dpu_encoder_phys *phys_enc) -{ - struct dpu_hw_cdm *hw_cdm; - struct dpu_hw_cdm_cfg *cdm_cfg; - struct dpu_hw_pingpong *hw_pp; - struct dpu_encoder_phys_wb *wb_enc; - const struct msm_format *format; - const struct dpu_format *dpu_fmt; - struct drm_writeback_job *wb_job; - int ret; - - if (!phys_enc) - return; - - wb_enc = to_dpu_encoder_phys_wb(phys_enc); - cdm_cfg = &wb_enc->cdm_cfg; - hw_pp = phys_enc->hw_pp; - hw_cdm = phys_enc->hw_cdm; - wb_job = wb_enc->wb_job; - - format = msm_framebuffer_format(wb_enc->wb_job->fb); - dpu_fmt = dpu_get_dpu_format_ext(format->pixel_format, wb_job->fb->modifier); - - if (!hw_cdm) - return; - - if (!DPU_FORMAT_IS_YUV(dpu_fmt)) { - DPU_DEBUG("[enc:%d] cdm_disable fmt:%x\n", DRMID(phys_enc->parent), - dpu_fmt->base.pixel_format); - if (hw_cdm->ops.bind_pingpong_blk) - hw_cdm->ops.bind_pingpong_blk(hw_cdm, PINGPONG_NONE); - - return; - } - - memset(cdm_cfg, 0, sizeof(struct dpu_hw_cdm_cfg)); - - cdm_cfg->output_width = wb_job->fb->width; - cdm_cfg->output_height = wb_job->fb->height; - cdm_cfg->output_fmt = dpu_fmt; - cdm_cfg->output_type = CDM_CDWN_OUTPUT_WB; - cdm_cfg->output_bit_depth = DPU_FORMAT_IS_DX(dpu_fmt) ? - CDM_CDWN_OUTPUT_10BIT : CDM_CDWN_OUTPUT_8BIT; - cdm_cfg->csc_cfg = &dpu_csc10_rgb2yuv_601l; - - /* enable 10 bit logic */ - switch (cdm_cfg->output_fmt->chroma_sample) { - case DPU_CHROMA_RGB: - cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE; - cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE; - break; - case DPU_CHROMA_H2V1: - cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE; - cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE; - break; - case DPU_CHROMA_420: - cdm_cfg->h_cdwn_type = CDM_CDWN_COSITE; - cdm_cfg->v_cdwn_type = CDM_CDWN_OFFSITE; - break; - case DPU_CHROMA_H1V2: - default: - DPU_ERROR("[enc:%d] unsupported chroma sampling type\n", - DRMID(phys_enc->parent)); - cdm_cfg->h_cdwn_type = CDM_CDWN_DISABLE; - cdm_cfg->v_cdwn_type = CDM_CDWN_DISABLE; - break; - } - - DPU_DEBUG("[enc:%d] cdm_enable:%d,%d,%X,%d,%d,%d,%d]\n", - DRMID(phys_enc->parent), cdm_cfg->output_width, - cdm_cfg->output_height, cdm_cfg->output_fmt->base.pixel_format, - cdm_cfg->output_type, cdm_cfg->output_bit_depth, - cdm_cfg->h_cdwn_type, cdm_cfg->v_cdwn_type); - - if (hw_cdm->ops.enable) { - cdm_cfg->pp_id = hw_pp->idx; - ret = hw_cdm->ops.enable(hw_cdm, cdm_cfg); - if (ret < 0) { - DPU_ERROR("[enc:%d] failed to enable CDM; ret:%d\n", - DRMID(phys_enc->parent), ret); - return; - } - } -} - -/** - * dpu_encoder_phys_wb_atomic_check - verify and fixup given atomic states - * @phys_enc: Pointer to physical encoder - * @crtc_state: Pointer to CRTC atomic state - * @conn_state: Pointer to connector atomic state - */ -static int dpu_encoder_phys_wb_atomic_check( - struct dpu_encoder_phys *phys_enc, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) -{ - struct drm_framebuffer *fb; - const struct drm_display_mode *mode = &crtc_state->mode; - - DPU_DEBUG("[atomic_check:%d, \"%s\",%d,%d]\n", - phys_enc->hw_wb->idx, mode->name, mode->hdisplay, mode->vdisplay); - - if (!conn_state || !conn_state->connector) { - DPU_ERROR("invalid connector state\n"); - return -EINVAL; - } else if (conn_state->connector->status != - connector_status_connected) { - DPU_ERROR("connector not connected %d\n", - conn_state->connector->status); - return -EINVAL; - } - - if (!conn_state->writeback_job || !conn_state->writeback_job->fb) - return 0; - - fb = conn_state->writeback_job->fb; - - DPU_DEBUG("[fb_id:%u][fb:%u,%u]\n", fb->base.id, - fb->width, fb->height); - - if (fb->width != mode->hdisplay) { - DPU_ERROR("invalid fb w=%d, mode w=%d\n", fb->width, - mode->hdisplay); - return -EINVAL; - } else if (fb->height != mode->vdisplay) { - DPU_ERROR("invalid fb h=%d, mode h=%d\n", fb->height, - mode->vdisplay); - return -EINVAL; - } else if (fb->width > phys_enc->hw_wb->caps->maxlinewidth) { - DPU_ERROR("invalid fb w=%d, maxlinewidth=%u\n", - fb->width, phys_enc->hw_wb->caps->maxlinewidth); - return -EINVAL; - } - - return drm_atomic_helper_check_wb_connector_state(conn_state->connector, conn_state->state); -} - - -/** * _dpu_encoder_phys_wb_update_flush - flush hardware update * @phys_enc: Pointer to physical encoder */ @@ -462,6 +319,14 @@ static void dpu_encoder_phys_wb_setup( struct dpu_hw_wb *hw_wb = phys_enc->hw_wb; struct drm_display_mode mode = phys_enc->cached_mode; struct drm_framebuffer *fb = NULL; + struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc); + struct drm_writeback_job *wb_job; + const struct msm_format *format; + const struct dpu_format *dpu_fmt; + + wb_job = wb_enc->wb_job; + format = msm_framebuffer_format(wb_enc->wb_job->fb); + dpu_fmt = dpu_get_dpu_format_ext(format->pixel_format, wb_job->fb->modifier); DPU_DEBUG("[mode_set:%d, \"%s\",%d,%d]\n", hw_wb->idx - WB_0, mode.name, @@ -475,7 +340,7 @@ static void dpu_encoder_phys_wb_setup( dpu_encoder_phys_wb_setup_fb(phys_enc, fb); - dpu_encoder_helper_phys_setup_cdm(phys_enc); + dpu_encoder_helper_phys_setup_cdm(phys_enc, dpu_fmt, CDM_CDWN_OUTPUT_WB); dpu_encoder_phys_wb_setup_ctl(phys_enc); } @@ -511,31 +376,32 @@ static void dpu_encoder_phys_wb_done_irq(void *arg) } /** - * dpu_encoder_phys_wb_irq_ctrl - irq control of WB + * dpu_encoder_phys_wb_irq_enable - irq control of WB * @phys: Pointer to physical encoder - * @enable: indicates enable or disable interrupts */ -static void dpu_encoder_phys_wb_irq_ctrl( - struct dpu_encoder_phys *phys, bool enable) +static void dpu_encoder_phys_wb_irq_enable(struct dpu_encoder_phys *phys) { struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys); - if (enable && atomic_inc_return(&wb_enc->wbirq_refcount) == 1) + if (atomic_inc_return(&wb_enc->wbirq_refcount) == 1) dpu_core_irq_register_callback(phys->dpu_kms, - phys->irq[INTR_IDX_WB_DONE], dpu_encoder_phys_wb_done_irq, phys); - else if (!enable && - atomic_dec_return(&wb_enc->wbirq_refcount) == 0) - dpu_core_irq_unregister_callback(phys->dpu_kms, phys->irq[INTR_IDX_WB_DONE]); + phys->irq[INTR_IDX_WB_DONE], + dpu_encoder_phys_wb_done_irq, + phys); } -static void dpu_encoder_phys_wb_atomic_mode_set( - struct dpu_encoder_phys *phys_enc, - struct drm_crtc_state *crtc_state, - struct drm_connector_state *conn_state) +/** + * dpu_encoder_phys_wb_irq_disable - irq control of WB + * @phys: Pointer to physical encoder + */ +static void dpu_encoder_phys_wb_irq_disable(struct dpu_encoder_phys *phys) { - phys_enc->irq[INTR_IDX_WB_DONE] = phys_enc->hw_wb->caps->intr_wb_done; + struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys); + + if (atomic_dec_return(&wb_enc->wbirq_refcount) == 0) + dpu_core_irq_unregister_callback(phys->dpu_kms, phys->irq[INTR_IDX_WB_DONE]); } static void _dpu_encoder_phys_wb_handle_wbdone_timeout( @@ -774,10 +640,8 @@ static bool dpu_encoder_phys_wb_is_valid_for_commit(struct dpu_encoder_phys *phy static void dpu_encoder_phys_wb_init_ops(struct dpu_encoder_phys_ops *ops) { ops->is_master = dpu_encoder_phys_wb_is_master; - ops->atomic_mode_set = dpu_encoder_phys_wb_atomic_mode_set; ops->enable = dpu_encoder_phys_wb_enable; ops->disable = dpu_encoder_phys_wb_disable; - ops->atomic_check = dpu_encoder_phys_wb_atomic_check; ops->wait_for_commit_done = dpu_encoder_phys_wb_wait_for_commit_done; ops->prepare_for_kickoff = dpu_encoder_phys_wb_prepare_for_kickoff; ops->handle_post_kickoff = dpu_encoder_phys_wb_handle_post_kickoff; @@ -785,7 +649,8 @@ static void dpu_encoder_phys_wb_init_ops(struct dpu_encoder_phys_ops *ops) ops->trigger_start = dpu_encoder_helper_trigger_start; ops->prepare_wb_job = dpu_encoder_phys_wb_prepare_wb_job; ops->cleanup_wb_job = dpu_encoder_phys_wb_cleanup_wb_job; - ops->irq_control = dpu_encoder_phys_wb_irq_ctrl; + ops->irq_enable = dpu_encoder_phys_wb_irq_enable; + ops->irq_disable = dpu_encoder_phys_wb_irq_disable; ops->is_valid_for_commit = dpu_encoder_phys_wb_is_valid_for_commit; } @@ -820,6 +685,7 @@ struct dpu_encoder_phys *dpu_encoder_phys_wb_init(struct drm_device *dev, dpu_encoder_phys_wb_init_ops(&phys_enc->ops); phys_enc->intf_mode = INTF_MODE_WB_LINE; + phys_enc->irq[INTR_IDX_WB_DONE] = phys_enc->hw_wb->caps->intr_wb_done; atomic_set(&wb_enc->wbirq_refcount, 0); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 54e8717403a0..f2b6eac7601d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -680,6 +680,8 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { *************************************************************/ #include "catalog/dpu_3_0_msm8998.h" +#include "catalog/dpu_3_2_sdm660.h" +#include "catalog/dpu_3_3_sdm630.h" #include "catalog/dpu_4_0_sdm845.h" #include "catalog/dpu_4_1_sdm670.h" @@ -703,4 +705,6 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = { #include "catalog/dpu_9_0_sm8550.h" +#include "catalog/dpu_9_2_x1e80100.h" + #include "catalog/dpu_10_0_sm8650.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index ba82ef4560a6..d1aef778340b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -832,6 +832,8 @@ struct dpu_mdss_cfg { }; extern const struct dpu_mdss_cfg dpu_msm8998_cfg; +extern const struct dpu_mdss_cfg dpu_sdm630_cfg; +extern const struct dpu_mdss_cfg dpu_sdm660_cfg; extern const struct dpu_mdss_cfg dpu_sdm845_cfg; extern const struct dpu_mdss_cfg dpu_sdm670_cfg; extern const struct dpu_mdss_cfg dpu_sm8150_cfg; @@ -849,5 +851,6 @@ extern const struct dpu_mdss_cfg dpu_sc8280xp_cfg; extern const struct dpu_mdss_cfg dpu_sm8450_cfg; extern const struct dpu_mdss_cfg dpu_sm8550_cfg; extern const struct dpu_mdss_cfg dpu_sm8650_cfg; +extern const struct dpu_mdss_cfg dpu_x1e80100_cfg; #endif /* _DPU_HW_CATALOG_H */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c index e9cdc7934a49..9016b3ade6bc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_cdm.c @@ -186,7 +186,7 @@ static int dpu_hw_cdm_enable(struct dpu_hw_cdm *ctx, struct dpu_hw_cdm_cfg *cdm) dpu_hw_cdm_setup_cdwn(ctx, cdm); if (cdm->output_type == CDM_CDWN_OUTPUT_HDMI) { - if (fmt->chroma_sample != DPU_CHROMA_H1V2) + if (fmt->chroma_sample == DPU_CHROMA_H1V2) return -EINVAL; /*unsupported format */ opmode = CDM_HDMI_PACK_OP_MODE_EN; opmode |= (fmt->chroma_sample << 1); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index e76565c3e6a4..a06f69d0b257 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -39,6 +39,7 @@ #define CTL_WB_FLUSH 0x108 #define CTL_INTF_FLUSH 0x110 #define CTL_CDM_FLUSH 0x114 +#define CTL_PERIPH_FLUSH 0x128 #define CTL_INTF_MASTER 0x134 #define CTL_DSPP_n_FLUSH(n) ((0x13C) + ((n) * 4)) @@ -49,6 +50,7 @@ #define MERGE_3D_IDX 23 #define DSC_IDX 22 #define CDM_IDX 26 +#define PERIPH_IDX 30 #define INTF_IDX 31 #define WB_IDX 16 #define DSPP_IDX 29 /* From DPU hw rev 7.x.x */ @@ -151,6 +153,10 @@ static inline void dpu_hw_ctl_trigger_flush_v1(struct dpu_hw_ctl *ctx) ctx->pending_dspp_flush_mask[dspp - DSPP_0]); } + if (ctx->pending_flush_mask & BIT(PERIPH_IDX)) + DPU_REG_WRITE(&ctx->hw, CTL_PERIPH_FLUSH, + ctx->pending_periph_flush_mask); + if (ctx->pending_flush_mask & BIT(DSC_IDX)) DPU_REG_WRITE(&ctx->hw, CTL_DSC_FLUSH, ctx->pending_dsc_flush_mask); @@ -311,6 +317,13 @@ static void dpu_hw_ctl_update_pending_flush_intf_v1(struct dpu_hw_ctl *ctx, ctx->pending_flush_mask |= BIT(INTF_IDX); } +static void dpu_hw_ctl_update_pending_flush_periph_v1(struct dpu_hw_ctl *ctx, + enum dpu_intf intf) +{ + ctx->pending_periph_flush_mask |= BIT(intf - INTF_0); + ctx->pending_flush_mask |= BIT(PERIPH_IDX); +} + static void dpu_hw_ctl_update_pending_flush_merge_3d_v1(struct dpu_hw_ctl *ctx, enum dpu_merge_3d merge_3d) { @@ -680,6 +693,10 @@ static void _setup_ctl_ops(struct dpu_hw_ctl_ops *ops, ops->reset_intf_cfg = dpu_hw_ctl_reset_intf_cfg_v1; ops->update_pending_flush_intf = dpu_hw_ctl_update_pending_flush_intf_v1; + + ops->update_pending_flush_periph = + dpu_hw_ctl_update_pending_flush_periph_v1; + ops->update_pending_flush_merge_3d = dpu_hw_ctl_update_pending_flush_merge_3d_v1; ops->update_pending_flush_wb = dpu_hw_ctl_update_pending_flush_wb_v1; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h index ff85b5ee0acf..ef56280bea93 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -123,6 +123,15 @@ struct dpu_hw_ctl_ops { enum dpu_intf blk); /** + * OR in the given flushbits to the cached pending_(periph_)flush_mask + * No effect on hardware + * @ctx : ctl path ctx pointer + * @blk : interface block index + */ + void (*update_pending_flush_periph)(struct dpu_hw_ctl *ctx, + enum dpu_intf blk); + + /** * OR in the given flushbits to the cached pending_(merge_3d_)flush_mask * No effect on hardware * @ctx : ctl path ctx pointer @@ -264,6 +273,7 @@ struct dpu_hw_ctl { u32 pending_flush_mask; u32 pending_intf_flush_mask; u32 pending_wb_flush_mask; + u32 pending_periph_flush_mask; u32 pending_merge_3d_flush_mask; u32 pending_dspp_flush_mask[DSPP_MAX - DSPP_0]; u32 pending_dsc_flush_mask; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c index 6bba531d6dc4..965692ef7892 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c @@ -163,13 +163,8 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, hsync_ctl = (hsync_period << 16) | p->hsync_pulse_width; display_hctl = (hsync_end_x << 16) | hsync_start_x; - /* - * DATA_HCTL_EN controls data timing which can be different from - * video timing. It is recommended to enable it for all cases, except - * if compression is enabled in 1 pixel per clock mode - */ if (p->wide_bus_en) - intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN | INTF_CFG2_DATA_HCTL_EN; + intf_cfg2 |= INTF_CFG2_DATABUS_WIDEN; data_width = p->width; @@ -229,6 +224,14 @@ static void dpu_hw_intf_setup_timing_engine(struct dpu_hw_intf *ctx, DPU_REG_WRITE(c, INTF_CONFIG, intf_cfg); DPU_REG_WRITE(c, INTF_PANEL_FORMAT, panel_format); if (ctx->cap->features & BIT(DPU_DATA_HCTL_EN)) { + /* + * DATA_HCTL_EN controls data timing which can be different from + * video timing. It is recommended to enable it for all cases, except + * if compression is enabled in 1 pixel per clock mode + */ + if (!(p->compression_en && !p->wide_bus_en)) + intf_cfg2 |= INTF_CFG2_DATA_HCTL_EN; + DPU_REG_WRITE(c, INTF_CONFIG2, intf_cfg2); DPU_REG_WRITE(c, INTF_DISPLAY_DATA_HCTL, display_data_hctl); DPU_REG_WRITE(c, INTF_ACTIVE_DATA_HCTL, active_data_hctl); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h index 0bd57a32144a..6f4c87244f94 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h @@ -33,6 +33,7 @@ struct dpu_hw_intf_timing_params { u32 hsync_skew; bool wide_bus_en; + bool compression_en; }; struct dpu_hw_intf_prog_fetch { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 723cc1d82143..a1f5d7c4ab91 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -317,11 +317,6 @@ struct dpu_global_state *dpu_kms_get_global_state(struct drm_atomic_state *s) struct msm_drm_private *priv = s->dev->dev_private; struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms); struct drm_private_state *priv_state; - int ret; - - ret = drm_modeset_lock(&dpu_kms->global_state_lock, s->acquire_ctx); - if (ret) - return ERR_PTR(ret); priv_state = drm_atomic_get_private_obj_state(s, &dpu_kms->global_state); @@ -362,8 +357,6 @@ static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms) { struct dpu_global_state *state; - drm_modeset_lock_init(&dpu_kms->global_state_lock); - state = kzalloc(sizeof(*state), GFP_KERNEL); if (!state) return -ENOMEM; @@ -374,6 +367,11 @@ static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms) return 0; } +static void dpu_kms_global_obj_fini(struct dpu_kms *dpu_kms) +{ + drm_atomic_private_obj_fini(&dpu_kms->global_state); +} + static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms) { struct icc_path *path0; @@ -478,7 +476,7 @@ static void dpu_kms_wait_for_commit_done(struct msm_kms *kms, * mode panels. This may be a no-op for command mode panels. */ trace_dpu_kms_wait_for_commit_done(DRMID(crtc)); - ret = dpu_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE); + ret = dpu_encoder_wait_for_commit_done(encoder); if (ret && ret != -EWOULDBLOCK) { DPU_ERROR("wait for commit done returned %d\n", ret); break; @@ -565,6 +563,7 @@ static int _dpu_kms_initialize_displayport(struct drm_device *dev, { struct drm_encoder *encoder = NULL; struct msm_display_info info; + bool yuv_supported; int rc; int i; @@ -583,7 +582,8 @@ static int _dpu_kms_initialize_displayport(struct drm_device *dev, return PTR_ERR(encoder); } - rc = msm_dp_modeset_init(priv->dp[i], dev, encoder); + yuv_supported = !!dpu_kms->catalog->cdm; + rc = msm_dp_modeset_init(priv->dp[i], dev, encoder, yuv_supported); if (rc) { DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc); return rc; @@ -630,23 +630,26 @@ static int _dpu_kms_initialize_writeback(struct drm_device *dev, { struct drm_encoder *encoder = NULL; struct msm_display_info info; + const enum dpu_wb wb_idx = WB_2; + u32 maxlinewidth; int rc; memset(&info, 0, sizeof(info)); info.num_of_h_tiles = 1; /* use only WB idx 2 instance for DPU */ - info.h_tile_instance[0] = WB_2; + info.h_tile_instance[0] = wb_idx; info.intf_type = INTF_WB; + maxlinewidth = dpu_rm_get_wb(&dpu_kms->rm, info.h_tile_instance[0])->caps->maxlinewidth; + encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_VIRTUAL, &info); if (IS_ERR(encoder)) { DPU_ERROR("encoder init failed for dsi display\n"); return PTR_ERR(encoder); } - rc = dpu_writeback_init(dev, encoder, wb_formats, - n_formats); + rc = dpu_writeback_init(dev, encoder, wb_formats, n_formats, maxlinewidth); if (rc) { DPU_ERROR("dpu_writeback_init, rc = %d\n", rc); return rc; @@ -801,6 +804,8 @@ static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms) dpu_kms->hw_vbif[i] = NULL; } + dpu_kms_global_obj_fini(dpu_kms); + dpu_kms->catalog = NULL; dpu_kms->hw_mdp = NULL; @@ -1197,6 +1202,78 @@ static int dpu_kms_init(struct drm_device *ddev) return 0; } +static int dpu_kms_mmap_mdp5(struct dpu_kms *dpu_kms) +{ + struct platform_device *pdev = dpu_kms->pdev; + struct platform_device *mdss_dev; + int ret; + + if (!dev_is_platform(dpu_kms->pdev->dev.parent)) + return -EINVAL; + + mdss_dev = to_platform_device(dpu_kms->pdev->dev.parent); + + dpu_kms->mmio = msm_ioremap(pdev, "mdp_phys"); + if (IS_ERR(dpu_kms->mmio)) { + ret = PTR_ERR(dpu_kms->mmio); + DPU_ERROR("mdp register memory map failed: %d\n", ret); + dpu_kms->mmio = NULL; + return ret; + } + DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio); + + dpu_kms->vbif[VBIF_RT] = msm_ioremap_mdss(mdss_dev, + dpu_kms->pdev, + "vbif_phys"); + if (IS_ERR(dpu_kms->vbif[VBIF_RT])) { + ret = PTR_ERR(dpu_kms->vbif[VBIF_RT]); + DPU_ERROR("vbif register memory map failed: %d\n", ret); + dpu_kms->vbif[VBIF_RT] = NULL; + return ret; + } + + dpu_kms->vbif[VBIF_NRT] = msm_ioremap_mdss(mdss_dev, + dpu_kms->pdev, + "vbif_nrt_phys"); + if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) { + dpu_kms->vbif[VBIF_NRT] = NULL; + DPU_DEBUG("VBIF NRT is not defined"); + } + + return 0; +} + +static int dpu_kms_mmap_dpu(struct dpu_kms *dpu_kms) +{ + struct platform_device *pdev = dpu_kms->pdev; + int ret; + + dpu_kms->mmio = msm_ioremap(pdev, "mdp"); + if (IS_ERR(dpu_kms->mmio)) { + ret = PTR_ERR(dpu_kms->mmio); + DPU_ERROR("mdp register memory map failed: %d\n", ret); + dpu_kms->mmio = NULL; + return ret; + } + DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio); + + dpu_kms->vbif[VBIF_RT] = msm_ioremap(pdev, "vbif"); + if (IS_ERR(dpu_kms->vbif[VBIF_RT])) { + ret = PTR_ERR(dpu_kms->vbif[VBIF_RT]); + DPU_ERROR("vbif register memory map failed: %d\n", ret); + dpu_kms->vbif[VBIF_RT] = NULL; + return ret; + } + + dpu_kms->vbif[VBIF_NRT] = msm_ioremap_quiet(pdev, "vbif_nrt"); + if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) { + dpu_kms->vbif[VBIF_NRT] = NULL; + DPU_DEBUG("VBIF NRT is not defined"); + } + + return 0; +} + static int dpu_dev_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -1204,6 +1281,9 @@ static int dpu_dev_probe(struct platform_device *pdev) int irq; int ret = 0; + if (!msm_disp_drv_should_bind(&pdev->dev, true)) + return -ENODEV; + dpu_kms = devm_kzalloc(dev, sizeof(*dpu_kms), GFP_KERNEL); if (!dpu_kms) return -ENOMEM; @@ -1230,28 +1310,12 @@ static int dpu_dev_probe(struct platform_device *pdev) dpu_kms->base.irq = irq; - dpu_kms->mmio = msm_ioremap(pdev, "mdp"); - if (IS_ERR(dpu_kms->mmio)) { - ret = PTR_ERR(dpu_kms->mmio); - DPU_ERROR("mdp register memory map failed: %d\n", ret); - dpu_kms->mmio = NULL; - return ret; - } - DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio); - - dpu_kms->vbif[VBIF_RT] = msm_ioremap(pdev, "vbif"); - if (IS_ERR(dpu_kms->vbif[VBIF_RT])) { - ret = PTR_ERR(dpu_kms->vbif[VBIF_RT]); - DPU_ERROR("vbif register memory map failed: %d\n", ret); - dpu_kms->vbif[VBIF_RT] = NULL; + if (of_device_is_compatible(dpu_kms->pdev->dev.of_node, "qcom,mdp5")) + ret = dpu_kms_mmap_mdp5(dpu_kms); + else + ret = dpu_kms_mmap_dpu(dpu_kms); + if (ret) return ret; - } - - dpu_kms->vbif[VBIF_NRT] = msm_ioremap_quiet(pdev, "vbif_nrt"); - if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) { - dpu_kms->vbif[VBIF_NRT] = NULL; - DPU_DEBUG("VBIF NRT is not defined"); - } ret = dpu_kms_parse_data_bus_icc_path(dpu_kms); if (ret) @@ -1318,6 +1382,8 @@ static const struct dev_pm_ops dpu_pm_ops = { static const struct of_device_id dpu_dt_match[] = { { .compatible = "qcom,msm8998-dpu", .data = &dpu_msm8998_cfg, }, { .compatible = "qcom,qcm2290-dpu", .data = &dpu_qcm2290_cfg, }, + { .compatible = "qcom,sdm630-mdp5", .data = &dpu_sdm630_cfg, }, + { .compatible = "qcom,sdm660-mdp5", .data = &dpu_sdm660_cfg, }, { .compatible = "qcom,sdm670-dpu", .data = &dpu_sdm670_cfg, }, { .compatible = "qcom,sdm845-dpu", .data = &dpu_sdm845_cfg, }, { .compatible = "qcom,sc7180-dpu", .data = &dpu_sc7180_cfg, }, @@ -1334,6 +1400,7 @@ static const struct of_device_id dpu_dt_match[] = { { .compatible = "qcom,sm8450-dpu", .data = &dpu_sm8450_cfg, }, { .compatible = "qcom,sm8550-dpu", .data = &dpu_sm8550_cfg, }, { .compatible = "qcom,sm8650-dpu", .data = &dpu_sm8650_cfg, }, + { .compatible = "qcom,x1e80100-dpu", .data = &dpu_x1e80100_cfg, }, {} }; MODULE_DEVICE_TABLE(of, dpu_dt_match); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h index d1207f4ec3ae..b5db3fc76ca6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.h @@ -85,7 +85,6 @@ struct dpu_kms { * Global private object state, Do not access directly, use * dpu_kms_global_get_state() */ - struct drm_modeset_lock global_state_lock; struct drm_private_obj global_state; struct dpu_rm rm; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c index 724537ab776d..cb5ce3c62a22 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c @@ -409,29 +409,153 @@ static int _dpu_rm_reserve_ctls( return 0; } -static int _dpu_rm_reserve_dsc(struct dpu_rm *rm, - struct dpu_global_state *global_state, - struct drm_encoder *enc, - const struct msm_display_topology *top) +static int _dpu_rm_pingpong_next_index(struct dpu_global_state *global_state, + int start, + uint32_t enc_id) { - int num_dsc = top->num_dsc; int i; - /* check if DSC required are allocated or not */ - for (i = 0; i < num_dsc; i++) { - if (!rm->dsc_blks[i]) { - DPU_ERROR("DSC %d does not exist\n", i); - return -EIO; + for (i = start; i < (PINGPONG_MAX - PINGPONG_0); i++) { + if (global_state->pingpong_to_enc_id[i] == enc_id) + return i; + } + + return -ENAVAIL; +} + +static int _dpu_rm_pingpong_dsc_check(int dsc_idx, int pp_idx) +{ + /* + * DSC with even index must be used with the PINGPONG with even index + * DSC with odd index must be used with the PINGPONG with odd index + */ + if ((dsc_idx & 0x01) != (pp_idx & 0x01)) + return -ENAVAIL; + + return 0; +} + +static int _dpu_rm_dsc_alloc(struct dpu_rm *rm, + struct dpu_global_state *global_state, + uint32_t enc_id, + const struct msm_display_topology *top) +{ + int num_dsc = 0; + int pp_idx = 0; + int dsc_idx; + int ret; + + for (dsc_idx = 0; dsc_idx < ARRAY_SIZE(rm->dsc_blks) && + num_dsc < top->num_dsc; dsc_idx++) { + if (!rm->dsc_blks[dsc_idx]) + continue; + + if (reserved_by_other(global_state->dsc_to_enc_id, dsc_idx, enc_id)) + continue; + + pp_idx = _dpu_rm_pingpong_next_index(global_state, pp_idx, enc_id); + if (pp_idx < 0) + return -ENAVAIL; + + ret = _dpu_rm_pingpong_dsc_check(dsc_idx, pp_idx); + if (ret) + return -ENAVAIL; + + global_state->dsc_to_enc_id[dsc_idx] = enc_id; + num_dsc++; + pp_idx++; + } + + if (num_dsc < top->num_dsc) { + DPU_ERROR("DSC allocation failed num_dsc=%d required=%d\n", + num_dsc, top->num_dsc); + return -ENAVAIL; + } + + return 0; +} + +static int _dpu_rm_dsc_alloc_pair(struct dpu_rm *rm, + struct dpu_global_state *global_state, + uint32_t enc_id, + const struct msm_display_topology *top) +{ + int num_dsc = 0; + int dsc_idx, pp_idx = 0; + int ret; + + /* only start from even dsc index */ + for (dsc_idx = 0; dsc_idx < ARRAY_SIZE(rm->dsc_blks) && + num_dsc < top->num_dsc; dsc_idx += 2) { + if (!rm->dsc_blks[dsc_idx] || + !rm->dsc_blks[dsc_idx + 1]) + continue; + + /* consective dsc index to be paired */ + if (reserved_by_other(global_state->dsc_to_enc_id, dsc_idx, enc_id) || + reserved_by_other(global_state->dsc_to_enc_id, dsc_idx + 1, enc_id)) + continue; + + pp_idx = _dpu_rm_pingpong_next_index(global_state, pp_idx, enc_id); + if (pp_idx < 0) + return -ENAVAIL; + + ret = _dpu_rm_pingpong_dsc_check(dsc_idx, pp_idx); + if (ret) { + pp_idx = 0; + continue; } - if (global_state->dsc_to_enc_id[i]) { - DPU_ERROR("DSC %d is already allocated\n", i); - return -EIO; + pp_idx = _dpu_rm_pingpong_next_index(global_state, pp_idx + 1, enc_id); + if (pp_idx < 0) + return -ENAVAIL; + + ret = _dpu_rm_pingpong_dsc_check(dsc_idx + 1, pp_idx); + if (ret) { + pp_idx = 0; + continue; } + + global_state->dsc_to_enc_id[dsc_idx] = enc_id; + global_state->dsc_to_enc_id[dsc_idx + 1] = enc_id; + num_dsc += 2; + pp_idx++; /* start for next pair */ } - for (i = 0; i < num_dsc; i++) - global_state->dsc_to_enc_id[i] = enc->base.id; + if (num_dsc < top->num_dsc) { + DPU_ERROR("DSC allocation failed num_dsc=%d required=%d\n", + num_dsc, top->num_dsc); + return -ENAVAIL; + } + + return 0; +} + +static int _dpu_rm_reserve_dsc(struct dpu_rm *rm, + struct dpu_global_state *global_state, + struct drm_encoder *enc, + const struct msm_display_topology *top) +{ + uint32_t enc_id = enc->base.id; + + if (!top->num_dsc || !top->num_intf) + return 0; + + /* + * Facts: + * 1) no pingpong split (two layer mixers shared one pingpong) + * 2) DSC pair starts from even index, such as index(0,1), (2,3), etc + * 3) even PINGPONG connects to even DSC + * 4) odd PINGPONG connects to odd DSC + * 5) pair: encoder +--> pp_idx_0 --> dsc_idx_0 + * +--> pp_idx_1 --> dsc_idx_1 + */ + + /* num_dsc should be either 1, 2 or 4 */ + if (top->num_dsc > top->num_intf) /* merge mode */ + return _dpu_rm_dsc_alloc_pair(rm, global_state, enc_id, top); + else + return _dpu_rm_dsc_alloc(rm, global_state, enc_id, top); return 0; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h index 35d03b121a0b..bd92fb2979aa 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h @@ -273,6 +273,14 @@ DEFINE_EVENT(dpu_drm_obj_template, dpu_crtc_runtime_resume, TP_PROTO(uint32_t drm_id), TP_ARGS(drm_id) ); +DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_rc_enable, + TP_PROTO(uint32_t drm_id), + TP_ARGS(drm_id) +); +DEFINE_EVENT(dpu_drm_obj_template, dpu_enc_rc_disable, + TP_PROTO(uint32_t drm_id), + TP_ARGS(drm_id) +); TRACE_EVENT(dpu_enc_enable, TP_PROTO(uint32_t drm_id, int hdisplay, int vdisplay), @@ -342,10 +350,6 @@ DECLARE_EVENT_CLASS(dpu_enc_id_enable_template, TP_printk("id=%u, enable=%s", __entry->drm_id, __entry->enable ? "true" : "false") ); -DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_rc_helper, - TP_PROTO(uint32_t drm_id, bool enable), - TP_ARGS(drm_id, enable) -); DEFINE_EVENT(dpu_enc_id_enable_template, dpu_enc_vblank_cb, TP_PROTO(uint32_t drm_id, bool enable), TP_ARGS(drm_id, enable) @@ -514,24 +518,41 @@ TRACE_EVENT(dpu_enc_wait_event_timeout, __entry->expected_time, __entry->atomic_cnt) ); -TRACE_EVENT(dpu_enc_phys_cmd_irq_ctrl, - TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, bool enable, +TRACE_EVENT(dpu_enc_phys_cmd_irq_enable, + TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, int refcnt), - TP_ARGS(drm_id, pp, enable, refcnt), + TP_ARGS(drm_id, pp, refcnt), + TP_STRUCT__entry( + __field( uint32_t, drm_id ) + __field( enum dpu_pingpong, pp ) + __field( int, refcnt ) + ), + TP_fast_assign( + __entry->drm_id = drm_id; + __entry->pp = pp; + __entry->refcnt = refcnt; + ), + TP_printk("id=%u, pp=%d, refcnt=%d", __entry->drm_id, + __entry->pp, + __entry->refcnt) +); + +TRACE_EVENT(dpu_enc_phys_cmd_irq_disable, + TP_PROTO(uint32_t drm_id, enum dpu_pingpong pp, + int refcnt), + TP_ARGS(drm_id, pp, refcnt), TP_STRUCT__entry( __field( uint32_t, drm_id ) __field( enum dpu_pingpong, pp ) - __field( bool, enable ) __field( int, refcnt ) ), TP_fast_assign( __entry->drm_id = drm_id; __entry->pp = pp; - __entry->enable = enable; __entry->refcnt = refcnt; ), - TP_printk("id=%u, pp=%d, enable=%s, refcnt=%d", __entry->drm_id, - __entry->pp, __entry->enable ? "true" : "false", + TP_printk("id=%u, pp=%d, refcnt=%d", __entry->drm_id, + __entry->pp, __entry->refcnt) ); @@ -592,24 +613,41 @@ TRACE_EVENT(dpu_enc_phys_vid_post_kickoff, TP_printk("id=%u, intf_idx=%d", __entry->drm_id, __entry->intf_idx) ); -TRACE_EVENT(dpu_enc_phys_vid_irq_ctrl, - TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx, bool enable, +TRACE_EVENT(dpu_enc_phys_vid_irq_enable, + TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx, int refcnt), - TP_ARGS(drm_id, intf_idx, enable, refcnt), + TP_ARGS(drm_id, intf_idx, refcnt), + TP_STRUCT__entry( + __field( uint32_t, drm_id ) + __field( enum dpu_intf, intf_idx ) + __field( int, refcnt ) + ), + TP_fast_assign( + __entry->drm_id = drm_id; + __entry->intf_idx = intf_idx; + __entry->refcnt = refcnt; + ), + TP_printk("id=%u, intf_idx=%d refcnt=%d", __entry->drm_id, + __entry->intf_idx, + __entry->drm_id) +); + +TRACE_EVENT(dpu_enc_phys_vid_irq_disable, + TP_PROTO(uint32_t drm_id, enum dpu_intf intf_idx, + int refcnt), + TP_ARGS(drm_id, intf_idx, refcnt), TP_STRUCT__entry( __field( uint32_t, drm_id ) __field( enum dpu_intf, intf_idx ) - __field( bool, enable ) __field( int, refcnt ) ), TP_fast_assign( __entry->drm_id = drm_id; __entry->intf_idx = intf_idx; - __entry->enable = enable; __entry->refcnt = refcnt; ), - TP_printk("id=%u, intf_idx=%d enable=%s refcnt=%d", __entry->drm_id, - __entry->intf_idx, __entry->enable ? "true" : "false", + TP_printk("id=%u, intf_idx=%d refcnt=%d", __entry->drm_id, + __entry->intf_idx, __entry->drm_id) ); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c index 2a5a68366582..16f144cbc0c9 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.c @@ -4,6 +4,7 @@ */ #include <drm/drm_edid.h> +#include <drm/drm_framebuffer.h> #include "dpu_writeback.h" @@ -24,6 +25,61 @@ static int dpu_wb_conn_get_modes(struct drm_connector *connector) dev->mode_config.max_height); } +static int dpu_wb_conn_atomic_check(struct drm_connector *connector, + struct drm_atomic_state *state) +{ + struct drm_writeback_connector *wb_conn = drm_connector_to_writeback(connector); + struct dpu_wb_connector *dpu_wb_conn = to_dpu_wb_conn(wb_conn); + struct drm_connector_state *conn_state = + drm_atomic_get_new_connector_state(state, connector); + struct drm_crtc *crtc; + struct drm_crtc_state *crtc_state; + const struct drm_display_mode *mode; + struct drm_framebuffer *fb; + + DPU_DEBUG("[atomic_check:%d]\n", connector->base.id); + + if (!conn_state || !conn_state->connector) { + DPU_ERROR("invalid connector state\n"); + return -EINVAL; + } else if (conn_state->connector->status != connector_status_connected) { + DPU_ERROR("connector not connected %d\n", conn_state->connector->status); + return -EINVAL; + } + + crtc = conn_state->crtc; + if (!crtc) + return 0; + + if (!conn_state->writeback_job || !conn_state->writeback_job->fb) + return 0; + + crtc_state = drm_atomic_get_crtc_state(state, crtc); + if (IS_ERR(crtc_state)) + return PTR_ERR(crtc_state); + + mode = &crtc_state->mode; + + fb = conn_state->writeback_job->fb; + + DPU_DEBUG("[fb_id:%u][fb:%u,%u][mode:\"%s\":%ux%u]\n", fb->base.id, fb->width, fb->height, + mode->name, mode->hdisplay, mode->vdisplay); + + if (fb->width != mode->hdisplay) { + DPU_ERROR("invalid fb w=%d, mode w=%d\n", fb->width, mode->hdisplay); + return -EINVAL; + } else if (fb->height != mode->vdisplay) { + DPU_ERROR("invalid fb h=%d, mode h=%d\n", fb->height, mode->vdisplay); + return -EINVAL; + } else if (fb->width > dpu_wb_conn->maxlinewidth) { + DPU_ERROR("invalid fb w=%d, maxlinewidth=%u\n", + fb->width, dpu_wb_conn->maxlinewidth); + return -EINVAL; + } + + return drm_atomic_helper_check_wb_connector_state(conn_state->connector, conn_state->state); +} + static const struct drm_connector_funcs dpu_wb_conn_funcs = { .reset = drm_atomic_helper_connector_reset, .fill_modes = drm_helper_probe_single_connector_modes, @@ -59,12 +115,13 @@ static void dpu_wb_conn_cleanup_job(struct drm_writeback_connector *connector, static const struct drm_connector_helper_funcs dpu_wb_conn_helper_funcs = { .get_modes = dpu_wb_conn_get_modes, + .atomic_check = dpu_wb_conn_atomic_check, .prepare_writeback_job = dpu_wb_conn_prepare_job, .cleanup_writeback_job = dpu_wb_conn_cleanup_job, }; int dpu_writeback_init(struct drm_device *dev, struct drm_encoder *enc, - const u32 *format_list, u32 num_formats) + const u32 *format_list, u32 num_formats, u32 maxlinewidth) { struct dpu_wb_connector *dpu_wb_conn; int rc = 0; @@ -73,6 +130,8 @@ int dpu_writeback_init(struct drm_device *dev, struct drm_encoder *enc, if (!dpu_wb_conn) return -ENOMEM; + dpu_wb_conn->maxlinewidth = maxlinewidth; + drm_connector_helper_add(&dpu_wb_conn->base.base, &dpu_wb_conn_helper_funcs); /* DPU initializes the encoder and sets it up completely for writeback diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.h index 5a75ea916101..4b11cca8014c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_writeback.h @@ -18,6 +18,7 @@ struct dpu_wb_connector { struct drm_writeback_connector base; struct drm_encoder *wb_enc; + u32 maxlinewidth; }; static inline struct dpu_wb_connector *to_dpu_wb_conn(struct drm_writeback_connector *conn) @@ -26,6 +27,6 @@ static inline struct dpu_wb_connector *to_dpu_wb_conn(struct drm_writeback_conne } int dpu_writeback_init(struct drm_device *dev, struct drm_encoder *enc, - const u32 *format_list, u32 num_formats); + const u32 *format_list, u32 num_formats, u32 maxlinewidth); #endif /*_DPU_WRITEBACK_H */ diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c index a640af22eafc..e5662412db9b 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cmd_encoder.c @@ -158,46 +158,4 @@ void mdp5_cmd_encoder_enable(struct drm_encoder *encoder) mdp5_cmd_enc->enabled = true; } - -int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder, - struct drm_encoder *slave_encoder) -{ - struct mdp5_encoder *mdp5_cmd_enc = to_mdp5_encoder(encoder); - struct mdp5_kms *mdp5_kms; - struct device *dev; - int intf_num; - u32 data = 0; - - if (!encoder || !slave_encoder) - return -EINVAL; - - mdp5_kms = get_kms(encoder); - intf_num = mdp5_cmd_enc->intf->num; - - /* Switch slave encoder's trigger MUX, to use the master's - * start signal for the slave encoder - */ - if (intf_num == 1) - data |= MDP5_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX; - else if (intf_num == 2) - data |= MDP5_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX; - else - return -EINVAL; - - /* Smart Panel, Sync mode */ - data |= MDP5_SPLIT_DPL_UPPER_SMART_PANEL; - - dev = &mdp5_kms->pdev->dev; - - /* Make sure clocks are on when connectors calling this function. */ - pm_runtime_get_sync(dev); - mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, data); - - mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER, - MDP5_SPLIT_DPL_LOWER_SMART_PANEL); - mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1); - pm_runtime_put_sync(dev); - - return 0; -} #endif /* CONFIG_DRM_MSM_DSI */ diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c index 8db97083e14d..eaba3b2d73b5 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_encoder.c @@ -263,48 +263,6 @@ u32 mdp5_encoder_get_framecount(struct drm_encoder *encoder) return mdp5_read(mdp5_kms, REG_MDP5_INTF_FRAME_COUNT(intf)); } -int mdp5_vid_encoder_set_split_display(struct drm_encoder *encoder, - struct drm_encoder *slave_encoder) -{ - struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder); - struct mdp5_encoder *mdp5_slave_enc = to_mdp5_encoder(slave_encoder); - struct mdp5_kms *mdp5_kms; - struct device *dev; - int intf_num; - u32 data = 0; - - if (!encoder || !slave_encoder) - return -EINVAL; - - mdp5_kms = get_kms(encoder); - intf_num = mdp5_encoder->intf->num; - - /* Switch slave encoder's TimingGen Sync mode, - * to use the master's enable signal for the slave encoder. - */ - if (intf_num == 1) - data |= MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC; - else if (intf_num == 2) - data |= MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC; - else - return -EINVAL; - - dev = &mdp5_kms->pdev->dev; - /* Make sure clocks are on when connectors calling this function. */ - pm_runtime_get_sync(dev); - - /* Dumb Panel, Sync mode */ - mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_UPPER, 0); - mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_LOWER, data); - mdp5_write(mdp5_kms, REG_MDP5_SPLIT_DPL_EN, 1); - - mdp5_ctl_pair(mdp5_encoder->ctl, mdp5_slave_enc->ctl, true); - - pm_runtime_put_sync(dev); - - return 0; -} - void mdp5_encoder_set_intf_mode(struct drm_encoder *encoder, bool cmd_mode) { struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder); diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c index 43443a435d59..b40ed3a847c8 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_irq.c @@ -31,8 +31,6 @@ static void mdp5_irq_error_handler(struct mdp_irq *irq, uint32_t irqstatus) if (dumpstate && __ratelimit(&rs)) { struct drm_printer p = drm_info_printer(mdp5_kms->dev->dev); drm_state_dump(mdp5_kms->dev, &p); - if (mdp5_kms->smp) - mdp5_smp_dump(mdp5_kms->smp, &p); } } diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c index 0827634664ae..a874fd95cc20 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c @@ -84,11 +84,6 @@ struct mdp5_global_state *mdp5_get_global_state(struct drm_atomic_state *s) struct msm_drm_private *priv = s->dev->dev_private; struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); struct drm_private_state *priv_state; - int ret; - - ret = drm_modeset_lock(&mdp5_kms->glob_state_lock, s->acquire_ctx); - if (ret) - return ERR_PTR(ret); priv_state = drm_atomic_get_private_obj_state(s, &mdp5_kms->glob_state); if (IS_ERR(priv_state)) @@ -119,17 +114,25 @@ static void mdp5_global_destroy_state(struct drm_private_obj *obj, kfree(mdp5_state); } +static void mdp5_global_print_state(struct drm_printer *p, + const struct drm_private_state *state) +{ + struct mdp5_global_state *mdp5_state = to_mdp5_global_state(state); + + if (mdp5_state->mdp5_kms->smp) + mdp5_smp_dump(mdp5_state->mdp5_kms->smp, p, mdp5_state); +} + static const struct drm_private_state_funcs mdp5_global_state_funcs = { .atomic_duplicate_state = mdp5_global_duplicate_state, .atomic_destroy_state = mdp5_global_destroy_state, + .atomic_print_state = mdp5_global_print_state, }; static int mdp5_global_obj_init(struct mdp5_kms *mdp5_kms) { struct mdp5_global_state *state; - drm_modeset_lock_init(&mdp5_kms->glob_state_lock); - state = kzalloc(sizeof(*state), GFP_KERNEL); if (!state) return -ENOMEM; @@ -190,19 +193,6 @@ static void mdp5_complete_commit(struct msm_kms *kms, unsigned crtc_mask) mdp5_smp_complete_commit(mdp5_kms->smp, &global_state->smp); } -static int mdp5_set_split_display(struct msm_kms *kms, - struct drm_encoder *encoder, - struct drm_encoder *slave_encoder, - bool is_cmd_mode) -{ - if (is_cmd_mode) - return mdp5_cmd_encoder_set_split_display(encoder, - slave_encoder); - else - return mdp5_vid_encoder_set_split_display(encoder, - slave_encoder); -} - static void mdp5_destroy(struct mdp5_kms *mdp5_kms); static void mdp5_kms_destroy(struct msm_kms *kms) @@ -219,39 +209,6 @@ static void mdp5_kms_destroy(struct msm_kms *kms) mdp5_destroy(mdp5_kms); } -#ifdef CONFIG_DEBUG_FS -static int smp_show(struct seq_file *m, void *arg) -{ - struct drm_info_node *node = m->private; - struct drm_device *dev = node->minor->dev; - struct msm_drm_private *priv = dev->dev_private; - struct mdp5_kms *mdp5_kms = to_mdp5_kms(to_mdp_kms(priv->kms)); - struct drm_printer p = drm_seq_file_printer(m); - - if (!mdp5_kms->smp) { - drm_printf(&p, "no SMP pool\n"); - return 0; - } - - mdp5_smp_dump(mdp5_kms->smp, &p); - - return 0; -} - -static struct drm_info_list mdp5_debugfs_list[] = { - {"smp", smp_show }, -}; - -static int mdp5_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor) -{ - drm_debugfs_create_files(mdp5_debugfs_list, - ARRAY_SIZE(mdp5_debugfs_list), - minor->debugfs_root, minor); - - return 0; -} -#endif - static const struct mdp_kms_funcs kms_funcs = { .base = { .hw_init = mdp5_hw_init, @@ -268,11 +225,7 @@ static const struct mdp_kms_funcs kms_funcs = { .wait_flush = mdp5_wait_flush, .complete_commit = mdp5_complete_commit, .get_format = mdp_get_format, - .set_split_display = mdp5_set_split_display, .destroy = mdp5_kms_destroy, -#ifdef CONFIG_DEBUG_FS - .debugfs_init = mdp5_kms_debugfs_init, -#endif }, .set_irqmask = mdp5_set_irqmask, }; @@ -620,7 +573,6 @@ static void mdp5_destroy(struct mdp5_kms *mdp5_kms) pm_runtime_disable(&mdp5_kms->pdev->dev); drm_atomic_private_obj_fini(&mdp5_kms->glob_state); - drm_modeset_lock_fini(&mdp5_kms->glob_state_lock); } static int construct_pipes(struct mdp5_kms *mdp5_kms, int cnt, @@ -866,6 +818,9 @@ static int mdp5_dev_probe(struct platform_device *pdev) DBG(""); + if (!msm_disp_drv_should_bind(&pdev->dev, false)) + return -ENODEV; + mdp5_kms = devm_kzalloc(&pdev->dev, sizeof(*mdp5_kms), GFP_KERNEL); if (!mdp5_kms) return -ENOMEM; diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h index 29bf11f08601..fac9f05aa639 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.h @@ -40,7 +40,6 @@ struct mdp5_kms { * Global private object state, Do not access directly, use * mdp5_global_get_state() */ - struct drm_modeset_lock glob_state_lock; struct drm_private_obj glob_state; struct mdp5_smp *smp; @@ -291,8 +290,6 @@ struct drm_crtc *mdp5_crtc_init(struct drm_device *dev, struct drm_encoder *mdp5_encoder_init(struct drm_device *dev, struct mdp5_interface *intf, struct mdp5_ctl *ctl); -int mdp5_vid_encoder_set_split_display(struct drm_encoder *encoder, - struct drm_encoder *slave_encoder); void mdp5_encoder_set_intf_mode(struct drm_encoder *encoder, bool cmd_mode); int mdp5_encoder_get_linecount(struct drm_encoder *encoder); u32 mdp5_encoder_get_framecount(struct drm_encoder *encoder); @@ -303,8 +300,6 @@ void mdp5_cmd_encoder_mode_set(struct drm_encoder *encoder, struct drm_display_mode *adjusted_mode); void mdp5_cmd_encoder_disable(struct drm_encoder *encoder); void mdp5_cmd_encoder_enable(struct drm_encoder *encoder); -int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder, - struct drm_encoder *slave_encoder); #else static inline void mdp5_cmd_encoder_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, @@ -317,11 +312,6 @@ static inline void mdp5_cmd_encoder_disable(struct drm_encoder *encoder) static inline void mdp5_cmd_encoder_enable(struct drm_encoder *encoder) { } -static inline int mdp5_cmd_encoder_set_split_display( - struct drm_encoder *encoder, struct drm_encoder *slave_encoder) -{ - return -EINVAL; -} #endif #endif /* __MDP5_KMS_H__ */ diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c index 8b59562e29e2..b4bebb425d22 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.c @@ -325,22 +325,17 @@ void mdp5_smp_complete_commit(struct mdp5_smp *smp, struct mdp5_smp_state *state state->released = 0; } -void mdp5_smp_dump(struct mdp5_smp *smp, struct drm_printer *p) +void mdp5_smp_dump(struct mdp5_smp *smp, struct drm_printer *p, + struct mdp5_global_state *global_state) { struct mdp5_kms *mdp5_kms = get_kms(smp); struct mdp5_hw_pipe_state *hwpstate; struct mdp5_smp_state *state; - struct mdp5_global_state *global_state; int total = 0, i, j; drm_printf(p, "name\tinuse\tplane\n"); drm_printf(p, "----\t-----\t-----\n"); - if (drm_can_sleep()) - drm_modeset_lock(&mdp5_kms->glob_state_lock, NULL); - - global_state = mdp5_get_existing_global_state(mdp5_kms); - /* grab these *after* we hold the state_lock */ hwpstate = &global_state->hwpipe; state = &global_state->smp; @@ -365,9 +360,6 @@ void mdp5_smp_dump(struct mdp5_smp *smp, struct drm_printer *p) drm_printf(p, "TOTAL:\t%d\t(of %d)\n", total, smp->blk_cnt); drm_printf(p, "AVAIL:\t%d\n", smp->blk_cnt - bitmap_weight(state->state, smp->blk_cnt)); - - if (drm_can_sleep()) - drm_modeset_unlock(&mdp5_kms->glob_state_lock); } diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h b/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h index d8b6a11413d9..21732ed485be 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_smp.h @@ -69,7 +69,9 @@ struct mdp5_smp; struct mdp5_smp *mdp5_smp_init(struct mdp5_kms *mdp5_kms, const struct mdp5_smp_block *cfg); -void mdp5_smp_dump(struct mdp5_smp *smp, struct drm_printer *p); +struct mdp5_global_state; +void mdp5_smp_dump(struct mdp5_smp *smp, struct drm_printer *p, + struct mdp5_global_state *global_state); uint32_t mdp5_smp_calculate(struct mdp5_smp *smp, const struct mdp_format *format, diff --git a/drivers/gpu/drm/msm/dp/dp_audio.c b/drivers/gpu/drm/msm/dp/dp_audio.c index 4a2e479723a8..7634e4b74208 100644 --- a/drivers/gpu/drm/msm/dp/dp_audio.c +++ b/drivers/gpu/drm/msm/dp/dp_audio.c @@ -15,13 +15,7 @@ #include "dp_audio.h" #include "dp_panel.h" #include "dp_display.h" - -#define HEADER_BYTE_2_BIT 0 -#define PARITY_BYTE_2_BIT 8 -#define HEADER_BYTE_1_BIT 16 -#define PARITY_BYTE_1_BIT 24 -#define HEADER_BYTE_3_BIT 16 -#define PARITY_BYTE_3_BIT 24 +#include "dp_utils.h" struct dp_audio_private { struct platform_device *audio_pdev; @@ -36,71 +30,6 @@ struct dp_audio_private { struct dp_audio dp_audio; }; -static u8 dp_audio_get_g0_value(u8 data) -{ - u8 c[4]; - u8 g[4]; - u8 ret_data = 0; - u8 i; - - for (i = 0; i < 4; i++) - c[i] = (data >> i) & 0x01; - - g[0] = c[3]; - g[1] = c[0] ^ c[3]; - g[2] = c[1]; - g[3] = c[2]; - - for (i = 0; i < 4; i++) - ret_data = ((g[i] & 0x01) << i) | ret_data; - - return ret_data; -} - -static u8 dp_audio_get_g1_value(u8 data) -{ - u8 c[4]; - u8 g[4]; - u8 ret_data = 0; - u8 i; - - for (i = 0; i < 4; i++) - c[i] = (data >> i) & 0x01; - - g[0] = c[0] ^ c[3]; - g[1] = c[0] ^ c[1] ^ c[3]; - g[2] = c[1] ^ c[2]; - g[3] = c[2] ^ c[3]; - - for (i = 0; i < 4; i++) - ret_data = ((g[i] & 0x01) << i) | ret_data; - - return ret_data; -} - -static u8 dp_audio_calculate_parity(u32 data) -{ - u8 x0 = 0; - u8 x1 = 0; - u8 ci = 0; - u8 iData = 0; - u8 i = 0; - u8 parity_byte; - u8 num_byte = (data & 0xFF00) > 0 ? 8 : 2; - - for (i = 0; i < num_byte; i++) { - iData = (data >> i*4) & 0xF; - - ci = iData ^ x1; - x1 = x0 ^ dp_audio_get_g1_value(ci); - x0 = dp_audio_get_g0_value(ci); - } - - parity_byte = x1 | (x0 << 4); - - return parity_byte; -} - static u32 dp_audio_get_header(struct dp_catalog *catalog, enum dp_catalog_audio_sdp_type sdp, enum dp_catalog_audio_header_type header) @@ -134,7 +63,7 @@ static void dp_audio_stream_sdp(struct dp_audio_private *audio) DP_AUDIO_SDP_STREAM, DP_AUDIO_SDP_HEADER_1); new_value = 0x02; - parity_byte = dp_audio_calculate_parity(new_value); + parity_byte = dp_utils_calculate_parity(new_value); value |= ((new_value << HEADER_BYTE_1_BIT) | (parity_byte << PARITY_BYTE_1_BIT)); drm_dbg_dp(audio->drm_dev, @@ -147,7 +76,7 @@ static void dp_audio_stream_sdp(struct dp_audio_private *audio) value = dp_audio_get_header(catalog, DP_AUDIO_SDP_STREAM, DP_AUDIO_SDP_HEADER_2); new_value = value; - parity_byte = dp_audio_calculate_parity(new_value); + parity_byte = dp_utils_calculate_parity(new_value); value |= ((new_value << HEADER_BYTE_2_BIT) | (parity_byte << PARITY_BYTE_2_BIT)); drm_dbg_dp(audio->drm_dev, @@ -162,7 +91,7 @@ static void dp_audio_stream_sdp(struct dp_audio_private *audio) DP_AUDIO_SDP_STREAM, DP_AUDIO_SDP_HEADER_3); new_value = audio->channels - 1; - parity_byte = dp_audio_calculate_parity(new_value); + parity_byte = dp_utils_calculate_parity(new_value); value |= ((new_value << HEADER_BYTE_3_BIT) | (parity_byte << PARITY_BYTE_3_BIT)); drm_dbg_dp(audio->drm_dev, @@ -184,7 +113,7 @@ static void dp_audio_timestamp_sdp(struct dp_audio_private *audio) DP_AUDIO_SDP_TIMESTAMP, DP_AUDIO_SDP_HEADER_1); new_value = 0x1; - parity_byte = dp_audio_calculate_parity(new_value); + parity_byte = dp_utils_calculate_parity(new_value); value |= ((new_value << HEADER_BYTE_1_BIT) | (parity_byte << PARITY_BYTE_1_BIT)); drm_dbg_dp(audio->drm_dev, @@ -198,7 +127,7 @@ static void dp_audio_timestamp_sdp(struct dp_audio_private *audio) DP_AUDIO_SDP_TIMESTAMP, DP_AUDIO_SDP_HEADER_2); new_value = 0x17; - parity_byte = dp_audio_calculate_parity(new_value); + parity_byte = dp_utils_calculate_parity(new_value); value |= ((new_value << HEADER_BYTE_2_BIT) | (parity_byte << PARITY_BYTE_2_BIT)); drm_dbg_dp(audio->drm_dev, @@ -212,7 +141,7 @@ static void dp_audio_timestamp_sdp(struct dp_audio_private *audio) DP_AUDIO_SDP_TIMESTAMP, DP_AUDIO_SDP_HEADER_3); new_value = (0x0 | (0x11 << 2)); - parity_byte = dp_audio_calculate_parity(new_value); + parity_byte = dp_utils_calculate_parity(new_value); value |= ((new_value << HEADER_BYTE_3_BIT) | (parity_byte << PARITY_BYTE_3_BIT)); drm_dbg_dp(audio->drm_dev, @@ -233,7 +162,7 @@ static void dp_audio_infoframe_sdp(struct dp_audio_private *audio) DP_AUDIO_SDP_INFOFRAME, DP_AUDIO_SDP_HEADER_1); new_value = 0x84; - parity_byte = dp_audio_calculate_parity(new_value); + parity_byte = dp_utils_calculate_parity(new_value); value |= ((new_value << HEADER_BYTE_1_BIT) | (parity_byte << PARITY_BYTE_1_BIT)); drm_dbg_dp(audio->drm_dev, @@ -247,7 +176,7 @@ static void dp_audio_infoframe_sdp(struct dp_audio_private *audio) DP_AUDIO_SDP_INFOFRAME, DP_AUDIO_SDP_HEADER_2); new_value = 0x1b; - parity_byte = dp_audio_calculate_parity(new_value); + parity_byte = dp_utils_calculate_parity(new_value); value |= ((new_value << HEADER_BYTE_2_BIT) | (parity_byte << PARITY_BYTE_2_BIT)); drm_dbg_dp(audio->drm_dev, @@ -261,7 +190,7 @@ static void dp_audio_infoframe_sdp(struct dp_audio_private *audio) DP_AUDIO_SDP_INFOFRAME, DP_AUDIO_SDP_HEADER_3); new_value = (0x0 | (0x11 << 2)); - parity_byte = dp_audio_calculate_parity(new_value); + parity_byte = dp_utils_calculate_parity(new_value); value |= ((new_value << HEADER_BYTE_3_BIT) | (parity_byte << PARITY_BYTE_3_BIT)); drm_dbg_dp(audio->drm_dev, @@ -282,7 +211,7 @@ static void dp_audio_copy_management_sdp(struct dp_audio_private *audio) DP_AUDIO_SDP_COPYMANAGEMENT, DP_AUDIO_SDP_HEADER_1); new_value = 0x05; - parity_byte = dp_audio_calculate_parity(new_value); + parity_byte = dp_utils_calculate_parity(new_value); value |= ((new_value << HEADER_BYTE_1_BIT) | (parity_byte << PARITY_BYTE_1_BIT)); drm_dbg_dp(audio->drm_dev, @@ -296,7 +225,7 @@ static void dp_audio_copy_management_sdp(struct dp_audio_private *audio) DP_AUDIO_SDP_COPYMANAGEMENT, DP_AUDIO_SDP_HEADER_2); new_value = 0x0F; - parity_byte = dp_audio_calculate_parity(new_value); + parity_byte = dp_utils_calculate_parity(new_value); value |= ((new_value << HEADER_BYTE_2_BIT) | (parity_byte << PARITY_BYTE_2_BIT)); drm_dbg_dp(audio->drm_dev, @@ -310,7 +239,7 @@ static void dp_audio_copy_management_sdp(struct dp_audio_private *audio) DP_AUDIO_SDP_COPYMANAGEMENT, DP_AUDIO_SDP_HEADER_3); new_value = 0x0; - parity_byte = dp_audio_calculate_parity(new_value); + parity_byte = dp_utils_calculate_parity(new_value); value |= ((new_value << HEADER_BYTE_3_BIT) | (parity_byte << PARITY_BYTE_3_BIT)); drm_dbg_dp(audio->drm_dev, @@ -331,7 +260,7 @@ static void dp_audio_isrc_sdp(struct dp_audio_private *audio) DP_AUDIO_SDP_ISRC, DP_AUDIO_SDP_HEADER_1); new_value = 0x06; - parity_byte = dp_audio_calculate_parity(new_value); + parity_byte = dp_utils_calculate_parity(new_value); value |= ((new_value << HEADER_BYTE_1_BIT) | (parity_byte << PARITY_BYTE_1_BIT)); drm_dbg_dp(audio->drm_dev, @@ -345,7 +274,7 @@ static void dp_audio_isrc_sdp(struct dp_audio_private *audio) DP_AUDIO_SDP_ISRC, DP_AUDIO_SDP_HEADER_2); new_value = 0x0F; - parity_byte = dp_audio_calculate_parity(new_value); + parity_byte = dp_utils_calculate_parity(new_value); value |= ((new_value << HEADER_BYTE_2_BIT) | (parity_byte << PARITY_BYTE_2_BIT)); drm_dbg_dp(audio->drm_dev, diff --git a/drivers/gpu/drm/msm/dp/dp_aux.c b/drivers/gpu/drm/msm/dp/dp_aux.c index 03f4951c49f4..adbd5a367395 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.c +++ b/drivers/gpu/drm/msm/dp/dp_aux.c @@ -4,6 +4,7 @@ */ #include <linux/delay.h> +#include <linux/phy/phy.h> #include <drm/drm_print.h> #include "dp_reg.h" @@ -23,6 +24,8 @@ struct dp_aux_private { struct device *dev; struct dp_catalog *catalog; + struct phy *phy; + struct mutex mutex; struct completion comp; @@ -336,7 +339,7 @@ static ssize_t dp_aux_transfer(struct drm_dp_aux *dp_aux, if (aux->native) { aux->retry_cnt++; if (!(aux->retry_cnt % MAX_AUX_RETRIES)) - dp_catalog_aux_update_cfg(aux->catalog); + phy_calibrate(aux->phy); } /* reset aux if link is in connected state */ if (dp_catalog_link_is_connected(aux->catalog)) @@ -439,7 +442,7 @@ void dp_aux_reconfig(struct drm_dp_aux *dp_aux) aux = container_of(dp_aux, struct dp_aux_private, dp_aux); - dp_catalog_aux_update_cfg(aux->catalog); + phy_calibrate(aux->phy); dp_catalog_aux_reset(aux->catalog); } @@ -517,6 +520,7 @@ static int dp_wait_hpd_asserted(struct drm_dp_aux *dp_aux, } struct drm_dp_aux *dp_aux_get(struct device *dev, struct dp_catalog *catalog, + struct phy *phy, bool is_edp) { struct dp_aux_private *aux; @@ -537,6 +541,7 @@ struct drm_dp_aux *dp_aux_get(struct device *dev, struct dp_catalog *catalog, aux->dev = dev; aux->catalog = catalog; + aux->phy = phy; aux->retry_cnt = 0; /* diff --git a/drivers/gpu/drm/msm/dp/dp_aux.h b/drivers/gpu/drm/msm/dp/dp_aux.h index 511305da4f66..f47d591c1f54 100644 --- a/drivers/gpu/drm/msm/dp/dp_aux.h +++ b/drivers/gpu/drm/msm/dp/dp_aux.h @@ -16,7 +16,9 @@ void dp_aux_init(struct drm_dp_aux *dp_aux); void dp_aux_deinit(struct drm_dp_aux *dp_aux); void dp_aux_reconfig(struct drm_dp_aux *dp_aux); +struct phy; struct drm_dp_aux *dp_aux_get(struct device *dev, struct dp_catalog *catalog, + struct phy *phy, bool is_edp); void dp_aux_put(struct drm_dp_aux *aux); diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.c b/drivers/gpu/drm/msm/dp/dp_catalog.c index 5142aeb705a4..3e7c84cdef47 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.c +++ b/drivers/gpu/drm/msm/dp/dp_catalog.c @@ -7,8 +7,7 @@ #include <linux/delay.h> #include <linux/iopoll.h> -#include <linux/phy/phy.h> -#include <linux/phy/phy-dp.h> +#include <linux/platform_device.h> #include <linux/rational.h> #include <drm/display/drm_dp_helper.h> #include <drm/drm_print.h> @@ -55,10 +54,31 @@ (PSR_UPDATE_MASK | PSR_CAPTURE_MASK | PSR_EXIT_MASK | \ PSR_UPDATE_ERROR_MASK | PSR_WAKE_ERROR_MASK) +#define DP_DEFAULT_AHB_OFFSET 0x0000 +#define DP_DEFAULT_AHB_SIZE 0x0200 +#define DP_DEFAULT_AUX_OFFSET 0x0200 +#define DP_DEFAULT_AUX_SIZE 0x0200 +#define DP_DEFAULT_LINK_OFFSET 0x0400 +#define DP_DEFAULT_LINK_SIZE 0x0C00 +#define DP_DEFAULT_P0_OFFSET 0x1000 +#define DP_DEFAULT_P0_SIZE 0x0400 + +struct dss_io_region { + size_t len; + void __iomem *base; +}; + +struct dss_io_data { + struct dss_io_region ahb; + struct dss_io_region aux; + struct dss_io_region link; + struct dss_io_region p0; +}; + struct dp_catalog_private { struct device *dev; struct drm_device *drm_dev; - struct dp_io *io; + struct dss_io_data io; u32 (*audio_map)[DP_AUDIO_SDP_HEADER_MAX]; struct dp_catalog dp_catalog; u8 aux_lut_cfg_index[PHY_AUX_CFG_MAX]; @@ -68,7 +88,7 @@ void dp_catalog_snapshot(struct dp_catalog *dp_catalog, struct msm_disp_state *d { struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); - struct dss_io_data *dss = &catalog->io->dp_controller; + struct dss_io_data *dss = &catalog->io; msm_disp_snapshot_add_block(disp_state, dss->ahb.len, dss->ahb.base, "dp_ahb"); msm_disp_snapshot_add_block(disp_state, dss->aux.len, dss->aux.base, "dp_aux"); @@ -78,7 +98,7 @@ void dp_catalog_snapshot(struct dp_catalog *dp_catalog, struct msm_disp_state *d static inline u32 dp_read_aux(struct dp_catalog_private *catalog, u32 offset) { - return readl_relaxed(catalog->io->dp_controller.aux.base + offset); + return readl_relaxed(catalog->io.aux.base + offset); } static inline void dp_write_aux(struct dp_catalog_private *catalog, @@ -88,12 +108,12 @@ static inline void dp_write_aux(struct dp_catalog_private *catalog, * To make sure aux reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io->dp_controller.aux.base + offset); + writel(data, catalog->io.aux.base + offset); } static inline u32 dp_read_ahb(const struct dp_catalog_private *catalog, u32 offset) { - return readl_relaxed(catalog->io->dp_controller.ahb.base + offset); + return readl_relaxed(catalog->io.ahb.base + offset); } static inline void dp_write_ahb(struct dp_catalog_private *catalog, @@ -103,7 +123,7 @@ static inline void dp_write_ahb(struct dp_catalog_private *catalog, * To make sure phy reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io->dp_controller.ahb.base + offset); + writel(data, catalog->io.ahb.base + offset); } static inline void dp_write_p0(struct dp_catalog_private *catalog, @@ -113,7 +133,7 @@ static inline void dp_write_p0(struct dp_catalog_private *catalog, * To make sure interface reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io->dp_controller.p0.base + offset); + writel(data, catalog->io.p0.base + offset); } static inline u32 dp_read_p0(struct dp_catalog_private *catalog, @@ -123,12 +143,12 @@ static inline u32 dp_read_p0(struct dp_catalog_private *catalog, * To make sure interface reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - return readl_relaxed(catalog->io->dp_controller.p0.base + offset); + return readl_relaxed(catalog->io.p0.base + offset); } static inline u32 dp_read_link(struct dp_catalog_private *catalog, u32 offset) { - return readl_relaxed(catalog->io->dp_controller.link.base + offset); + return readl_relaxed(catalog->io.link.base + offset); } static inline void dp_write_link(struct dp_catalog_private *catalog, @@ -138,7 +158,7 @@ static inline void dp_write_link(struct dp_catalog_private *catalog, * To make sure link reg writes happens before any other operation, * this function uses writel() instread of writel_relaxed() */ - writel(data, catalog->io->dp_controller.link.base + offset); + writel(data, catalog->io.link.base + offset); } /* aux related catalog functions */ @@ -243,16 +263,6 @@ void dp_catalog_aux_enable(struct dp_catalog *dp_catalog, bool enable) dp_write_aux(catalog, REG_DP_AUX_CTRL, aux_ctrl); } -void dp_catalog_aux_update_cfg(struct dp_catalog *dp_catalog) -{ - struct dp_catalog_private *catalog = container_of(dp_catalog, - struct dp_catalog_private, dp_catalog); - struct dp_io *dp_io = catalog->io; - struct phy *phy = dp_io->phy; - - phy_calibrate(phy); -} - int dp_catalog_aux_wait_for_hpd_connect_state(struct dp_catalog *dp_catalog) { u32 state; @@ -260,7 +270,7 @@ int dp_catalog_aux_wait_for_hpd_connect_state(struct dp_catalog *dp_catalog) struct dp_catalog_private, dp_catalog); /* poll for hpd connected status every 2ms and timeout after 500ms */ - return readl_poll_timeout(catalog->io->dp_controller.aux.base + + return readl_poll_timeout(catalog->io.aux.base + REG_DP_DP_HPD_INT_STATUS, state, state & DP_DP_HPD_STATE_STATUS_CONNECTED, 2000, 500000); @@ -288,7 +298,7 @@ void dp_catalog_dump_regs(struct dp_catalog *dp_catalog) { struct dp_catalog_private *catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); - struct dss_io_data *io = &catalog->io->dp_controller; + struct dss_io_data *io = &catalog->io; pr_info("AHB regs\n"); dump_regs(io->ahb.base, io->ahb.len); @@ -440,9 +450,26 @@ void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, dp_write_link(catalog, REG_DP_MISC1_MISC0, misc_val); } +void dp_catalog_setup_peripheral_flush(struct dp_catalog *dp_catalog) +{ + u32 mainlink_ctrl, hw_revision; + struct dp_catalog_private *catalog = container_of(dp_catalog, + struct dp_catalog_private, dp_catalog); + + mainlink_ctrl = dp_read_link(catalog, REG_DP_MAINLINK_CTRL); + + hw_revision = dp_catalog_hw_revision(dp_catalog); + if (hw_revision >= DP_HW_VERSION_1_2) + mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE; + else + mainlink_ctrl |= DP_MAINLINK_FLUSH_MODE_UPDATE_SDP; + + dp_write_link(catalog, REG_DP_MAINLINK_CTRL, mainlink_ctrl); +} + void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate, u32 stream_rate_khz, - bool fixed_nvid) + bool fixed_nvid, bool is_ycbcr_420) { u32 pixel_m, pixel_n; u32 mvid, nvid, pixel_div = 0, dispcc_input_rate; @@ -485,6 +512,9 @@ void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, nvid = temp; } + if (is_ycbcr_420) + mvid /= 2; + if (link_rate_hbr2 == rate) nvid *= 2; @@ -512,7 +542,7 @@ int dp_catalog_ctrl_set_pattern_state_bit(struct dp_catalog *dp_catalog, bit = BIT(state_bit - 1) << DP_MAINLINK_READY_LINK_TRAINING_SHIFT; /* Poll for mainlink ready status */ - ret = readx_poll_timeout(readl, catalog->io->dp_controller.link.base + + ret = readx_poll_timeout(readl, catalog->io.link.base + REG_DP_MAINLINK_READY, data, data & bit, POLLING_SLEEP_US, POLLING_TIMEOUT_US); @@ -575,7 +605,7 @@ bool dp_catalog_ctrl_mainlink_ready(struct dp_catalog *dp_catalog) struct dp_catalog_private, dp_catalog); /* Poll for mainlink ready status */ - ret = readl_poll_timeout(catalog->io->dp_controller.link.base + + ret = readl_poll_timeout(catalog->io.link.base + REG_DP_MAINLINK_READY, data, data & DP_MAINLINK_READY_FOR_VIDEO, POLLING_SLEEP_US, POLLING_TIMEOUT_US); @@ -765,25 +795,6 @@ void dp_catalog_ctrl_phy_reset(struct dp_catalog *dp_catalog) dp_write_ahb(catalog, REG_DP_PHY_CTRL, 0x0); } -int dp_catalog_ctrl_update_vx_px(struct dp_catalog *dp_catalog, - u8 v_level, u8 p_level) -{ - struct dp_catalog_private *catalog = container_of(dp_catalog, - struct dp_catalog_private, dp_catalog); - struct dp_io *dp_io = catalog->io; - struct phy *phy = dp_io->phy; - struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp; - - /* TODO: Update for all lanes instead of just first one */ - opts_dp->voltage[0] = v_level; - opts_dp->pre[0] = p_level; - opts_dp->set_voltages = 1; - phy_configure(phy, &dp_io->phy_opts); - opts_dp->set_voltages = 0; - - return 0; -} - void dp_catalog_ctrl_send_phy_pattern(struct dp_catalog *dp_catalog, u32 pattern) { @@ -898,6 +909,99 @@ int dp_catalog_panel_timing_cfg(struct dp_catalog *dp_catalog) return 0; } +static void dp_catalog_panel_send_vsc_sdp(struct dp_catalog *dp_catalog, struct dp_sdp *vsc_sdp) +{ + struct dp_catalog_private *catalog; + u32 header[2]; + u32 val; + int i; + + catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); + + dp_utils_pack_sdp_header(&vsc_sdp->sdp_header, header); + + dp_write_link(catalog, MMSS_DP_GENERIC0_0, header[0]); + dp_write_link(catalog, MMSS_DP_GENERIC0_1, header[1]); + + for (i = 0; i < sizeof(vsc_sdp->db); i += 4) { + val = ((vsc_sdp->db[i]) | (vsc_sdp->db[i + 1] << 8) | (vsc_sdp->db[i + 2] << 16) | + (vsc_sdp->db[i + 3] << 24)); + dp_write_link(catalog, MMSS_DP_GENERIC0_2 + i, val); + } +} + +static void dp_catalog_panel_update_sdp(struct dp_catalog *dp_catalog) +{ + struct dp_catalog_private *catalog; + u32 hw_revision; + + catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); + + hw_revision = dp_catalog_hw_revision(dp_catalog); + if (hw_revision < DP_HW_VERSION_1_2 && hw_revision >= DP_HW_VERSION_1_0) { + dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x01); + dp_write_link(catalog, MMSS_DP_SDP_CFG3, 0x00); + } +} + +void dp_catalog_panel_enable_vsc_sdp(struct dp_catalog *dp_catalog, struct dp_sdp *vsc_sdp) +{ + struct dp_catalog_private *catalog; + u32 cfg, cfg2, misc; + + catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); + + cfg = dp_read_link(catalog, MMSS_DP_SDP_CFG); + cfg2 = dp_read_link(catalog, MMSS_DP_SDP_CFG2); + misc = dp_read_link(catalog, REG_DP_MISC1_MISC0); + + cfg |= GEN0_SDP_EN; + dp_write_link(catalog, MMSS_DP_SDP_CFG, cfg); + + cfg2 |= GENERIC0_SDPSIZE_VALID; + dp_write_link(catalog, MMSS_DP_SDP_CFG2, cfg2); + + dp_catalog_panel_send_vsc_sdp(dp_catalog, vsc_sdp); + + /* indicates presence of VSC (BIT(6) of MISC1) */ + misc |= DP_MISC1_VSC_SDP; + + drm_dbg_dp(catalog->drm_dev, "vsc sdp enable=1\n"); + + pr_debug("misc settings = 0x%x\n", misc); + dp_write_link(catalog, REG_DP_MISC1_MISC0, misc); + + dp_catalog_panel_update_sdp(dp_catalog); +} + +void dp_catalog_panel_disable_vsc_sdp(struct dp_catalog *dp_catalog) +{ + struct dp_catalog_private *catalog; + u32 cfg, cfg2, misc; + + catalog = container_of(dp_catalog, struct dp_catalog_private, dp_catalog); + + cfg = dp_read_link(catalog, MMSS_DP_SDP_CFG); + cfg2 = dp_read_link(catalog, MMSS_DP_SDP_CFG2); + misc = dp_read_link(catalog, REG_DP_MISC1_MISC0); + + cfg &= ~GEN0_SDP_EN; + dp_write_link(catalog, MMSS_DP_SDP_CFG, cfg); + + cfg2 &= ~GENERIC0_SDPSIZE_VALID; + dp_write_link(catalog, MMSS_DP_SDP_CFG2, cfg2); + + /* switch back to MSA */ + misc &= ~DP_MISC1_VSC_SDP; + + drm_dbg_dp(catalog->drm_dev, "vsc sdp enable=0\n"); + + pr_debug("misc settings = 0x%x\n", misc); + dp_write_link(catalog, REG_DP_MISC1_MISC0, misc); + + dp_catalog_panel_update_sdp(dp_catalog); +} + void dp_catalog_panel_tpg_enable(struct dp_catalog *dp_catalog, struct drm_display_mode *drm_mode) { @@ -976,21 +1080,84 @@ void dp_catalog_panel_tpg_disable(struct dp_catalog *dp_catalog) dp_write_p0(catalog, MMSS_DP_TIMING_ENGINE_EN, 0x0); } -struct dp_catalog *dp_catalog_get(struct device *dev, struct dp_io *io) +static void __iomem *dp_ioremap(struct platform_device *pdev, int idx, size_t *len) { - struct dp_catalog_private *catalog; + struct resource *res; + void __iomem *base; + + base = devm_platform_get_and_ioremap_resource(pdev, idx, &res); + if (!IS_ERR(base)) + *len = resource_size(res); + + return base; +} + +static int dp_catalog_get_io(struct dp_catalog_private *catalog) +{ + struct platform_device *pdev = to_platform_device(catalog->dev); + struct dss_io_data *dss = &catalog->io; + + dss->ahb.base = dp_ioremap(pdev, 0, &dss->ahb.len); + if (IS_ERR(dss->ahb.base)) + return PTR_ERR(dss->ahb.base); - if (!io) { - DRM_ERROR("invalid input\n"); - return ERR_PTR(-EINVAL); + dss->aux.base = dp_ioremap(pdev, 1, &dss->aux.len); + if (IS_ERR(dss->aux.base)) { + /* + * The initial binding had a single reg, but in order to + * support variation in the sub-region sizes this was split. + * dp_ioremap() will fail with -EINVAL here if only a single + * reg is specified, so fill in the sub-region offsets and + * lengths based on this single region. + */ + if (PTR_ERR(dss->aux.base) == -EINVAL) { + if (dss->ahb.len < DP_DEFAULT_P0_OFFSET + DP_DEFAULT_P0_SIZE) { + DRM_ERROR("legacy memory region not large enough\n"); + return -EINVAL; + } + + dss->ahb.len = DP_DEFAULT_AHB_SIZE; + dss->aux.base = dss->ahb.base + DP_DEFAULT_AUX_OFFSET; + dss->aux.len = DP_DEFAULT_AUX_SIZE; + dss->link.base = dss->ahb.base + DP_DEFAULT_LINK_OFFSET; + dss->link.len = DP_DEFAULT_LINK_SIZE; + dss->p0.base = dss->ahb.base + DP_DEFAULT_P0_OFFSET; + dss->p0.len = DP_DEFAULT_P0_SIZE; + } else { + DRM_ERROR("unable to remap aux region: %pe\n", dss->aux.base); + return PTR_ERR(dss->aux.base); + } + } else { + dss->link.base = dp_ioremap(pdev, 2, &dss->link.len); + if (IS_ERR(dss->link.base)) { + DRM_ERROR("unable to remap link region: %pe\n", dss->link.base); + return PTR_ERR(dss->link.base); + } + + dss->p0.base = dp_ioremap(pdev, 3, &dss->p0.len); + if (IS_ERR(dss->p0.base)) { + DRM_ERROR("unable to remap p0 region: %pe\n", dss->p0.base); + return PTR_ERR(dss->p0.base); + } } + return 0; +} + +struct dp_catalog *dp_catalog_get(struct device *dev) +{ + struct dp_catalog_private *catalog; + int ret; + catalog = devm_kzalloc(dev, sizeof(*catalog), GFP_KERNEL); if (!catalog) return ERR_PTR(-ENOMEM); catalog->dev = dev; - catalog->io = io; + + ret = dp_catalog_get_io(catalog); + if (ret) + return ERR_PTR(ret); return &catalog->dp_catalog; } diff --git a/drivers/gpu/drm/msm/dp/dp_catalog.h b/drivers/gpu/drm/msm/dp/dp_catalog.h index 38786e855b51..75ec290127c7 100644 --- a/drivers/gpu/drm/msm/dp/dp_catalog.h +++ b/drivers/gpu/drm/msm/dp/dp_catalog.h @@ -8,7 +8,7 @@ #include <drm/drm_modes.h> -#include "dp_parser.h" +#include "dp_utils.h" #include "disp/msm_disp_snapshot.h" /* interrupts */ @@ -30,6 +30,9 @@ #define DP_AUX_CFG_MAX_VALUE_CNT 3 +#define DP_HW_VERSION_1_0 0x10000000 +#define DP_HW_VERSION_1_2 0x10020000 + /* PHY AUX config registers */ enum dp_phy_aux_config_type { PHY_AUX_CFG0, @@ -84,7 +87,6 @@ int dp_catalog_aux_clear_trans(struct dp_catalog *dp_catalog, bool read); int dp_catalog_aux_clear_hw_interrupts(struct dp_catalog *dp_catalog); void dp_catalog_aux_reset(struct dp_catalog *dp_catalog); void dp_catalog_aux_enable(struct dp_catalog *dp_catalog, bool enable); -void dp_catalog_aux_update_cfg(struct dp_catalog *dp_catalog); int dp_catalog_aux_wait_for_hpd_connect_state(struct dp_catalog *dp_catalog); u32 dp_catalog_aux_get_irq(struct dp_catalog *dp_catalog); @@ -94,9 +96,10 @@ void dp_catalog_ctrl_config_ctrl(struct dp_catalog *dp_catalog, u32 config); void dp_catalog_ctrl_lane_mapping(struct dp_catalog *dp_catalog); void dp_catalog_ctrl_mainlink_ctrl(struct dp_catalog *dp_catalog, bool enable); void dp_catalog_ctrl_psr_mainlink_enable(struct dp_catalog *dp_catalog, bool enable); +void dp_catalog_setup_peripheral_flush(struct dp_catalog *dp_catalog); void dp_catalog_ctrl_config_misc(struct dp_catalog *dp_catalog, u32 cc, u32 tb); void dp_catalog_ctrl_config_msa(struct dp_catalog *dp_catalog, u32 rate, - u32 stream_rate_khz, bool fixed_nvid); + u32 stream_rate_khz, bool fixed_nvid, bool is_ycbcr_420); int dp_catalog_ctrl_set_pattern_state_bit(struct dp_catalog *dp_catalog, u32 pattern); u32 dp_catalog_hw_revision(const struct dp_catalog *dp_catalog); void dp_catalog_ctrl_reset(struct dp_catalog *dp_catalog); @@ -111,8 +114,6 @@ void dp_catalog_ctrl_set_psr(struct dp_catalog *dp_catalog, bool enter); u32 dp_catalog_link_is_connected(struct dp_catalog *dp_catalog); u32 dp_catalog_hpd_get_intr_status(struct dp_catalog *dp_catalog); void dp_catalog_ctrl_phy_reset(struct dp_catalog *dp_catalog); -int dp_catalog_ctrl_update_vx_px(struct dp_catalog *dp_catalog, u8 v_level, - u8 p_level); int dp_catalog_ctrl_get_interrupt(struct dp_catalog *dp_catalog); u32 dp_catalog_ctrl_read_psr_interrupt_status(struct dp_catalog *dp_catalog); void dp_catalog_ctrl_update_transfer_unit(struct dp_catalog *dp_catalog, @@ -124,12 +125,14 @@ u32 dp_catalog_ctrl_read_phy_pattern(struct dp_catalog *dp_catalog); /* DP Panel APIs */ int dp_catalog_panel_timing_cfg(struct dp_catalog *dp_catalog); +void dp_catalog_panel_enable_vsc_sdp(struct dp_catalog *dp_catalog, struct dp_sdp *vsc_sdp); +void dp_catalog_panel_disable_vsc_sdp(struct dp_catalog *dp_catalog); void dp_catalog_dump_regs(struct dp_catalog *dp_catalog); void dp_catalog_panel_tpg_enable(struct dp_catalog *dp_catalog, struct drm_display_mode *drm_mode); void dp_catalog_panel_tpg_disable(struct dp_catalog *dp_catalog); -struct dp_catalog *dp_catalog_get(struct device *dev, struct dp_io *io); +struct dp_catalog *dp_catalog_get(struct device *dev); /* DP Audio APIs */ void dp_catalog_audio_get_header(struct dp_catalog *catalog); diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.c b/drivers/gpu/drm/msm/dp/dp_ctrl.c index fb588fde298a..c4dda1faef67 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.c +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.c @@ -76,13 +76,27 @@ struct dp_ctrl_private { struct drm_dp_aux *aux; struct dp_panel *panel; struct dp_link *link; - struct dp_power *power; - struct dp_parser *parser; struct dp_catalog *catalog; + struct phy *phy; + + unsigned int num_core_clks; + struct clk_bulk_data *core_clks; + + unsigned int num_link_clks; + struct clk_bulk_data *link_clks; + + struct clk *pixel_clk; + + union phy_configure_opts phy_opts; + struct completion idle_comp; struct completion psr_op_comp; struct completion video_comp; + + bool core_clks_on; + bool link_clks_on; + bool stream_clks_on; }; static int dp_aux_link_configure(struct drm_dp_aux *aux, @@ -128,6 +142,9 @@ static void dp_ctrl_config_ctrl(struct dp_ctrl_private *ctrl) /* Default-> LSCLK DIV: 1/4 LCLK */ config |= (2 << DP_CONFIGURATION_CTRL_LSCLK_DIV_SHIFT); + if (ctrl->panel->dp_mode.out_fmt_is_yuv_420) + config |= DP_CONFIGURATION_CTRL_RGB_YUV; /* YUV420 */ + /* Scrambler reset enable */ if (drm_dp_alternate_scrambler_reset_cap(dpcd)) config |= DP_CONFIGURATION_CTRL_ASSR; @@ -162,6 +179,7 @@ static void dp_ctrl_configure_source_params(struct dp_ctrl_private *ctrl) dp_catalog_ctrl_lane_mapping(ctrl->catalog); dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, true); + dp_catalog_setup_peripheral_flush(ctrl->catalog); dp_ctrl_config_ctrl(ctrl); @@ -952,7 +970,7 @@ static void dp_ctrl_calc_tu_parameters(struct dp_ctrl_private *ctrl, in.hporch = drm_mode->htotal - drm_mode->hdisplay; in.nlanes = ctrl->link->link_params.num_lanes; in.bpp = ctrl->panel->dp_mode.bpp; - in.pixel_enc = 444; + in.pixel_enc = ctrl->panel->dp_mode.out_fmt_is_yuv_420 ? 420 : 444; in.dsc_en = 0; in.async_en = 0; in.fec_en = 0; @@ -1001,6 +1019,21 @@ static int dp_ctrl_wait4video_ready(struct dp_ctrl_private *ctrl) return ret; } +static int dp_ctrl_set_vx_px(struct dp_ctrl_private *ctrl, + u8 v_level, u8 p_level) +{ + union phy_configure_opts *phy_opts = &ctrl->phy_opts; + + /* TODO: Update for all lanes instead of just first one */ + phy_opts->dp.voltage[0] = v_level; + phy_opts->dp.pre[0] = p_level; + phy_opts->dp.set_voltages = 1; + phy_configure(ctrl->phy, phy_opts); + phy_opts->dp.set_voltages = 0; + + return 0; +} + static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl) { struct dp_link *link = ctrl->link; @@ -1013,7 +1046,7 @@ static int dp_ctrl_update_vx_px(struct dp_ctrl_private *ctrl) drm_dbg_dp(ctrl->drm_dev, "voltage level: %d emphasis level: %d\n", voltage_swing_level, pre_emphasis_level); - ret = dp_catalog_ctrl_update_vx_px(ctrl->catalog, + ret = dp_ctrl_set_vx_px(ctrl, voltage_swing_level, pre_emphasis_level); if (ret) @@ -1312,44 +1345,115 @@ static int dp_ctrl_setup_main_link(struct dp_ctrl_private *ctrl, return ret; } -static void dp_ctrl_set_clock_rate(struct dp_ctrl_private *ctrl, - enum dp_pm_type module, char *name, unsigned long rate) +int dp_ctrl_core_clk_enable(struct dp_ctrl *dp_ctrl) { - u32 num = ctrl->parser->mp[module].num_clk; - struct clk_bulk_data *cfg = ctrl->parser->mp[module].clocks; + struct dp_ctrl_private *ctrl; + int ret = 0; + + ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); - while (num && strcmp(cfg->id, name)) { - num--; - cfg++; + if (ctrl->core_clks_on) { + drm_dbg_dp(ctrl->drm_dev, "core clks already enabled\n"); + return 0; } - drm_dbg_dp(ctrl->drm_dev, "setting rate=%lu on clk=%s\n", - rate, name); + ret = clk_bulk_prepare_enable(ctrl->num_core_clks, ctrl->core_clks); + if (ret) + return ret; - if (num) - clk_set_rate(cfg->clk, rate); - else - DRM_ERROR("%s clock doesn't exit to set rate %lu\n", - name, rate); + ctrl->core_clks_on = true; + + drm_dbg_dp(ctrl->drm_dev, "enable core clocks \n"); + drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", + ctrl->stream_clks_on ? "on" : "off", + ctrl->link_clks_on ? "on" : "off", + ctrl->core_clks_on ? "on" : "off"); + + return 0; +} + +void dp_ctrl_core_clk_disable(struct dp_ctrl *dp_ctrl) +{ + struct dp_ctrl_private *ctrl; + + ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); + + clk_bulk_disable_unprepare(ctrl->num_core_clks, ctrl->core_clks); + + ctrl->core_clks_on = false; + + drm_dbg_dp(ctrl->drm_dev, "disable core clocks \n"); + drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", + ctrl->stream_clks_on ? "on" : "off", + ctrl->link_clks_on ? "on" : "off", + ctrl->core_clks_on ? "on" : "off"); +} + +static int dp_ctrl_link_clk_enable(struct dp_ctrl *dp_ctrl) +{ + struct dp_ctrl_private *ctrl; + int ret = 0; + + ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); + + if (ctrl->link_clks_on) { + drm_dbg_dp(ctrl->drm_dev, "links clks already enabled\n"); + return 0; + } + + if (!ctrl->core_clks_on) { + drm_dbg_dp(ctrl->drm_dev, "Enable core clks before link clks\n"); + + dp_ctrl_core_clk_enable(dp_ctrl); + } + + ret = clk_bulk_prepare_enable(ctrl->num_link_clks, ctrl->link_clks); + if (ret) + return ret; + + ctrl->link_clks_on = true; + + drm_dbg_dp(ctrl->drm_dev, "enable link clocks\n"); + drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", + ctrl->stream_clks_on ? "on" : "off", + ctrl->link_clks_on ? "on" : "off", + ctrl->core_clks_on ? "on" : "off"); + + return 0; +} + +static void dp_ctrl_link_clk_disable(struct dp_ctrl *dp_ctrl) +{ + struct dp_ctrl_private *ctrl; + + ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); + + clk_bulk_disable_unprepare(ctrl->num_link_clks, ctrl->link_clks); + + ctrl->link_clks_on = false; + + drm_dbg_dp(ctrl->drm_dev, "disabled link clocks\n"); + drm_dbg_dp(ctrl->drm_dev, "stream_clks:%s link_clks:%s core_clks:%s\n", + ctrl->stream_clks_on ? "on" : "off", + ctrl->link_clks_on ? "on" : "off", + ctrl->core_clks_on ? "on" : "off"); } static int dp_ctrl_enable_mainlink_clocks(struct dp_ctrl_private *ctrl) { int ret = 0; - struct dp_io *dp_io = &ctrl->parser->io; - struct phy *phy = dp_io->phy; - struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp; + struct phy *phy = ctrl->phy; const u8 *dpcd = ctrl->panel->dpcd; - opts_dp->lanes = ctrl->link->link_params.num_lanes; - opts_dp->link_rate = ctrl->link->link_params.rate / 100; - opts_dp->ssc = drm_dp_max_downspread(dpcd); + ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes; + ctrl->phy_opts.dp.link_rate = ctrl->link->link_params.rate / 100; + ctrl->phy_opts.dp.ssc = drm_dp_max_downspread(dpcd); - phy_configure(phy, &dp_io->phy_opts); + phy_configure(phy, &ctrl->phy_opts); phy_power_on(phy); dev_pm_opp_set_rate(ctrl->dev, ctrl->link->link_params.rate * 1000); - ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, true); + ret = dp_ctrl_link_clk_enable(&ctrl->dp_ctrl); if (ret) DRM_ERROR("Unable to start link clocks. ret=%d\n", ret); @@ -1436,12 +1540,10 @@ void dp_ctrl_set_psr(struct dp_ctrl *dp_ctrl, bool enter) void dp_ctrl_phy_init(struct dp_ctrl *dp_ctrl) { struct dp_ctrl_private *ctrl; - struct dp_io *dp_io; struct phy *phy; ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); - dp_io = &ctrl->parser->io; - phy = dp_io->phy; + phy = ctrl->phy; dp_catalog_ctrl_phy_reset(ctrl->catalog); phy_init(phy); @@ -1453,12 +1555,10 @@ void dp_ctrl_phy_init(struct dp_ctrl *dp_ctrl) void dp_ctrl_phy_exit(struct dp_ctrl *dp_ctrl) { struct dp_ctrl_private *ctrl; - struct dp_io *dp_io; struct phy *phy; ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); - dp_io = &ctrl->parser->io; - phy = dp_io->phy; + phy = ctrl->phy; dp_catalog_ctrl_phy_reset(ctrl->catalog); phy_exit(phy); @@ -1483,25 +1583,21 @@ static bool dp_ctrl_use_fixed_nvid(struct dp_ctrl_private *ctrl) static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl) { + struct phy *phy = ctrl->phy; int ret = 0; - struct dp_io *dp_io = &ctrl->parser->io; - struct phy *phy = dp_io->phy; - struct phy_configure_opts_dp *opts_dp = &dp_io->phy_opts.dp; dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); - opts_dp->lanes = ctrl->link->link_params.num_lanes; - phy_configure(phy, &dp_io->phy_opts); + ctrl->phy_opts.dp.lanes = ctrl->link->link_params.num_lanes; + phy_configure(phy, &ctrl->phy_opts); /* * Disable and re-enable the mainlink clock since the * link clock might have been adjusted as part of the * link maintenance. */ dev_pm_opp_set_rate(ctrl->dev, 0); - ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); - if (ret) { - DRM_ERROR("Failed to disable clocks. ret=%d\n", ret); - return ret; - } + + dp_ctrl_link_clk_disable(&ctrl->dp_ctrl); + phy_power_off(phy); /* hw recommended delay before re-enabling clocks */ msleep(20); @@ -1517,22 +1613,16 @@ static int dp_ctrl_reinitialize_mainlink(struct dp_ctrl_private *ctrl) static int dp_ctrl_deinitialize_mainlink(struct dp_ctrl_private *ctrl) { - struct dp_io *dp_io; struct phy *phy; - int ret; - dp_io = &ctrl->parser->io; - phy = dp_io->phy; + phy = ctrl->phy; dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); dp_catalog_ctrl_reset(ctrl->catalog); dev_pm_opp_set_rate(ctrl->dev, 0); - ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); - if (ret) { - DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret); - } + dp_ctrl_link_clk_disable(&ctrl->dp_ctrl); phy_power_off(phy); @@ -1576,7 +1666,7 @@ static bool dp_ctrl_send_phy_test_pattern(struct dp_ctrl_private *ctrl) drm_dbg_dp(ctrl->drm_dev, "request: 0x%x\n", pattern_requested); - if (dp_catalog_ctrl_update_vx_px(ctrl->catalog, + if (dp_ctrl_set_vx_px(ctrl, ctrl->link->phy_params.v_level, ctrl->link->phy_params.p_level)) { DRM_ERROR("Failed to set v/p levels\n"); @@ -1636,11 +1726,7 @@ static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl) * running. Add the global reset just before disabling the * link clocks and core clocks. */ - ret = dp_ctrl_off(&ctrl->dp_ctrl); - if (ret) { - DRM_ERROR("failed to disable DP controller\n"); - return ret; - } + dp_ctrl_off(&ctrl->dp_ctrl); ret = dp_ctrl_on_link(&ctrl->dp_ctrl); if (ret) { @@ -1649,14 +1735,23 @@ static int dp_ctrl_process_phy_test_request(struct dp_ctrl_private *ctrl) } pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; - dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel", pixel_rate * 1000); - - ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true); + ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); if (ret) { - DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret); + DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret); return ret; } + if (ctrl->stream_clks_on) { + drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); + } else { + ret = clk_prepare_enable(ctrl->pixel_clk); + if (ret) { + DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret); + return ret; + } + ctrl->stream_clks_on = true; + } + dp_ctrl_send_phy_test_pattern(ctrl); return 0; @@ -1747,7 +1842,7 @@ int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl) rate = ctrl->panel->link_info.rate; pixel_rate = ctrl->panel->dp_mode.drm_mode.clock; - dp_power_clk_enable(ctrl->power, DP_CORE_PM, true); + dp_ctrl_core_clk_enable(&ctrl->dp_ctrl); if (ctrl->link->sink_request & DP_TEST_LINK_PHY_TEST_PATTERN) { drm_dbg_dp(ctrl->drm_dev, @@ -1758,6 +1853,8 @@ int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl) ctrl->link->link_params.rate = rate; ctrl->link->link_params.num_lanes = ctrl->panel->link_info.num_lanes; + if (ctrl->panel->dp_mode.out_fmt_is_yuv_420) + pixel_rate >>= 1; } drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n", @@ -1873,14 +1970,18 @@ int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train) pixel_rate = pixel_rate_orig = ctrl->panel->dp_mode.drm_mode.clock; - if (dp_ctrl->wide_bus_en) + if (dp_ctrl->wide_bus_en || ctrl->panel->dp_mode.out_fmt_is_yuv_420) pixel_rate >>= 1; drm_dbg_dp(ctrl->drm_dev, "rate=%d, num_lanes=%d, pixel_rate=%lu\n", ctrl->link->link_params.rate, ctrl->link->link_params.num_lanes, pixel_rate); - if (!dp_power_clk_status(ctrl->power, DP_CTRL_PM)) { /* link clk is off */ + drm_dbg_dp(ctrl->drm_dev, + "core_clk_on=%d link_clk_on=%d stream_clk_on=%d\n", + ctrl->core_clks_on, ctrl->link_clks_on, ctrl->stream_clks_on); + + if (!ctrl->link_clks_on) { /* link clk is off */ ret = dp_ctrl_enable_mainlink_clocks(ctrl); if (ret) { DRM_ERROR("Failed to start link clocks. ret=%d\n", ret); @@ -1888,14 +1989,23 @@ int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train) } } - dp_ctrl_set_clock_rate(ctrl, DP_STREAM_PM, "stream_pixel", pixel_rate * 1000); - - ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, true); + ret = clk_set_rate(ctrl->pixel_clk, pixel_rate * 1000); if (ret) { - DRM_ERROR("Unable to start pixel clocks. ret=%d\n", ret); + DRM_ERROR("Failed to set pixel clock rate. ret=%d\n", ret); goto end; } + if (ctrl->stream_clks_on) { + drm_dbg_dp(ctrl->drm_dev, "pixel clks already enabled\n"); + } else { + ret = clk_prepare_enable(ctrl->pixel_clk); + if (ret) { + DRM_ERROR("Failed to start pixel clocks. ret=%d\n", ret); + goto end; + } + ctrl->stream_clks_on = true; + } + if (force_link_train || !dp_ctrl_channel_eq_ok(ctrl)) dp_ctrl_link_retrain(ctrl); @@ -1912,7 +2022,8 @@ int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train) dp_catalog_ctrl_config_msa(ctrl->catalog, ctrl->link->link_params.rate, - pixel_rate_orig, dp_ctrl_use_fixed_nvid(ctrl)); + pixel_rate_orig, dp_ctrl_use_fixed_nvid(ctrl), + ctrl->panel->dp_mode.out_fmt_is_yuv_420); dp_ctrl_setup_tr_unit(ctrl); @@ -1930,36 +2041,28 @@ end: return ret; } -int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl) +void dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl) { struct dp_ctrl_private *ctrl; - struct dp_io *dp_io; struct phy *phy; - int ret; ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); - dp_io = &ctrl->parser->io; - phy = dp_io->phy; + phy = ctrl->phy; + + dp_catalog_panel_disable_vsc_sdp(ctrl->catalog); /* set dongle to D3 (power off) mode */ dp_link_psm_config(ctrl->link, &ctrl->panel->link_info, true); dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); - if (dp_power_clk_status(ctrl->power, DP_STREAM_PM)) { - ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false); - if (ret) { - DRM_ERROR("Failed to disable pclk. ret=%d\n", ret); - return ret; - } + if (ctrl->stream_clks_on) { + clk_disable_unprepare(ctrl->pixel_clk); + ctrl->stream_clks_on = false; } dev_pm_opp_set_rate(ctrl->dev, 0); - ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); - if (ret) { - DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret); - return ret; - } + dp_ctrl_link_clk_disable(&ctrl->dp_ctrl); phy_power_off(phy); @@ -1969,26 +2072,19 @@ int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl) drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", phy, phy->init_count, phy->power_count); - return ret; } -int dp_ctrl_off_link(struct dp_ctrl *dp_ctrl) +void dp_ctrl_off_link(struct dp_ctrl *dp_ctrl) { struct dp_ctrl_private *ctrl; - struct dp_io *dp_io; struct phy *phy; - int ret; ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); - dp_io = &ctrl->parser->io; - phy = dp_io->phy; + phy = ctrl->phy; dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); - ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); - if (ret) { - DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret); - } + dp_ctrl_link_clk_disable(&ctrl->dp_ctrl); DRM_DEBUG_DP("Before, phy=%p init_count=%d power_on=%d\n", phy, phy->init_count, phy->power_count); @@ -1997,43 +2093,33 @@ int dp_ctrl_off_link(struct dp_ctrl *dp_ctrl) DRM_DEBUG_DP("After, phy=%p init_count=%d power_on=%d\n", phy, phy->init_count, phy->power_count); - - return ret; } -int dp_ctrl_off(struct dp_ctrl *dp_ctrl) +void dp_ctrl_off(struct dp_ctrl *dp_ctrl) { struct dp_ctrl_private *ctrl; - struct dp_io *dp_io; struct phy *phy; - int ret = 0; - - if (!dp_ctrl) - return -EINVAL; ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); - dp_io = &ctrl->parser->io; - phy = dp_io->phy; + phy = ctrl->phy; + + dp_catalog_panel_disable_vsc_sdp(ctrl->catalog); dp_catalog_ctrl_mainlink_ctrl(ctrl->catalog, false); dp_catalog_ctrl_reset(ctrl->catalog); - ret = dp_power_clk_enable(ctrl->power, DP_STREAM_PM, false); - if (ret) - DRM_ERROR("Failed to disable pixel clocks. ret=%d\n", ret); + if (ctrl->stream_clks_on) { + clk_disable_unprepare(ctrl->pixel_clk); + ctrl->stream_clks_on = false; + } dev_pm_opp_set_rate(ctrl->dev, 0); - ret = dp_power_clk_enable(ctrl->power, DP_CTRL_PM, false); - if (ret) { - DRM_ERROR("Failed to disable link clocks. ret=%d\n", ret); - } + dp_ctrl_link_clk_disable(&ctrl->dp_ctrl); phy_power_off(phy); drm_dbg_dp(ctrl->drm_dev, "phy=%p init=%d power_on=%d\n", phy, phy->init_count, phy->power_count); - - return ret; } irqreturn_t dp_ctrl_isr(struct dp_ctrl *dp_ctrl) @@ -2081,10 +2167,60 @@ irqreturn_t dp_ctrl_isr(struct dp_ctrl *dp_ctrl) return ret; } +static const char *core_clks[] = { + "core_iface", + "core_aux", +}; + +static const char *ctrl_clks[] = { + "ctrl_link", + "ctrl_link_iface", +}; + +static int dp_ctrl_clk_init(struct dp_ctrl *dp_ctrl) +{ + struct dp_ctrl_private *ctrl; + struct device *dev; + int i, rc; + + ctrl = container_of(dp_ctrl, struct dp_ctrl_private, dp_ctrl); + dev = ctrl->dev; + + ctrl->num_core_clks = ARRAY_SIZE(core_clks); + ctrl->core_clks = devm_kcalloc(dev, ctrl->num_core_clks, sizeof(*ctrl->core_clks), GFP_KERNEL); + if (!ctrl->core_clks) + return -ENOMEM; + + for (i = 0; i < ctrl->num_core_clks; i++) + ctrl->core_clks[i].id = core_clks[i]; + + rc = devm_clk_bulk_get(dev, ctrl->num_core_clks, ctrl->core_clks); + if (rc) + return rc; + + ctrl->num_link_clks = ARRAY_SIZE(ctrl_clks); + ctrl->link_clks = devm_kcalloc(dev, ctrl->num_link_clks, sizeof(*ctrl->link_clks), GFP_KERNEL); + if (!ctrl->link_clks) + return -ENOMEM; + + for (i = 0; i < ctrl->num_link_clks; i++) + ctrl->link_clks[i].id = ctrl_clks[i]; + + rc = devm_clk_bulk_get(dev, ctrl->num_link_clks, ctrl->link_clks); + if (rc) + return rc; + + ctrl->pixel_clk = devm_clk_get(dev, "stream_pixel"); + if (IS_ERR(ctrl->pixel_clk)) + return PTR_ERR(ctrl->pixel_clk); + + return 0; +} + struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link, struct dp_panel *panel, struct drm_dp_aux *aux, - struct dp_power *power, struct dp_catalog *catalog, - struct dp_parser *parser) + struct dp_catalog *catalog, + struct phy *phy) { struct dp_ctrl_private *ctrl; int ret; @@ -2118,13 +2254,18 @@ struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link, init_completion(&ctrl->video_comp); /* in parameters */ - ctrl->parser = parser; ctrl->panel = panel; - ctrl->power = power; ctrl->aux = aux; ctrl->link = link; ctrl->catalog = catalog; ctrl->dev = dev; + ctrl->phy = phy; + + ret = dp_ctrl_clk_init(&ctrl->dp_ctrl); + if (ret) { + dev_err(dev, "failed to init clocks\n"); + return ERR_PTR(ret); + } return &ctrl->dp_ctrl; } diff --git a/drivers/gpu/drm/msm/dp/dp_ctrl.h b/drivers/gpu/drm/msm/dp/dp_ctrl.h index b2c27d3532bf..fa014cee7e21 100644 --- a/drivers/gpu/drm/msm/dp/dp_ctrl.h +++ b/drivers/gpu/drm/msm/dp/dp_ctrl.h @@ -9,8 +9,6 @@ #include "dp_aux.h" #include "dp_panel.h" #include "dp_link.h" -#include "dp_parser.h" -#include "dp_power.h" #include "dp_catalog.h" struct dp_ctrl { @@ -18,18 +16,20 @@ struct dp_ctrl { bool wide_bus_en; }; +struct phy; + int dp_ctrl_on_link(struct dp_ctrl *dp_ctrl); int dp_ctrl_on_stream(struct dp_ctrl *dp_ctrl, bool force_link_train); -int dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl); -int dp_ctrl_off_link(struct dp_ctrl *dp_ctrl); -int dp_ctrl_off(struct dp_ctrl *dp_ctrl); +void dp_ctrl_off_link_stream(struct dp_ctrl *dp_ctrl); +void dp_ctrl_off_link(struct dp_ctrl *dp_ctrl); +void dp_ctrl_off(struct dp_ctrl *dp_ctrl); void dp_ctrl_push_idle(struct dp_ctrl *dp_ctrl); irqreturn_t dp_ctrl_isr(struct dp_ctrl *dp_ctrl); void dp_ctrl_handle_sink_request(struct dp_ctrl *dp_ctrl); struct dp_ctrl *dp_ctrl_get(struct device *dev, struct dp_link *link, struct dp_panel *panel, struct drm_dp_aux *aux, - struct dp_power *power, struct dp_catalog *catalog, - struct dp_parser *parser); + struct dp_catalog *catalog, + struct phy *phy); void dp_ctrl_reset_irq_ctrl(struct dp_ctrl *dp_ctrl, bool enable); void dp_ctrl_phy_init(struct dp_ctrl *dp_ctrl); @@ -39,4 +39,7 @@ void dp_ctrl_irq_phy_exit(struct dp_ctrl *dp_ctrl); void dp_ctrl_set_psr(struct dp_ctrl *dp_ctrl, bool enable); void dp_ctrl_config_psr(struct dp_ctrl *dp_ctrl); +int dp_ctrl_core_clk_enable(struct dp_ctrl *dp_ctrl); +void dp_ctrl_core_clk_disable(struct dp_ctrl *dp_ctrl); + #endif /* _DP_CTRL_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_debug.c b/drivers/gpu/drm/msm/dp/dp_debug.c index 6c281dc095b9..eca5a02f9003 100644 --- a/drivers/gpu/drm/msm/dp/dp_debug.c +++ b/drivers/gpu/drm/msm/dp/dp_debug.c @@ -9,7 +9,6 @@ #include <drm/drm_connector.h> #include <drm/drm_file.h> -#include "dp_parser.h" #include "dp_catalog.h" #include "dp_aux.h" #include "dp_ctrl.h" @@ -101,7 +100,7 @@ static int dp_test_data_show(struct seq_file *m, void *data) seq_printf(m, "vdisplay: %d\n", debug->link->test_video.test_v_height); seq_printf(m, "bpc: %u\n", - dp_link_bit_depth_to_bpc(bpc)); + dp_link_bit_depth_to_bpp(bpc) / 3); } else { seq_puts(m, "0"); } diff --git a/drivers/gpu/drm/msm/dp/dp_display.c b/drivers/gpu/drm/msm/dp/dp_display.c index 4c72124ffb5d..c4cb82af5c2f 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.c +++ b/drivers/gpu/drm/msm/dp/dp_display.c @@ -9,19 +9,19 @@ #include <linux/debugfs.h> #include <linux/component.h> #include <linux/of_irq.h> +#include <linux/phy/phy.h> #include <linux/delay.h> #include <drm/display/drm_dp_aux_bus.h> +#include <drm/drm_edid.h> #include "msm_drv.h" #include "msm_kms.h" -#include "dp_parser.h" -#include "dp_power.h" +#include "dp_ctrl.h" #include "dp_catalog.h" #include "dp_aux.h" #include "dp_reg.h" #include "dp_link.h" #include "dp_panel.h" -#include "dp_ctrl.h" #include "dp_display.h" #include "dp_drm.h" #include "dp_audio.h" @@ -88,8 +88,6 @@ struct dp_display_private { struct drm_device *drm_dev; struct dentry *root; - struct dp_parser *parser; - struct dp_power *power; struct dp_catalog *catalog; struct drm_dp_aux *aux; struct dp_link *link; @@ -113,7 +111,7 @@ struct dp_display_private { struct dp_event event_list[DP_EVENT_Q_MAX]; spinlock_t event_lock; - bool wide_bus_en; + bool wide_bus_supported; struct dp_audio *audio; }; @@ -122,7 +120,7 @@ struct msm_dp_desc { phys_addr_t io_start; unsigned int id; unsigned int connector_type; - bool wide_bus_en; + bool wide_bus_supported; }; static const struct msm_dp_desc sc7180_dp_descs[] = { @@ -131,8 +129,8 @@ static const struct msm_dp_desc sc7180_dp_descs[] = { }; static const struct msm_dp_desc sc7280_dp_descs[] = { - { .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true }, - { .io_start = 0x0aea0000, .id = MSM_DP_CONTROLLER_1, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_en = true }, + { .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_supported = true }, + { .io_start = 0x0aea0000, .id = MSM_DP_CONTROLLER_1, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_supported = true }, {} }; @@ -144,22 +142,22 @@ static const struct msm_dp_desc sc8180x_dp_descs[] = { }; static const struct msm_dp_desc sc8280xp_dp_descs[] = { - { .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true }, - { .io_start = 0x0ae98000, .id = MSM_DP_CONTROLLER_1, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true }, - { .io_start = 0x0ae9a000, .id = MSM_DP_CONTROLLER_2, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true }, - { .io_start = 0x0aea0000, .id = MSM_DP_CONTROLLER_3, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true }, - { .io_start = 0x22090000, .id = MSM_DP_CONTROLLER_0, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true }, - { .io_start = 0x22098000, .id = MSM_DP_CONTROLLER_1, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true }, - { .io_start = 0x2209a000, .id = MSM_DP_CONTROLLER_2, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true }, - { .io_start = 0x220a0000, .id = MSM_DP_CONTROLLER_3, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_en = true }, + { .io_start = 0x0ae90000, .id = MSM_DP_CONTROLLER_0, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_supported = true }, + { .io_start = 0x0ae98000, .id = MSM_DP_CONTROLLER_1, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_supported = true }, + { .io_start = 0x0ae9a000, .id = MSM_DP_CONTROLLER_2, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_supported = true }, + { .io_start = 0x0aea0000, .id = MSM_DP_CONTROLLER_3, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_supported = true }, + { .io_start = 0x22090000, .id = MSM_DP_CONTROLLER_0, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_supported = true }, + { .io_start = 0x22098000, .id = MSM_DP_CONTROLLER_1, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_supported = true }, + { .io_start = 0x2209a000, .id = MSM_DP_CONTROLLER_2, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_supported = true }, + { .io_start = 0x220a0000, .id = MSM_DP_CONTROLLER_3, .connector_type = DRM_MODE_CONNECTOR_DisplayPort, .wide_bus_supported = true }, {} }; static const struct msm_dp_desc sc8280xp_edp_descs[] = { - { .io_start = 0x0ae9a000, .id = MSM_DP_CONTROLLER_2, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_en = true }, - { .io_start = 0x0aea0000, .id = MSM_DP_CONTROLLER_3, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_en = true }, - { .io_start = 0x2209a000, .id = MSM_DP_CONTROLLER_2, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_en = true }, - { .io_start = 0x220a0000, .id = MSM_DP_CONTROLLER_3, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_en = true }, + { .io_start = 0x0ae9a000, .id = MSM_DP_CONTROLLER_2, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_supported = true }, + { .io_start = 0x0aea0000, .id = MSM_DP_CONTROLLER_3, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_supported = true }, + { .io_start = 0x2209a000, .id = MSM_DP_CONTROLLER_2, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_supported = true }, + { .io_start = 0x220a0000, .id = MSM_DP_CONTROLLER_3, .connector_type = DRM_MODE_CONNECTOR_eDP, .wide_bus_supported = true }, {} }; @@ -374,12 +372,6 @@ static int dp_display_process_hpd_high(struct dp_display_private *dp) int rc = 0; struct edid *edid; - dp->panel->max_dp_lanes = dp->parser->max_dp_lanes; - dp->panel->max_dp_link_rate = dp->parser->max_dp_link_rate; - - drm_dbg_dp(dp->drm_dev, "max_lanes=%d max_link_rate=%d\n", - dp->panel->max_dp_lanes, dp->panel->max_dp_link_rate); - rc = dp_panel_read_sink_caps(dp->panel, dp->dp_display.connector); if (rc) goto end; @@ -399,8 +391,6 @@ static int dp_display_process_hpd_high(struct dp_display_private *dp) dp->audio_supported = drm_detect_monitor_audio(edid); dp_panel_handle_sink_request(dp->panel); - dp->dp_display.max_dp_lanes = dp->parser->max_dp_lanes; - /* * set sink to normal operation mode -- D0 * before dpcd read @@ -450,7 +440,7 @@ static void dp_display_host_init(struct dp_display_private *dp) dp->dp_display.connector_type, dp->core_initialized, dp->phy_initialized); - dp_power_init(dp->power); + dp_ctrl_core_clk_enable(dp->ctrl); dp_ctrl_reset_irq_ctrl(dp->ctrl, true); dp_aux_init(dp->aux); dp->core_initialized = true; @@ -464,7 +454,7 @@ static void dp_display_host_deinit(struct dp_display_private *dp) dp_ctrl_reset_irq_ctrl(dp->ctrl, false); dp_aux_deinit(dp->aux); - dp_power_deinit(dp->power); + dp_ctrl_core_clk_disable(dp->ctrl); dp->core_initialized = false; } @@ -730,16 +720,13 @@ static int dp_init_sub_modules(struct dp_display_private *dp) struct dp_panel_in panel_in = { .dev = dev, }; + struct phy *phy; - dp->parser = dp_parser_get(dp->dp_display.pdev); - if (IS_ERR(dp->parser)) { - rc = PTR_ERR(dp->parser); - DRM_ERROR("failed to initialize parser, rc = %d\n", rc); - dp->parser = NULL; - goto error; - } + phy = devm_phy_get(dev, "dp"); + if (IS_ERR(phy)) + return PTR_ERR(phy); - dp->catalog = dp_catalog_get(dev, &dp->parser->io); + dp->catalog = dp_catalog_get(dev); if (IS_ERR(dp->catalog)) { rc = PTR_ERR(dp->catalog); DRM_ERROR("failed to initialize catalog, rc = %d\n", rc); @@ -747,15 +734,9 @@ static int dp_init_sub_modules(struct dp_display_private *dp) goto error; } - dp->power = dp_power_get(dev, dp->parser); - if (IS_ERR(dp->power)) { - rc = PTR_ERR(dp->power); - DRM_ERROR("failed to initialize power, rc = %d\n", rc); - dp->power = NULL; - goto error; - } - - dp->aux = dp_aux_get(dev, dp->catalog, dp->dp_display.is_edp); + dp->aux = dp_aux_get(dev, dp->catalog, + phy, + dp->dp_display.is_edp); if (IS_ERR(dp->aux)) { rc = PTR_ERR(dp->aux); DRM_ERROR("failed to initialize aux, rc = %d\n", rc); @@ -784,7 +765,8 @@ static int dp_init_sub_modules(struct dp_display_private *dp) } dp->ctrl = dp_ctrl_get(dev, dp->link, dp->panel, dp->aux, - dp->power, dp->catalog, dp->parser); + dp->catalog, + phy); if (IS_ERR(dp->ctrl)) { rc = PTR_ERR(dp->ctrl); DRM_ERROR("failed to initialize ctrl, rc = %d\n", rc); @@ -800,10 +782,6 @@ static int dp_init_sub_modules(struct dp_display_private *dp) goto error_ctrl; } - /* populate wide_bus_en to differernt layers */ - dp->ctrl->wide_bus_en = dp->wide_bus_en; - dp->catalog->wide_bus_en = dp->wide_bus_en; - return rc; error_ctrl: @@ -824,6 +802,7 @@ static int dp_display_set_mode(struct msm_dp *dp_display, drm_mode_copy(&dp->panel->dp_mode.drm_mode, &mode->drm_mode); dp->panel->dp_mode.bpp = mode->bpp; dp->panel->dp_mode.capabilities = mode->capabilities; + dp->panel->dp_mode.out_fmt_is_yuv_420 = mode->out_fmt_is_yuv_420; dp_panel_init_panel_info(dp->panel); return 0; } @@ -952,6 +931,10 @@ enum drm_mode_status dp_bridge_mode_valid(struct drm_bridge *bridge, dp_display = container_of(dp, struct dp_display_private, dp_display); link_info = &dp_display->panel->link_info; + if (drm_mode_is_420_only(&dp->connector->display_info, mode) && + dp_display->panel->vsc_sdp_supported) + mode_pclk_khz /= 2; + mode_bpp = dp->connector->display_info.bpc * num_components; if (!mode_bpp) mode_bpp = default_bpp; @@ -1226,16 +1209,25 @@ static const struct msm_dp_desc *dp_display_get_desc(struct platform_device *pde return NULL; } -static int dp_display_get_next_bridge(struct msm_dp *dp); - static int dp_display_probe_tail(struct device *dev) { struct msm_dp *dp = dev_get_drvdata(dev); int ret; - ret = dp_display_get_next_bridge(dp); - if (ret) - return ret; + /* + * External bridges are mandatory for eDP interfaces: one has to + * provide at least an eDP panel (which gets wrapped into panel-bridge). + * + * For DisplayPort interfaces external bridges are optional, so + * silently ignore an error if one is not present (-ENODEV). + */ + dp->next_bridge = devm_drm_of_get_bridge(&dp->pdev->dev, dp->pdev->dev.of_node, 1, 0); + if (IS_ERR(dp->next_bridge)) { + ret = PTR_ERR(dp->next_bridge); + dp->next_bridge = NULL; + if (dp->is_edp || ret != -ENODEV) + return ret; + } ret = component_add(dev, &dp_display_comp_ops); if (ret) @@ -1272,7 +1264,7 @@ static int dp_display_probe(struct platform_device *pdev) dp->name = "drm_dp"; dp->id = desc->id; dp->dp_display.connector_type = desc->connector_type; - dp->wide_bus_en = desc->wide_bus_en; + dp->wide_bus_supported = desc->wide_bus_supported; dp->dp_display.is_edp = (dp->dp_display.connector_type == DRM_MODE_CONNECTOR_eDP); @@ -1282,18 +1274,6 @@ static int dp_display_probe(struct platform_device *pdev) return -EPROBE_DEFER; } - rc = dp->parser->parse(dp->parser); - if (rc) { - DRM_ERROR("device tree parsing failed\n"); - goto err; - } - - rc = dp_power_client_init(dp->power); - if (rc) { - DRM_ERROR("Power client create failed\n"); - goto err; - } - /* setup event q */ mutex_init(&dp->event_mutex); init_waitqueue_head(&dp->event_q); @@ -1412,13 +1392,34 @@ void __exit msm_dp_unregister(void) platform_driver_unregister(&dp_display_driver); } +bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display, + const struct drm_display_mode *mode) +{ + struct dp_display_private *dp; + const struct drm_display_info *info; + + dp = container_of(dp_display, struct dp_display_private, dp_display); + info = &dp_display->connector->display_info; + + return dp->panel->vsc_sdp_supported && drm_mode_is_420_only(info, mode); +} + +bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, + const struct drm_display_mode *mode) +{ + return msm_dp_is_yuv_420_enabled(dp_display, mode); +} + bool msm_dp_wide_bus_available(const struct msm_dp *dp_display) { struct dp_display_private *dp; dp = container_of(dp_display, struct dp_display_private, dp_display); - return dp->wide_bus_en; + if (dp->dp_mode.out_fmt_is_yuv_420) + return false; + + return dp->wide_bus_supported; } void dp_display_debugfs_init(struct msm_dp *dp_display, struct dentry *root, bool is_edp) @@ -1440,32 +1441,8 @@ void dp_display_debugfs_init(struct msm_dp *dp_display, struct dentry *root, boo } } -static int dp_display_get_next_bridge(struct msm_dp *dp) -{ - int rc; - struct dp_display_private *dp_priv; - - dp_priv = container_of(dp, struct dp_display_private, dp_display); - - /* - * External bridges are mandatory for eDP interfaces: one has to - * provide at least an eDP panel (which gets wrapped into panel-bridge). - * - * For DisplayPort interfaces external bridges are optional, so - * silently ignore an error if one is not present (-ENODEV). - */ - rc = devm_dp_parser_find_next_bridge(&dp->pdev->dev, dp_priv->parser); - if (!dp->is_edp && rc == -ENODEV) - return 0; - - if (!rc) - dp->next_bridge = dp_priv->parser->next_bridge; - - return rc; -} - int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, - struct drm_encoder *encoder) + struct drm_encoder *encoder, bool yuv_supported) { struct dp_display_private *dp_priv; int ret; @@ -1481,7 +1458,7 @@ int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, return ret; } - dp_display->connector = dp_drm_connector_init(dp_display, encoder); + dp_display->connector = dp_drm_connector_init(dp_display, encoder, yuv_supported); if (IS_ERR(dp_display->connector)) { ret = PTR_ERR(dp_display->connector); DRM_DEV_ERROR(dev->dev, @@ -1611,8 +1588,10 @@ void dp_bridge_mode_set(struct drm_bridge *drm_bridge, struct msm_dp_bridge *dp_bridge = to_dp_bridge(drm_bridge); struct msm_dp *dp = dp_bridge->dp_display; struct dp_display_private *dp_display; + struct dp_panel *dp_panel; dp_display = container_of(dp, struct dp_display_private, dp_display); + dp_panel = dp_display->panel; memset(&dp_display->dp_mode, 0x0, sizeof(struct dp_display_mode)); @@ -1631,6 +1610,16 @@ void dp_bridge_mode_set(struct drm_bridge *drm_bridge, dp_display->dp_mode.h_active_low = !!(dp_display->dp_mode.drm_mode.flags & DRM_MODE_FLAG_NHSYNC); + + dp_display->dp_mode.out_fmt_is_yuv_420 = + drm_mode_is_420_only(&dp->connector->display_info, adjusted_mode) && + dp_panel->vsc_sdp_supported; + + /* populate wide_bus_support to different layers */ + dp_display->ctrl->wide_bus_en = + dp_display->dp_mode.out_fmt_is_yuv_420 ? false : dp_display->wide_bus_supported; + dp_display->catalog->wide_bus_en = + dp_display->dp_mode.out_fmt_is_yuv_420 ? false : dp_display->wide_bus_supported; } void dp_bridge_hpd_enable(struct drm_bridge *bridge) diff --git a/drivers/gpu/drm/msm/dp/dp_display.h b/drivers/gpu/drm/msm/dp/dp_display.h index 102f3507d824..234dada88687 100644 --- a/drivers/gpu/drm/msm/dp/dp_display.h +++ b/drivers/gpu/drm/msm/dp/dp_display.h @@ -10,6 +10,8 @@ #include <sound/hdmi-codec.h> #include "disp/msm_disp_snapshot.h" +#define DP_MAX_PIXEL_CLK_KHZ 675000 + struct msm_dp { struct drm_device *drm_dev; struct platform_device *pdev; @@ -28,7 +30,6 @@ struct msm_dp { bool wide_bus_en; - u32 max_dp_lanes; struct dp_audio *dp_audio; bool psr_supported; }; diff --git a/drivers/gpu/drm/msm/dp/dp_drm.c b/drivers/gpu/drm/msm/dp/dp_drm.c index 46e6889037e8..a819a4ff76a9 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.c +++ b/drivers/gpu/drm/msm/dp/dp_drm.c @@ -353,7 +353,8 @@ int dp_bridge_init(struct msm_dp *dp_display, struct drm_device *dev, } /* connector initialization */ -struct drm_connector *dp_drm_connector_init(struct msm_dp *dp_display, struct drm_encoder *encoder) +struct drm_connector *dp_drm_connector_init(struct msm_dp *dp_display, struct drm_encoder *encoder, + bool yuv_supported) { struct drm_connector *connector = NULL; @@ -364,6 +365,9 @@ struct drm_connector *dp_drm_connector_init(struct msm_dp *dp_display, struct dr if (!dp_display->is_edp) drm_connector_attach_dp_subconnector_property(connector); + if (yuv_supported) + connector->ycbcr_420_allowed = true; + drm_connector_attach_encoder(connector, encoder); return connector; diff --git a/drivers/gpu/drm/msm/dp/dp_drm.h b/drivers/gpu/drm/msm/dp/dp_drm.h index b3d684db2383..45e57ac25a4d 100644 --- a/drivers/gpu/drm/msm/dp/dp_drm.h +++ b/drivers/gpu/drm/msm/dp/dp_drm.h @@ -19,7 +19,8 @@ struct msm_dp_bridge { #define to_dp_bridge(x) container_of((x), struct msm_dp_bridge, bridge) -struct drm_connector *dp_drm_connector_init(struct msm_dp *dp_display, struct drm_encoder *encoder); +struct drm_connector *dp_drm_connector_init(struct msm_dp *dp_display, struct drm_encoder *encoder, + bool yuv_supported); int dp_bridge_init(struct msm_dp *dp_display, struct drm_device *dev, struct drm_encoder *encoder); diff --git a/drivers/gpu/drm/msm/dp/dp_link.h b/drivers/gpu/drm/msm/dp/dp_link.h index 9dd4dd926530..83da170bc56b 100644 --- a/drivers/gpu/drm/msm/dp/dp_link.h +++ b/drivers/gpu/drm/msm/dp/dp_link.h @@ -112,29 +112,6 @@ static inline u32 dp_link_bit_depth_to_bpp(u32 tbd) } } -/** - * dp_test_bit_depth_to_bpc() - convert test bit depth to bpc - * @tbd: test bit depth - * - * Returns the bits per comp (bpc) to be used corresponding to the - * bit depth value. This function assumes that bit depth has - * already been validated. - */ -static inline u32 dp_link_bit_depth_to_bpc(u32 tbd) -{ - switch (tbd) { - case DP_TEST_BIT_DEPTH_6: - return 6; - case DP_TEST_BIT_DEPTH_8: - return 8; - case DP_TEST_BIT_DEPTH_10: - return 10; - case DP_TEST_BIT_DEPTH_UNKNOWN: - default: - return 0; - } -} - void dp_link_reset_phy_params_vx_px(struct dp_link *dp_link); u32 dp_link_get_test_bits_depth(struct dp_link *dp_link, u32 bpp); int dp_link_process_request(struct dp_link *dp_link); diff --git a/drivers/gpu/drm/msm/dp/dp_panel.c b/drivers/gpu/drm/msm/dp/dp_panel.c index 127f6af995cd..8e7069453952 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.c +++ b/drivers/gpu/drm/msm/dp/dp_panel.c @@ -4,11 +4,16 @@ */ #include "dp_panel.h" +#include "dp_utils.h" #include <drm/drm_connector.h> #include <drm/drm_edid.h> +#include <drm/drm_of.h> #include <drm/drm_print.h> +#define DP_MAX_NUM_DP_LANES 4 +#define DP_LINK_RATE_HBR2 540000 /* kbytes */ + struct dp_panel_private { struct device *dev; struct drm_device *drm_dev; @@ -53,6 +58,7 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel) if (rc) return rc; + dp_panel->vsc_sdp_supported = drm_dp_vsc_sdp_supported(panel->aux, dpcd); link_info = &dp_panel->link_info; link_info->revision = dpcd[DP_DPCD_REV]; major = (link_info->revision >> 4) & 0x0f; @@ -138,6 +144,9 @@ int dp_panel_read_sink_caps(struct dp_panel *dp_panel, panel = container_of(dp_panel, struct dp_panel_private, dp_panel); + drm_dbg_dp(panel->drm_dev, "max_lanes=%d max_link_rate=%d\n", + dp_panel->max_dp_lanes, dp_panel->max_dp_link_rate); + rc = dp_panel_read_dpcd(dp_panel); if (rc) { DRM_ERROR("read dpcd failed %d\n", rc); @@ -280,6 +289,53 @@ void dp_panel_tpg_config(struct dp_panel *dp_panel, bool enable) dp_catalog_panel_tpg_enable(catalog, &panel->dp_panel.dp_mode.drm_mode); } +static int dp_panel_setup_vsc_sdp_yuv_420(struct dp_panel *dp_panel) +{ + struct dp_catalog *catalog; + struct dp_panel_private *panel; + struct dp_display_mode *dp_mode; + struct drm_dp_vsc_sdp vsc_sdp_data; + struct dp_sdp vsc_sdp; + ssize_t len; + + if (!dp_panel) { + DRM_ERROR("invalid input\n"); + return -EINVAL; + } + + panel = container_of(dp_panel, struct dp_panel_private, dp_panel); + catalog = panel->catalog; + dp_mode = &dp_panel->dp_mode; + + memset(&vsc_sdp_data, 0, sizeof(vsc_sdp_data)); + + /* VSC SDP header as per table 2-118 of DP 1.4 specification */ + vsc_sdp_data.sdp_type = DP_SDP_VSC; + vsc_sdp_data.revision = 0x05; + vsc_sdp_data.length = 0x13; + + /* VSC SDP Payload for DB16 */ + vsc_sdp_data.pixelformat = DP_PIXELFORMAT_YUV420; + vsc_sdp_data.colorimetry = DP_COLORIMETRY_DEFAULT; + + /* VSC SDP Payload for DB17 */ + vsc_sdp_data.bpc = dp_mode->bpp / 3; + vsc_sdp_data.dynamic_range = DP_DYNAMIC_RANGE_CTA; + + /* VSC SDP Payload for DB18 */ + vsc_sdp_data.content_type = DP_CONTENT_TYPE_GRAPHICS; + + len = drm_dp_vsc_sdp_pack(&vsc_sdp_data, &vsc_sdp); + if (len < 0) { + DRM_ERROR("unable to pack vsc sdp\n"); + return len; + } + + dp_catalog_panel_enable_vsc_sdp(catalog, &vsc_sdp); + + return 0; +} + void dp_panel_dump_regs(struct dp_panel *dp_panel) { struct dp_catalog *catalog; @@ -343,6 +399,10 @@ int dp_panel_timing_cfg(struct dp_panel *dp_panel) catalog->dp_active = data; dp_catalog_panel_timing_cfg(catalog); + + if (dp_panel->dp_mode.out_fmt_is_yuv_420) + dp_panel_setup_vsc_sdp_yuv_420(dp_panel); + panel->panel_on = true; return 0; @@ -386,10 +446,65 @@ int dp_panel_init_panel_info(struct dp_panel *dp_panel) return 0; } +static u32 dp_panel_link_frequencies(struct device_node *of_node) +{ + struct device_node *endpoint; + u64 frequency = 0; + int cnt; + + endpoint = of_graph_get_endpoint_by_regs(of_node, 1, 0); /* port@1 */ + if (!endpoint) + return 0; + + cnt = of_property_count_u64_elems(endpoint, "link-frequencies"); + + if (cnt > 0) + of_property_read_u64_index(endpoint, "link-frequencies", + cnt - 1, &frequency); + of_node_put(endpoint); + + do_div(frequency, + 10 * /* from symbol rate to link rate */ + 1000); /* kbytes */ + + return frequency; +} + +static int dp_panel_parse_dt(struct dp_panel *dp_panel) +{ + struct dp_panel_private *panel; + struct device_node *of_node; + int cnt; + + panel = container_of(dp_panel, struct dp_panel_private, dp_panel); + of_node = panel->dev->of_node; + + /* + * data-lanes is the property of dp_out endpoint + */ + cnt = drm_of_get_data_lanes_count_ep(of_node, 1, 0, 1, DP_MAX_NUM_DP_LANES); + if (cnt < 0) { + /* legacy code, data-lanes is the property of mdss_dp node */ + cnt = drm_of_get_data_lanes_count(of_node, 1, DP_MAX_NUM_DP_LANES); + } + + if (cnt > 0) + dp_panel->max_dp_lanes = cnt; + else + dp_panel->max_dp_lanes = DP_MAX_NUM_DP_LANES; /* 4 lanes */ + + dp_panel->max_dp_link_rate = dp_panel_link_frequencies(of_node); + if (!dp_panel->max_dp_link_rate) + dp_panel->max_dp_link_rate = DP_LINK_RATE_HBR2; + + return 0; +} + struct dp_panel *dp_panel_get(struct dp_panel_in *in) { struct dp_panel_private *panel; struct dp_panel *dp_panel; + int ret; if (!in->dev || !in->catalog || !in->aux || !in->link) { DRM_ERROR("invalid input\n"); @@ -408,6 +523,10 @@ struct dp_panel *dp_panel_get(struct dp_panel_in *in) dp_panel = &panel->dp_panel; dp_panel->max_bw_code = DP_LINK_BW_8_1; + ret = dp_panel_parse_dt(dp_panel); + if (ret) + return ERR_PTR(ret); + return dp_panel; } diff --git a/drivers/gpu/drm/msm/dp/dp_panel.h b/drivers/gpu/drm/msm/dp/dp_panel.h index a0dfc579c5f9..e843f5062d1f 100644 --- a/drivers/gpu/drm/msm/dp/dp_panel.h +++ b/drivers/gpu/drm/msm/dp/dp_panel.h @@ -19,6 +19,7 @@ struct dp_display_mode { u32 bpp; u32 h_active_low; u32 v_active_low; + bool out_fmt_is_yuv_420; }; struct dp_panel_in { @@ -45,6 +46,7 @@ struct dp_panel { struct dp_display_mode dp_mode; struct dp_panel_psr psr_cap; bool video_test; + bool vsc_sdp_supported; u32 vic; u32 max_dp_lanes; diff --git a/drivers/gpu/drm/msm/dp/dp_parser.c b/drivers/gpu/drm/msm/dp/dp_parser.c deleted file mode 100644 index 7032dcc8842b..000000000000 --- a/drivers/gpu/drm/msm/dp/dp_parser.c +++ /dev/null @@ -1,327 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. - */ - -#include <linux/of_gpio.h> -#include <linux/phy/phy.h> - -#include <drm/drm_of.h> -#include <drm/drm_print.h> -#include <drm/drm_bridge.h> - -#include "dp_parser.h" -#include "dp_reg.h" - -#define DP_DEFAULT_AHB_OFFSET 0x0000 -#define DP_DEFAULT_AHB_SIZE 0x0200 -#define DP_DEFAULT_AUX_OFFSET 0x0200 -#define DP_DEFAULT_AUX_SIZE 0x0200 -#define DP_DEFAULT_LINK_OFFSET 0x0400 -#define DP_DEFAULT_LINK_SIZE 0x0C00 -#define DP_DEFAULT_P0_OFFSET 0x1000 -#define DP_DEFAULT_P0_SIZE 0x0400 - -static void __iomem *dp_ioremap(struct platform_device *pdev, int idx, size_t *len) -{ - struct resource *res; - void __iomem *base; - - base = devm_platform_get_and_ioremap_resource(pdev, idx, &res); - if (!IS_ERR(base)) - *len = resource_size(res); - - return base; -} - -static int dp_parser_ctrl_res(struct dp_parser *parser) -{ - struct platform_device *pdev = parser->pdev; - struct dp_io *io = &parser->io; - struct dss_io_data *dss = &io->dp_controller; - - dss->ahb.base = dp_ioremap(pdev, 0, &dss->ahb.len); - if (IS_ERR(dss->ahb.base)) - return PTR_ERR(dss->ahb.base); - - dss->aux.base = dp_ioremap(pdev, 1, &dss->aux.len); - if (IS_ERR(dss->aux.base)) { - /* - * The initial binding had a single reg, but in order to - * support variation in the sub-region sizes this was split. - * dp_ioremap() will fail with -EINVAL here if only a single - * reg is specified, so fill in the sub-region offsets and - * lengths based on this single region. - */ - if (PTR_ERR(dss->aux.base) == -EINVAL) { - if (dss->ahb.len < DP_DEFAULT_P0_OFFSET + DP_DEFAULT_P0_SIZE) { - DRM_ERROR("legacy memory region not large enough\n"); - return -EINVAL; - } - - dss->ahb.len = DP_DEFAULT_AHB_SIZE; - dss->aux.base = dss->ahb.base + DP_DEFAULT_AUX_OFFSET; - dss->aux.len = DP_DEFAULT_AUX_SIZE; - dss->link.base = dss->ahb.base + DP_DEFAULT_LINK_OFFSET; - dss->link.len = DP_DEFAULT_LINK_SIZE; - dss->p0.base = dss->ahb.base + DP_DEFAULT_P0_OFFSET; - dss->p0.len = DP_DEFAULT_P0_SIZE; - } else { - DRM_ERROR("unable to remap aux region: %pe\n", dss->aux.base); - return PTR_ERR(dss->aux.base); - } - } else { - dss->link.base = dp_ioremap(pdev, 2, &dss->link.len); - if (IS_ERR(dss->link.base)) { - DRM_ERROR("unable to remap link region: %pe\n", dss->link.base); - return PTR_ERR(dss->link.base); - } - - dss->p0.base = dp_ioremap(pdev, 3, &dss->p0.len); - if (IS_ERR(dss->p0.base)) { - DRM_ERROR("unable to remap p0 region: %pe\n", dss->p0.base); - return PTR_ERR(dss->p0.base); - } - } - - io->phy = devm_phy_get(&pdev->dev, "dp"); - if (IS_ERR(io->phy)) - return PTR_ERR(io->phy); - - return 0; -} - -static u32 dp_parser_link_frequencies(struct device_node *of_node) -{ - struct device_node *endpoint; - u64 frequency = 0; - int cnt; - - endpoint = of_graph_get_endpoint_by_regs(of_node, 1, 0); /* port@1 */ - if (!endpoint) - return 0; - - cnt = of_property_count_u64_elems(endpoint, "link-frequencies"); - - if (cnt > 0) - of_property_read_u64_index(endpoint, "link-frequencies", - cnt - 1, &frequency); - of_node_put(endpoint); - - do_div(frequency, - 10 * /* from symbol rate to link rate */ - 1000); /* kbytes */ - - return frequency; -} - -static int dp_parser_misc(struct dp_parser *parser) -{ - struct device_node *of_node = parser->pdev->dev.of_node; - int cnt; - - /* - * data-lanes is the property of dp_out endpoint - */ - cnt = drm_of_get_data_lanes_count_ep(of_node, 1, 0, 1, DP_MAX_NUM_DP_LANES); - if (cnt < 0) { - /* legacy code, data-lanes is the property of mdss_dp node */ - cnt = drm_of_get_data_lanes_count(of_node, 1, DP_MAX_NUM_DP_LANES); - } - - if (cnt > 0) - parser->max_dp_lanes = cnt; - else - parser->max_dp_lanes = DP_MAX_NUM_DP_LANES; /* 4 lanes */ - - parser->max_dp_link_rate = dp_parser_link_frequencies(of_node); - if (!parser->max_dp_link_rate) - parser->max_dp_link_rate = DP_LINK_RATE_HBR2; - - return 0; -} - -static inline bool dp_parser_check_prefix(const char *clk_prefix, - const char *clk_name) -{ - return !strncmp(clk_prefix, clk_name, strlen(clk_prefix)); -} - -static int dp_parser_init_clk_data(struct dp_parser *parser) -{ - int num_clk, i, rc; - int core_clk_count = 0, ctrl_clk_count = 0, stream_clk_count = 0; - const char *clk_name; - struct device *dev = &parser->pdev->dev; - struct dss_module_power *core_power = &parser->mp[DP_CORE_PM]; - struct dss_module_power *ctrl_power = &parser->mp[DP_CTRL_PM]; - struct dss_module_power *stream_power = &parser->mp[DP_STREAM_PM]; - - num_clk = of_property_count_strings(dev->of_node, "clock-names"); - if (num_clk <= 0) { - DRM_ERROR("no clocks are defined\n"); - return -EINVAL; - } - - for (i = 0; i < num_clk; i++) { - rc = of_property_read_string_index(dev->of_node, - "clock-names", i, &clk_name); - if (rc < 0) - return rc; - - if (dp_parser_check_prefix("core", clk_name)) - core_clk_count++; - - if (dp_parser_check_prefix("ctrl", clk_name)) - ctrl_clk_count++; - - if (dp_parser_check_prefix("stream", clk_name)) - stream_clk_count++; - } - - /* Initialize the CORE power module */ - if (core_clk_count == 0) { - DRM_ERROR("no core clocks are defined\n"); - return -EINVAL; - } - - core_power->num_clk = core_clk_count; - core_power->clocks = devm_kcalloc(dev, - core_power->num_clk, sizeof(struct clk_bulk_data), - GFP_KERNEL); - if (!core_power->clocks) - return -ENOMEM; - - /* Initialize the CTRL power module */ - if (ctrl_clk_count == 0) { - DRM_ERROR("no ctrl clocks are defined\n"); - return -EINVAL; - } - - ctrl_power->num_clk = ctrl_clk_count; - ctrl_power->clocks = devm_kcalloc(dev, - ctrl_power->num_clk, sizeof(struct clk_bulk_data), - GFP_KERNEL); - if (!ctrl_power->clocks) { - ctrl_power->num_clk = 0; - return -ENOMEM; - } - - /* Initialize the STREAM power module */ - if (stream_clk_count == 0) { - DRM_ERROR("no stream (pixel) clocks are defined\n"); - return -EINVAL; - } - - stream_power->num_clk = stream_clk_count; - stream_power->clocks = devm_kcalloc(dev, - stream_power->num_clk, sizeof(struct clk_bulk_data), - GFP_KERNEL); - if (!stream_power->clocks) { - stream_power->num_clk = 0; - return -ENOMEM; - } - - return 0; -} - -static int dp_parser_clock(struct dp_parser *parser) -{ - int rc = 0, i = 0; - int num_clk = 0; - int core_clk_index = 0, ctrl_clk_index = 0, stream_clk_index = 0; - int core_clk_count = 0, ctrl_clk_count = 0, stream_clk_count = 0; - const char *clk_name; - struct device *dev = &parser->pdev->dev; - struct dss_module_power *core_power = &parser->mp[DP_CORE_PM]; - struct dss_module_power *ctrl_power = &parser->mp[DP_CTRL_PM]; - struct dss_module_power *stream_power = &parser->mp[DP_STREAM_PM]; - - rc = dp_parser_init_clk_data(parser); - if (rc) { - DRM_ERROR("failed to initialize power data %d\n", rc); - return -EINVAL; - } - - core_clk_count = core_power->num_clk; - ctrl_clk_count = ctrl_power->num_clk; - stream_clk_count = stream_power->num_clk; - - num_clk = core_clk_count + ctrl_clk_count + stream_clk_count; - - for (i = 0; i < num_clk; i++) { - rc = of_property_read_string_index(dev->of_node, "clock-names", - i, &clk_name); - if (rc) { - DRM_ERROR("error reading clock-names %d\n", rc); - return rc; - } - if (dp_parser_check_prefix("core", clk_name) && - core_clk_index < core_clk_count) { - core_power->clocks[core_clk_index].id = devm_kstrdup(dev, clk_name, GFP_KERNEL); - core_clk_index++; - } else if (dp_parser_check_prefix("stream", clk_name) && - stream_clk_index < stream_clk_count) { - stream_power->clocks[stream_clk_index].id = devm_kstrdup(dev, clk_name, GFP_KERNEL); - stream_clk_index++; - } else if (dp_parser_check_prefix("ctrl", clk_name) && - ctrl_clk_index < ctrl_clk_count) { - ctrl_power->clocks[ctrl_clk_index].id = devm_kstrdup(dev, clk_name, GFP_KERNEL); - ctrl_clk_index++; - } - } - - return 0; -} - -int devm_dp_parser_find_next_bridge(struct device *dev, struct dp_parser *parser) -{ - struct platform_device *pdev = parser->pdev; - struct drm_bridge *bridge; - - bridge = devm_drm_of_get_bridge(dev, pdev->dev.of_node, 1, 0); - if (IS_ERR(bridge)) - return PTR_ERR(bridge); - - parser->next_bridge = bridge; - - return 0; -} - -static int dp_parser_parse(struct dp_parser *parser) -{ - int rc = 0; - - if (!parser) { - DRM_ERROR("invalid input\n"); - return -EINVAL; - } - - rc = dp_parser_ctrl_res(parser); - if (rc) - return rc; - - rc = dp_parser_misc(parser); - if (rc) - return rc; - - rc = dp_parser_clock(parser); - if (rc) - return rc; - - return 0; -} - -struct dp_parser *dp_parser_get(struct platform_device *pdev) -{ - struct dp_parser *parser; - - parser = devm_kzalloc(&pdev->dev, sizeof(*parser), GFP_KERNEL); - if (!parser) - return ERR_PTR(-ENOMEM); - - parser->parse = dp_parser_parse; - parser->pdev = pdev; - - return parser; -} diff --git a/drivers/gpu/drm/msm/dp/dp_parser.h b/drivers/gpu/drm/msm/dp/dp_parser.h deleted file mode 100644 index 1f068626d445..000000000000 --- a/drivers/gpu/drm/msm/dp/dp_parser.h +++ /dev/null @@ -1,155 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. - */ - -#ifndef _DP_PARSER_H_ -#define _DP_PARSER_H_ - -#include <linux/platform_device.h> -#include <linux/phy/phy.h> -#include <linux/phy/phy-dp.h> - -#include "msm_drv.h" - -#define DP_LABEL "MDSS DP DISPLAY" -#define DP_MAX_PIXEL_CLK_KHZ 675000 -#define DP_MAX_NUM_DP_LANES 4 -#define DP_LINK_RATE_HBR2 540000 /* kbytes */ - -enum dp_pm_type { - DP_CORE_PM, - DP_CTRL_PM, - DP_STREAM_PM, - DP_PHY_PM, - DP_MAX_PM -}; - -struct dss_io_region { - size_t len; - void __iomem *base; -}; - -struct dss_io_data { - struct dss_io_region ahb; - struct dss_io_region aux; - struct dss_io_region link; - struct dss_io_region p0; -}; - -static inline const char *dp_parser_pm_name(enum dp_pm_type module) -{ - switch (module) { - case DP_CORE_PM: return "DP_CORE_PM"; - case DP_CTRL_PM: return "DP_CTRL_PM"; - case DP_STREAM_PM: return "DP_STREAM_PM"; - case DP_PHY_PM: return "DP_PHY_PM"; - default: return "???"; - } -} - -/** - * struct dp_display_data - display related device tree data. - * - * @ctrl_node: referece to controller device - * @phy_node: reference to phy device - * @is_active: is the controller currently active - * @name: name of the display - * @display_type: type of the display - */ -struct dp_display_data { - struct device_node *ctrl_node; - struct device_node *phy_node; - bool is_active; - const char *name; - const char *display_type; -}; - -/** - * struct dp_ctrl_resource - controller's IO related data - * - * @dp_controller: Display Port controller mapped memory address - * @phy_io: phy's mapped memory address - */ -struct dp_io { - struct dss_io_data dp_controller; - struct phy *phy; - union phy_configure_opts phy_opts; -}; - -/** - * struct dp_pinctrl - DP's pin control - * - * @pin: pin-controller's instance - * @state_active: active state pin control - * @state_hpd_active: hpd active state pin control - * @state_suspend: suspend state pin control - */ -struct dp_pinctrl { - struct pinctrl *pin; - struct pinctrl_state *state_active; - struct pinctrl_state *state_hpd_active; - struct pinctrl_state *state_suspend; -}; - -/* Regulators for DP devices */ -struct dp_reg_entry { - char name[32]; - int enable_load; - int disable_load; -}; - -struct dss_module_power { - unsigned int num_clk; - struct clk_bulk_data *clocks; -}; - -/** - * struct dp_parser - DP parser's data exposed to clients - * - * @pdev: platform data of the client - * @mp: gpio, regulator and clock related data - * @pinctrl: pin-control related data - * @disp_data: controller's display related data - * @parse: function to be called by client to parse device tree. - */ -struct dp_parser { - struct platform_device *pdev; - struct dss_module_power mp[DP_MAX_PM]; - struct dp_pinctrl pinctrl; - struct dp_io io; - struct dp_display_data disp_data; - u32 max_dp_lanes; - u32 max_dp_link_rate; - struct drm_bridge *next_bridge; - - int (*parse)(struct dp_parser *parser); -}; - -/** - * dp_parser_get() - get the DP's device tree parser module - * - * @pdev: platform data of the client - * return: pointer to dp_parser structure. - * - * This function provides client capability to parse the - * device tree and populate the data structures. The data - * related to clock, regulators, pin-control and other - * can be parsed using this module. - */ -struct dp_parser *dp_parser_get(struct platform_device *pdev); - -/** - * devm_dp_parser_find_next_bridge() - find an additional bridge to DP - * - * @dev: device to tie bridge lifetime to - * @parser: dp_parser data from client - * - * This function is used to find any additional bridge attached to - * the DP controller. The eDP interface requires a panel bridge. - * - * Return: 0 if able to get the bridge, otherwise negative errno for failure. - */ -int devm_dp_parser_find_next_bridge(struct device *dev, struct dp_parser *parser); - -#endif diff --git a/drivers/gpu/drm/msm/dp/dp_power.c b/drivers/gpu/drm/msm/dp/dp_power.c deleted file mode 100644 index c4843dd69f47..000000000000 --- a/drivers/gpu/drm/msm/dp/dp_power.c +++ /dev/null @@ -1,183 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. - */ - -#define pr_fmt(fmt) "[drm-dp] %s: " fmt, __func__ - -#include <linux/clk.h> -#include <linux/clk-provider.h> -#include <linux/regulator/consumer.h> -#include <linux/pm_opp.h> -#include "dp_power.h" -#include "msm_drv.h" - -struct dp_power_private { - struct dp_parser *parser; - struct device *dev; - struct drm_device *drm_dev; - struct clk *link_clk_src; - struct clk *pixel_provider; - struct clk *link_provider; - - struct dp_power dp_power; -}; - -static int dp_power_clk_init(struct dp_power_private *power) -{ - int rc = 0; - struct dss_module_power *core, *ctrl, *stream; - struct device *dev = power->dev; - - core = &power->parser->mp[DP_CORE_PM]; - ctrl = &power->parser->mp[DP_CTRL_PM]; - stream = &power->parser->mp[DP_STREAM_PM]; - - rc = devm_clk_bulk_get(dev, core->num_clk, core->clocks); - if (rc) - return rc; - - rc = devm_clk_bulk_get(dev, ctrl->num_clk, ctrl->clocks); - if (rc) - return -ENODEV; - - rc = devm_clk_bulk_get(dev, stream->num_clk, stream->clocks); - if (rc) - return -ENODEV; - - return 0; -} - -int dp_power_clk_status(struct dp_power *dp_power, enum dp_pm_type pm_type) -{ - struct dp_power_private *power; - - power = container_of(dp_power, struct dp_power_private, dp_power); - - drm_dbg_dp(power->drm_dev, - "core_clk_on=%d link_clk_on=%d stream_clk_on=%d\n", - dp_power->core_clks_on, dp_power->link_clks_on, dp_power->stream_clks_on); - - if (pm_type == DP_CORE_PM) - return dp_power->core_clks_on; - - if (pm_type == DP_CTRL_PM) - return dp_power->link_clks_on; - - if (pm_type == DP_STREAM_PM) - return dp_power->stream_clks_on; - - return 0; -} - -int dp_power_clk_enable(struct dp_power *dp_power, - enum dp_pm_type pm_type, bool enable) -{ - int rc = 0; - struct dp_power_private *power; - struct dss_module_power *mp; - - power = container_of(dp_power, struct dp_power_private, dp_power); - - if (pm_type != DP_CORE_PM && pm_type != DP_CTRL_PM && - pm_type != DP_STREAM_PM) { - DRM_ERROR("unsupported power module: %s\n", - dp_parser_pm_name(pm_type)); - return -EINVAL; - } - - if (enable) { - if (pm_type == DP_CORE_PM && dp_power->core_clks_on) { - drm_dbg_dp(power->drm_dev, - "core clks already enabled\n"); - return 0; - } - - if (pm_type == DP_CTRL_PM && dp_power->link_clks_on) { - drm_dbg_dp(power->drm_dev, - "links clks already enabled\n"); - return 0; - } - - if (pm_type == DP_STREAM_PM && dp_power->stream_clks_on) { - drm_dbg_dp(power->drm_dev, - "pixel clks already enabled\n"); - return 0; - } - - if ((pm_type == DP_CTRL_PM) && (!dp_power->core_clks_on)) { - drm_dbg_dp(power->drm_dev, - "Enable core clks before link clks\n"); - mp = &power->parser->mp[DP_CORE_PM]; - - rc = clk_bulk_prepare_enable(mp->num_clk, mp->clocks); - if (rc) - return rc; - - dp_power->core_clks_on = true; - } - } - - mp = &power->parser->mp[pm_type]; - if (enable) { - rc = clk_bulk_prepare_enable(mp->num_clk, mp->clocks); - if (rc) - return rc; - } else { - clk_bulk_disable_unprepare(mp->num_clk, mp->clocks); - } - - if (pm_type == DP_CORE_PM) - dp_power->core_clks_on = enable; - else if (pm_type == DP_STREAM_PM) - dp_power->stream_clks_on = enable; - else - dp_power->link_clks_on = enable; - - drm_dbg_dp(power->drm_dev, "%s clocks for %s\n", - enable ? "enable" : "disable", - dp_parser_pm_name(pm_type)); - drm_dbg_dp(power->drm_dev, - "strem_clks:%s link_clks:%s core_clks:%s\n", - dp_power->stream_clks_on ? "on" : "off", - dp_power->link_clks_on ? "on" : "off", - dp_power->core_clks_on ? "on" : "off"); - - return 0; -} - -int dp_power_client_init(struct dp_power *dp_power) -{ - struct dp_power_private *power; - - power = container_of(dp_power, struct dp_power_private, dp_power); - - return dp_power_clk_init(power); -} - -int dp_power_init(struct dp_power *dp_power) -{ - return dp_power_clk_enable(dp_power, DP_CORE_PM, true); -} - -int dp_power_deinit(struct dp_power *dp_power) -{ - return dp_power_clk_enable(dp_power, DP_CORE_PM, false); -} - -struct dp_power *dp_power_get(struct device *dev, struct dp_parser *parser) -{ - struct dp_power_private *power; - struct dp_power *dp_power; - - power = devm_kzalloc(dev, sizeof(*power), GFP_KERNEL); - if (!power) - return ERR_PTR(-ENOMEM); - - power->parser = parser; - power->dev = dev; - - dp_power = &power->dp_power; - - return dp_power; -} diff --git a/drivers/gpu/drm/msm/dp/dp_power.h b/drivers/gpu/drm/msm/dp/dp_power.h deleted file mode 100644 index 55ada51edb57..000000000000 --- a/drivers/gpu/drm/msm/dp/dp_power.h +++ /dev/null @@ -1,95 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. - */ - -#ifndef _DP_POWER_H_ -#define _DP_POWER_H_ - -#include "dp_parser.h" - -/** - * sruct dp_power - DisplayPort's power related data - * - * @init: initializes the regulators/core clocks/GPIOs/pinctrl - * @deinit: turns off the regulators/core clocks/GPIOs/pinctrl - * @clk_enable: enable/disable the DP clocks - * @set_pixel_clk_parent: set the parent of DP pixel clock - */ -struct dp_power { - bool core_clks_on; - bool link_clks_on; - bool stream_clks_on; -}; - -/** - * dp_power_init() - enable power supplies for display controller - * - * @power: instance of power module - * return: 0 if success or error if failure. - * - * This API will turn on the regulators and configures gpio's - * aux/hpd. - */ -int dp_power_init(struct dp_power *power); - -/** - * dp_power_deinit() - turn off regulators and gpios. - * - * @power: instance of power module - * return: 0 for success - * - * This API turns off power and regulators. - */ -int dp_power_deinit(struct dp_power *power); - -/** - * dp_power_clk_status() - display controller clocks status - * - * @power: instance of power module - * @pm_type: type of pm, core/ctrl/phy - * return: status of power clocks - * - * This API return status of DP clocks - */ - -int dp_power_clk_status(struct dp_power *dp_power, enum dp_pm_type pm_type); - -/** - * dp_power_clk_enable() - enable display controller clocks - * - * @power: instance of power module - * @pm_type: type of pm, core/ctrl/phy - * @enable: enables or disables - * return: pointer to allocated power module data - * - * This API will call setrate and enable for DP clocks - */ - -int dp_power_clk_enable(struct dp_power *power, enum dp_pm_type pm_type, - bool enable); - -/** - * dp_power_client_init() - initialize clock and regulator modules - * - * @power: instance of power module - * return: 0 for success, error for failure. - * - * This API will configure the DisplayPort's clocks and regulator - * modules. - */ -int dp_power_client_init(struct dp_power *power); - -/** - * dp_power_get() - configure and get the DisplayPort power module data - * - * @parser: instance of parser module - * return: pointer to allocated power module data - * - * This API will configure the DisplayPort's power module and provides - * methods to be called by the client to configure the power related - * modules. - */ -struct dp_power *dp_power_get(struct device *dev, struct dp_parser *parser); - -#endif /* _DP_POWER_H_ */ diff --git a/drivers/gpu/drm/msm/dp/dp_reg.h b/drivers/gpu/drm/msm/dp/dp_reg.h index 78785ed4b40c..3835c7f5cb98 100644 --- a/drivers/gpu/drm/msm/dp/dp_reg.h +++ b/drivers/gpu/drm/msm/dp/dp_reg.h @@ -6,6 +6,9 @@ #ifndef _DP_REG_H_ #define _DP_REG_H_ +#include <linux/bitfield.h> +#include <linux/bits.h> + /* DP_TX Registers */ #define REG_DP_HW_VERSION (0x00000000) @@ -102,6 +105,9 @@ #define DP_MAINLINK_CTRL_ENABLE (0x00000001) #define DP_MAINLINK_CTRL_RESET (0x00000002) #define DP_MAINLINK_CTRL_SW_BYPASS_SCRAMBLER (0x00000010) +#define DP_MAINLINK_CTRL_FLUSH_MODE_MASK GENMASK(24, 23) +#define DP_MAINLINK_FLUSH_MODE_UPDATE_SDP FIELD_PREP(DP_MAINLINK_CTRL_FLUSH_MODE_MASK, 1) +#define DP_MAINLINK_FLUSH_MODE_SDE_PERIPH_UPDATE FIELD_PREP(DP_MAINLINK_CTRL_FLUSH_MODE_MASK, 3) #define DP_MAINLINK_FB_BOUNDARY_SEL (0x02000000) #define REG_DP_STATE_CTRL (0x00000004) @@ -142,6 +148,7 @@ #define DP_MISC0_SYNCHRONOUS_CLK (0x00000001) #define DP_MISC0_COLORIMETRY_CFG_SHIFT (0x00000001) #define DP_MISC0_TEST_BITS_DEPTH_SHIFT (0x00000005) +#define DP_MISC1_VSC_SDP (0x00004000) #define DP_MISC0_COLORIMERY_CFG_LEGACY_RGB (0) #define DP_MISC0_COLORIMERY_CFG_CEA_RGB (0x04) @@ -204,9 +211,11 @@ #define MMSS_DP_AUDIO_CTRL_RESET (0x00000214) #define MMSS_DP_SDP_CFG (0x00000228) +#define GEN0_SDP_EN (0x00020000) #define MMSS_DP_SDP_CFG2 (0x0000022C) #define MMSS_DP_AUDIO_TIMESTAMP_0 (0x00000230) #define MMSS_DP_AUDIO_TIMESTAMP_1 (0x00000234) +#define GENERIC0_SDPSIZE_VALID (0x00010000) #define MMSS_DP_AUDIO_STREAM_0 (0x00000240) #define MMSS_DP_AUDIO_STREAM_1 (0x00000244) diff --git a/drivers/gpu/drm/msm/dp/dp_utils.c b/drivers/gpu/drm/msm/dp/dp_utils.c new file mode 100644 index 000000000000..da9207caf72d --- /dev/null +++ b/drivers/gpu/drm/msm/dp/dp_utils.c @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2024, The Linux Foundation. All rights reserved. + */ + +#include <linux/types.h> + +#include "dp_utils.h" + +#define DP_SDP_HEADER_SIZE 8 + +u8 dp_utils_get_g0_value(u8 data) +{ + u8 c[4]; + u8 g[4]; + u8 ret_data = 0; + u8 i; + + for (i = 0; i < 4; i++) + c[i] = (data >> i) & 0x01; + + g[0] = c[3]; + g[1] = c[0] ^ c[3]; + g[2] = c[1]; + g[3] = c[2]; + + for (i = 0; i < 4; i++) + ret_data = ((g[i] & 0x01) << i) | ret_data; + + return ret_data; +} + +u8 dp_utils_get_g1_value(u8 data) +{ + u8 c[4]; + u8 g[4]; + u8 ret_data = 0; + u8 i; + + for (i = 0; i < 4; i++) + c[i] = (data >> i) & 0x01; + + g[0] = c[0] ^ c[3]; + g[1] = c[0] ^ c[1] ^ c[3]; + g[2] = c[1] ^ c[2]; + g[3] = c[2] ^ c[3]; + + for (i = 0; i < 4; i++) + ret_data = ((g[i] & 0x01) << i) | ret_data; + + return ret_data; +} + +u8 dp_utils_calculate_parity(u32 data) +{ + u8 x0 = 0; + u8 x1 = 0; + u8 ci = 0; + u8 iData = 0; + u8 i = 0; + u8 parity_byte; + u8 num_byte = (data & 0xFF00) > 0 ? 8 : 2; + + for (i = 0; i < num_byte; i++) { + iData = (data >> i * 4) & 0xF; + + ci = iData ^ x1; + x1 = x0 ^ dp_utils_get_g1_value(ci); + x0 = dp_utils_get_g0_value(ci); + } + + parity_byte = x1 | (x0 << 4); + + return parity_byte; +} + +ssize_t dp_utils_pack_sdp_header(struct dp_sdp_header *sdp_header, u32 *header_buff) +{ + size_t length; + + length = sizeof(header_buff); + if (length < DP_SDP_HEADER_SIZE) + return -ENOSPC; + + header_buff[0] = FIELD_PREP(HEADER_0_MASK, sdp_header->HB0) | + FIELD_PREP(PARITY_0_MASK, dp_utils_calculate_parity(sdp_header->HB0)) | + FIELD_PREP(HEADER_1_MASK, sdp_header->HB1) | + FIELD_PREP(PARITY_1_MASK, dp_utils_calculate_parity(sdp_header->HB1)); + + header_buff[1] = FIELD_PREP(HEADER_2_MASK, sdp_header->HB2) | + FIELD_PREP(PARITY_2_MASK, dp_utils_calculate_parity(sdp_header->HB2)) | + FIELD_PREP(HEADER_3_MASK, sdp_header->HB3) | + FIELD_PREP(PARITY_3_MASK, dp_utils_calculate_parity(sdp_header->HB3)); + + return length; +} diff --git a/drivers/gpu/drm/msm/dp/dp_utils.h b/drivers/gpu/drm/msm/dp/dp_utils.h new file mode 100644 index 000000000000..7c056d9798dc --- /dev/null +++ b/drivers/gpu/drm/msm/dp/dp_utils.h @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2024, The Linux Foundation. All rights reserved. + */ + +#ifndef _DP_UTILS_H_ +#define _DP_UTILS_H_ + +#include <linux/bitfield.h> +#include <linux/bits.h> +#include <drm/display/drm_dp_helper.h> + +#define HEADER_BYTE_0_BIT 0 +#define PARITY_BYTE_0_BIT 8 +#define HEADER_BYTE_1_BIT 16 +#define PARITY_BYTE_1_BIT 24 +#define HEADER_BYTE_2_BIT 0 +#define PARITY_BYTE_2_BIT 8 +#define HEADER_BYTE_3_BIT 16 +#define PARITY_BYTE_3_BIT 24 + +#define HEADER_0_MASK GENMASK(7, 0) +#define PARITY_0_MASK GENMASK(15, 8) +#define HEADER_1_MASK GENMASK(23, 16) +#define PARITY_1_MASK GENMASK(31, 24) +#define HEADER_2_MASK GENMASK(7, 0) +#define PARITY_2_MASK GENMASK(15, 8) +#define HEADER_3_MASK GENMASK(23, 16) +#define PARITY_3_MASK GENMASK(31, 24) + +u8 dp_utils_get_g0_value(u8 data); +u8 dp_utils_get_g1_value(u8 data); +u8 dp_utils_calculate_parity(u32 data); +ssize_t dp_utils_pack_sdp_header(struct dp_sdp_header *sdp_header, u32 *header_buff); + +#endif /* _DP_UTILS_H_ */ diff --git a/drivers/gpu/drm/msm/dsi/dsi.c b/drivers/gpu/drm/msm/dsi/dsi.c index c6bd7bf15605..37c4c07005fe 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.c +++ b/drivers/gpu/drm/msm/dsi/dsi.c @@ -216,6 +216,7 @@ void __exit msm_dsi_unregister(void) int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, struct drm_encoder *encoder) { + struct drm_bridge *bridge; int ret; msm_dsi->dev = dev; @@ -235,15 +236,14 @@ int msm_dsi_modeset_init(struct msm_dsi *msm_dsi, struct drm_device *dev, return 0; } - msm_dsi->encoder = encoder; - - ret = msm_dsi_manager_bridge_init(msm_dsi); - if (ret) { + bridge = msm_dsi_manager_bridge_init(msm_dsi, encoder); + if (IS_ERR(bridge)) { + ret = PTR_ERR(bridge); DRM_DEV_ERROR(dev->dev, "failed to create dsi bridge: %d\n", ret); return ret; } - ret = msm_dsi_manager_ext_bridge_init(msm_dsi->id); + ret = msm_dsi_manager_ext_bridge_init(msm_dsi->id, bridge); if (ret) { DRM_DEV_ERROR(dev->dev, "failed to create dsi connector: %d\n", ret); diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 28379b1af63f..2ad9a842c678 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -35,41 +35,25 @@ struct msm_dsi { struct drm_device *dev; struct platform_device *pdev; - /* internal dsi bridge attached to MDP interface */ - struct drm_bridge *bridge; - struct mipi_dsi_host *host; struct msm_dsi_phy *phy; - /* - * external_bridge connected to dsi bridge output - */ - struct drm_bridge *external_bridge; - struct device *phy_dev; bool phy_enabled; - /* the encoder we are hooked to (outside of dsi block) */ - struct drm_encoder *encoder; - int id; }; /* dsi manager */ -int msm_dsi_manager_bridge_init(struct msm_dsi *msm_dsi); -int msm_dsi_manager_ext_bridge_init(u8 id); +struct drm_bridge *msm_dsi_manager_bridge_init(struct msm_dsi *msm_dsi, + struct drm_encoder *encoder); +int msm_dsi_manager_ext_bridge_init(u8 id, struct drm_bridge *int_bridge); int msm_dsi_manager_cmd_xfer(int id, const struct mipi_dsi_msg *msg); bool msm_dsi_manager_cmd_xfer_trigger(int id, u32 dma_base, u32 len); int msm_dsi_manager_register(struct msm_dsi *msm_dsi); void msm_dsi_manager_unregister(struct msm_dsi *msm_dsi); void msm_dsi_manager_tpg_enable(void); -/* msm dsi */ -static inline bool msm_dsi_device_connected(struct msm_dsi *msm_dsi) -{ - return msm_dsi->external_bridge; -} - /* dsi host */ struct msm_dsi_host; int msm_dsi_host_xfer_prepare(struct mipi_dsi_host *host, diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index deeecdfd6c4e..9d86a6aca6f2 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -183,16 +183,6 @@ struct msm_dsi_host { int irq; }; -static u32 dsi_get_bpp(const enum mipi_dsi_pixel_format fmt) -{ - switch (fmt) { - case MIPI_DSI_FMT_RGB565: return 16; - case MIPI_DSI_FMT_RGB666_PACKED: return 18; - case MIPI_DSI_FMT_RGB666: - case MIPI_DSI_FMT_RGB888: - default: return 24; - } -} static inline u32 dsi_read(struct msm_dsi_host *msm_host, u32 reg) { @@ -529,6 +519,25 @@ void dsi_link_clk_disable_v2(struct msm_dsi_host *msm_host) clk_disable_unprepare(msm_host->byte_clk); } +/** + * dsi_adjust_pclk_for_compression() - Adjust the pclk rate for compression case + * @mode: The selected mode for the DSI output + * @dsc: DRM DSC configuration for this DSI output + * + * Adjust the pclk rate by calculating a new hdisplay proportional to + * the compression ratio such that: + * new_hdisplay = old_hdisplay * compressed_bpp / uncompressed_bpp + * + * Porches do not need to be adjusted: + * - For VIDEO mode they are not compressed by DSC and are passed as is. + * - For CMD mode there are no actual porches. Instead these fields + * currently represent the overhead to the image data transfer. As such, they + * are calculated for the final mode parameters (after the compression) and + * are not to be adjusted too. + * + * FIXME: Reconsider this if/when CMD mode handling is rewritten to use + * transfer time and data overhead as a starting point of the calculations. + */ static unsigned long dsi_adjust_pclk_for_compression(const struct drm_display_mode *mode, const struct drm_dsc_config *dsc) { @@ -567,7 +576,7 @@ unsigned long dsi_byte_clk_get_rate(struct mipi_dsi_host *host, bool is_bonded_d { struct msm_dsi_host *msm_host = to_msm_dsi_host(host); u8 lanes = msm_host->lanes; - u32 bpp = dsi_get_bpp(msm_host->format); + u32 bpp = mipi_dsi_pixel_format_to_bpp(msm_host->format); unsigned long pclk_rate = dsi_get_pclk_rate(mode, msm_host->dsc, is_bonded_dsi); unsigned long pclk_bpp; @@ -610,7 +619,7 @@ int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi) int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi) { - u32 bpp = dsi_get_bpp(msm_host->format); + u32 bpp = mipi_dsi_pixel_format_to_bpp(msm_host->format); unsigned int esc_mhz, esc_div; unsigned long byte_mhz; @@ -951,8 +960,18 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) if (ret) return; - /* Divide the display by 3 but keep back/font porch and - * pulse width same + /* + * DPU sends 3 bytes per pclk cycle to DSI. If widebus is + * enabled, bus width is extended to 6 bytes. + * + * Calculate the number of pclks needed to transmit one line of + * the compressed data. + + * The back/font porch and pulse width are kept intact. For + * VIDEO mode they represent timing parameters rather than + * actual data transfer, see the documentation for + * dsi_adjust_pclk_for_compression(). For CMD mode they are + * unused anyway. */ h_total -= hdisplay; if (wide_bus_enabled && !(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO)) @@ -993,7 +1012,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) /* image data and 1 byte write_memory_start cmd */ if (!msm_host->dsc) - wc = hdisplay * dsi_get_bpp(msm_host->format) / 8 + 1; + wc = hdisplay * mipi_dsi_pixel_format_to_bpp(msm_host->format) / 8 + 1; else /* * When DSC is enabled, WC = slice_chunk_size * slice_per_pkt + 1. @@ -1413,7 +1432,7 @@ static int dsi_cmds2buf_tx(struct msm_dsi_host *msm_host, { int len, ret; int bllp_len = msm_host->mode->hdisplay * - dsi_get_bpp(msm_host->format) / 8; + mipi_dsi_pixel_format_to_bpp(msm_host->format) / 8; len = dsi_cmd_dma_add(msm_host, msg); if (len < 0) { diff --git a/drivers/gpu/drm/msm/dsi/dsi_manager.c b/drivers/gpu/drm/msm/dsi/dsi_manager.c index 896f369fdd53..af2a287cb3bd 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_manager.c +++ b/drivers/gpu/drm/msm/dsi/dsi_manager.c @@ -198,36 +198,6 @@ static int dsi_mgr_bridge_get_id(struct drm_bridge *bridge) return dsi_bridge->id; } -static void msm_dsi_manager_set_split_display(u8 id) -{ - struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); - struct msm_dsi *other_dsi = dsi_mgr_get_other_dsi(id); - struct msm_drm_private *priv = msm_dsi->dev->dev_private; - struct msm_kms *kms = priv->kms; - struct msm_dsi *master_dsi, *slave_dsi; - - if (IS_BONDED_DSI() && !IS_MASTER_DSI_LINK(id)) { - master_dsi = other_dsi; - slave_dsi = msm_dsi; - } else { - master_dsi = msm_dsi; - slave_dsi = other_dsi; - } - - if (!msm_dsi->external_bridge || !IS_BONDED_DSI()) - return; - - /* - * Set split display info to kms once bonded DSI panel is connected to - * both hosts. - */ - if (other_dsi && other_dsi->external_bridge && kms->funcs->set_split_display) { - kms->funcs->set_split_display(kms, master_dsi->encoder, - slave_dsi->encoder, - msm_dsi_is_cmd_mode(msm_dsi)); - } -} - static int dsi_mgr_bridge_power_on(struct drm_bridge *bridge) { int id = dsi_mgr_bridge_get_id(bridge); @@ -305,8 +275,6 @@ static void dsi_mgr_bridge_pre_enable(struct drm_bridge *bridge) int ret; DBG("id=%d", id); - if (!msm_dsi_device_connected(msm_dsi)) - return; /* Do nothing with the host if it is slave-DSI in case of bonded DSI */ if (is_bonded_dsi && !IS_MASTER_DSI_LINK(id)) @@ -364,9 +332,6 @@ static void dsi_mgr_bridge_post_disable(struct drm_bridge *bridge) DBG("id=%d", id); - if (!msm_dsi_device_connected(msm_dsi)) - return; - /* * Do nothing with the host if it is slave-DSI in case of bonded DSI. * It is safe to call dsi_mgr_phy_disable() here because a single PHY @@ -466,55 +431,48 @@ static const struct drm_bridge_funcs dsi_mgr_bridge_funcs = { }; /* initialize bridge */ -int msm_dsi_manager_bridge_init(struct msm_dsi *msm_dsi) +struct drm_bridge *msm_dsi_manager_bridge_init(struct msm_dsi *msm_dsi, + struct drm_encoder *encoder) { - struct drm_bridge *bridge = NULL; + struct drm_bridge *bridge; struct dsi_bridge *dsi_bridge; - struct drm_encoder *encoder; int ret; dsi_bridge = devm_kzalloc(msm_dsi->dev->dev, sizeof(*dsi_bridge), GFP_KERNEL); if (!dsi_bridge) - return -ENOMEM; + return ERR_PTR(-ENOMEM); dsi_bridge->id = msm_dsi->id; - encoder = msm_dsi->encoder; - bridge = &dsi_bridge->base; bridge->funcs = &dsi_mgr_bridge_funcs; ret = devm_drm_bridge_add(msm_dsi->dev->dev, bridge); if (ret) - return ret; + return ERR_PTR(ret); ret = drm_bridge_attach(encoder, bridge, NULL, 0); if (ret) - return ret; - - msm_dsi->bridge = bridge; + return ERR_PTR(ret); - return 0; + return bridge; } -int msm_dsi_manager_ext_bridge_init(u8 id) +int msm_dsi_manager_ext_bridge_init(u8 id, struct drm_bridge *int_bridge) { struct msm_dsi *msm_dsi = dsi_mgr_get_dsi(id); struct drm_device *dev = msm_dsi->dev; struct drm_encoder *encoder; - struct drm_bridge *int_bridge, *ext_bridge; + struct drm_bridge *ext_bridge; int ret; - int_bridge = msm_dsi->bridge; ext_bridge = devm_drm_of_get_bridge(&msm_dsi->pdev->dev, msm_dsi->pdev->dev.of_node, 1, 0); if (IS_ERR(ext_bridge)) return PTR_ERR(ext_bridge); - msm_dsi->external_bridge = ext_bridge; - - encoder = msm_dsi->encoder; + encoder = int_bridge->encoder; /* * Try first to create the bridge without it creating its own @@ -546,9 +504,6 @@ int msm_dsi_manager_ext_bridge_init(u8 id) return ret; } - /* The pipeline is ready, ping encoders if necessary */ - msm_dsi_manager_set_split_display(id); - return 0; } diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c index f5e01471b0b0..4a5b5112227f 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_bridge.c @@ -236,24 +236,33 @@ static void msm_hdmi_bridge_mode_set(struct drm_bridge *bridge, msm_hdmi_audio_update(hdmi); } -static struct edid *msm_hdmi_bridge_get_edid(struct drm_bridge *bridge, - struct drm_connector *connector) +static const struct drm_edid *msm_hdmi_bridge_edid_read(struct drm_bridge *bridge, + struct drm_connector *connector) { struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge); struct hdmi *hdmi = hdmi_bridge->hdmi; - struct edid *edid; + const struct drm_edid *drm_edid; uint32_t hdmi_ctrl; hdmi_ctrl = hdmi_read(hdmi, REG_HDMI_CTRL); hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl | HDMI_CTRL_ENABLE); - edid = drm_get_edid(connector, hdmi->i2c); + drm_edid = drm_edid_read_ddc(connector, hdmi->i2c); hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl); - hdmi->hdmi_mode = drm_detect_hdmi_monitor(edid); + if (drm_edid) { + /* + * FIXME: This should use connector->display_info.is_hdmi from a + * path that has read the EDID and called + * drm_edid_connector_update(). + */ + const struct edid *edid = drm_edid_raw(drm_edid); - return edid; + hdmi->hdmi_mode = drm_detect_hdmi_monitor(edid); + } + + return drm_edid; } static enum drm_mode_status msm_hdmi_bridge_mode_valid(struct drm_bridge *bridge, @@ -290,12 +299,12 @@ static enum drm_mode_status msm_hdmi_bridge_mode_valid(struct drm_bridge *bridge } static const struct drm_bridge_funcs msm_hdmi_bridge_funcs = { - .pre_enable = msm_hdmi_bridge_pre_enable, - .post_disable = msm_hdmi_bridge_post_disable, - .mode_set = msm_hdmi_bridge_mode_set, - .mode_valid = msm_hdmi_bridge_mode_valid, - .get_edid = msm_hdmi_bridge_get_edid, - .detect = msm_hdmi_bridge_detect, + .pre_enable = msm_hdmi_bridge_pre_enable, + .post_disable = msm_hdmi_bridge_post_disable, + .mode_set = msm_hdmi_bridge_mode_set, + .mode_valid = msm_hdmi_bridge_mode_valid, + .edid_read = msm_hdmi_bridge_edid_read, + .detect = msm_hdmi_bridge_detect, }; static void diff --git a/drivers/gpu/drm/msm/msm_drv.c b/drivers/gpu/drm/msm/msm_drv.c index 50b65ffc24b1..97790faffd23 100644 --- a/drivers/gpu/drm/msm/msm_drv.c +++ b/drivers/gpu/drm/msm/msm_drv.c @@ -969,6 +969,39 @@ static int add_components_mdp(struct device *master_dev, return 0; } +#if !IS_REACHABLE(CONFIG_DRM_MSM_MDP5) || !IS_REACHABLE(CONFIG_DRM_MSM_DPU) +bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver) +{ + /* If just a single driver is enabled, use it no matter what */ + return true; +} +#else + +static bool prefer_mdp5 = true; +MODULE_PARM_DESC(prefer_mdp5, "Select whether MDP5 or DPU driver should be preferred"); +module_param(prefer_mdp5, bool, 0444); + +/* list all platforms supported by both mdp5 and dpu drivers */ +static const char *const msm_mdp5_dpu_migration[] = { + "qcom,sdm630-mdp5", + "qcom,sdm660-mdp5", + NULL, +}; + +bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver) +{ + /* If it is not an MDP5 device, do not try MDP5 driver */ + if (!of_device_is_compatible(dev->of_node, "qcom,mdp5")) + return dpu_driver; + + /* If it is not in the migration list, use MDP5 */ + if (!of_device_compatible_match(dev->of_node, msm_mdp5_dpu_migration)) + return !dpu_driver; + + return prefer_mdp5 ? !dpu_driver : dpu_driver; +} +#endif + /* * We don't know what's the best binding to link the gpu with the drm device. * Fow now, we just hunt for all the possible gpus that we support, and add them diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 16a7cbc0b7dd..65f213660452 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -75,16 +75,6 @@ enum msm_dsi_controller { #define MAX_H_TILES_PER_DISPLAY 2 /** - * enum msm_event_wait - type of HW events to wait for - * @MSM_ENC_COMMIT_DONE - wait for the driver to flush the registers to HW - * @MSM_ENC_TX_COMPLETE - wait for the HW to transfer the frame to panel - */ -enum msm_event_wait { - MSM_ENC_COMMIT_DONE = 0, - MSM_ENC_TX_COMPLETE, -}; - -/** * struct msm_display_topology - defines a display topology pipeline * @num_lm: number of layer mixers used * @num_intf: number of interfaces the panel is mounted on @@ -385,9 +375,12 @@ static inline struct drm_dsc_config *msm_dsi_get_dsc_config(struct msm_dsi *msm_ int __init msm_dp_register(void); void __exit msm_dp_unregister(void); int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, - struct drm_encoder *encoder); + struct drm_encoder *encoder, bool yuv_supported); void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm_dp *dp_display); - +bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display, + const struct drm_display_mode *mode); +bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, + const struct drm_display_mode *mode); bool msm_dp_wide_bus_available(const struct msm_dp *dp_display); #else @@ -400,7 +393,8 @@ static inline void __exit msm_dp_unregister(void) } static inline int msm_dp_modeset_init(struct msm_dp *dp_display, struct drm_device *dev, - struct drm_encoder *encoder) + struct drm_encoder *encoder, + bool yuv_supported) { return -EINVAL; } @@ -409,6 +403,18 @@ static inline void msm_dp_snapshot(struct msm_disp_state *disp_state, struct msm { } +static inline bool msm_dp_is_yuv_420_enabled(const struct msm_dp *dp_display, + const struct drm_display_mode *mode) +{ + return false; +} + +static inline bool msm_dp_needs_periph_flush(const struct msm_dp *dp_display, + const struct drm_display_mode *mode) +{ + return false; +} + static inline bool msm_dp_wide_bus_available(const struct msm_dp *dp_display) { return false; @@ -476,6 +482,9 @@ void __iomem *msm_ioremap(struct platform_device *pdev, const char *name); void __iomem *msm_ioremap_size(struct platform_device *pdev, const char *name, phys_addr_t *size); void __iomem *msm_ioremap_quiet(struct platform_device *pdev, const char *name); +void __iomem *msm_ioremap_mdss(struct platform_device *mdss_pdev, + struct platform_device *dev, + const char *name); struct icc_path *msm_icc_get(struct device *dev, const char *name); @@ -560,5 +569,6 @@ int msm_drv_probe(struct device *dev, struct msm_kms *kms); void msm_kms_shutdown(struct platform_device *pdev); +bool msm_disp_drv_should_bind(struct device *dev, bool dpu_driver); #endif /* __MSM_DRV_H__ */ diff --git a/drivers/gpu/drm/msm/msm_io_utils.c b/drivers/gpu/drm/msm/msm_io_utils.c index 59d2788c4510..afedd61c3e28 100644 --- a/drivers/gpu/drm/msm/msm_io_utils.c +++ b/drivers/gpu/drm/msm/msm_io_utils.c @@ -50,6 +50,19 @@ struct clk *msm_clk_get(struct platform_device *pdev, const char *name) return clk; } +void __iomem *msm_ioremap_mdss(struct platform_device *mdss_pdev, + struct platform_device *pdev, + const char *name) +{ + struct resource *res; + + res = platform_get_resource_byname(mdss_pdev, IORESOURCE_MEM, name); + if (!res) + return ERR_PTR(-EINVAL); + + return devm_ioremap_resource(&pdev->dev, res); +} + static void __iomem *_msm_ioremap(struct platform_device *pdev, const char *name, bool quiet, phys_addr_t *psize) { diff --git a/drivers/gpu/drm/msm/msm_kms.h b/drivers/gpu/drm/msm/msm_kms.h index 44aa435d68ce..0641f6111b93 100644 --- a/drivers/gpu/drm/msm/msm_kms.h +++ b/drivers/gpu/drm/msm/msm_kms.h @@ -105,10 +105,6 @@ struct msm_kms_funcs { /* misc: */ long (*round_pixclk)(struct msm_kms *kms, unsigned long rate, struct drm_encoder *encoder); - int (*set_split_display)(struct msm_kms *kms, - struct drm_encoder *encoder, - struct drm_encoder *slave_encoder, - bool is_cmd_mode); /* cleanup: */ void (*destroy)(struct msm_kms *kms); diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index 35423d10aafa..fab6ad4e5107 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -3,6 +3,7 @@ * Copyright (c) 2018, The Linux Foundation */ +#include <linux/bitfield.h> #include <linux/clk.h> #include <linux/delay.h> #include <linux/interconnect.h> @@ -213,6 +214,49 @@ static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss *msm_mdss) } } +#define MDSS_HW_MAJ_MIN GENMASK(31, 16) + +#define MDSS_HW_MSM8996 0x1007 +#define MDSS_HW_MSM8937 0x100e +#define MDSS_HW_MSM8953 0x1010 +#define MDSS_HW_MSM8998 0x3000 +#define MDSS_HW_SDM660 0x3002 +#define MDSS_HW_SDM630 0x3003 + +/* + * MDP5 platforms use generic qcom,mdp5 compat string, so we have to generate this data + */ +static const struct msm_mdss_data *msm_mdss_generate_mdp5_mdss_data(struct msm_mdss *mdss) +{ + struct msm_mdss_data *data; + u32 hw_rev; + + data = devm_kzalloc(mdss->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return NULL; + + hw_rev = readl_relaxed(mdss->mmio + HW_REV); + hw_rev = FIELD_GET(MDSS_HW_MAJ_MIN, hw_rev); + + if (hw_rev == MDSS_HW_MSM8996 || + hw_rev == MDSS_HW_MSM8937 || + hw_rev == MDSS_HW_MSM8953 || + hw_rev == MDSS_HW_MSM8998 || + hw_rev == MDSS_HW_SDM660 || + hw_rev == MDSS_HW_SDM630) { + data->ubwc_dec_version = UBWC_1_0; + data->ubwc_enc_version = UBWC_1_0; + } + + if (hw_rev == MDSS_HW_MSM8996 || + hw_rev == MDSS_HW_MSM8998) + data->highest_bank_bit = 2; + else + data->highest_bank_bit = 1; + + return data; +} + const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev) { struct msm_mdss *mdss; @@ -222,6 +266,13 @@ const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev) mdss = dev_get_drvdata(dev); + /* + * We could not do it at the probe time, since hw revision register was + * not readable. Fill data structure now for the MDP5 platforms. + */ + if (!mdss->mdss_data && mdss->is_mdp5) + mdss->mdss_data = msm_mdss_generate_mdp5_mdss_data(mdss); + return mdss->mdss_data; } @@ -636,6 +687,18 @@ static const struct msm_mdss_data sm8550_data = { .macrotile_mode = 1, .reg_bus_bw = 57000, }; + +static const struct msm_mdss_data x1e80100_data = { + .ubwc_enc_version = UBWC_4_0, + .ubwc_dec_version = UBWC_4_3, + .ubwc_swizzle = 6, + .ubwc_static = 1, + /* TODO: highest_bank_bit = 2 for LP_DDR4 */ + .highest_bank_bit = 3, + .macrotile_mode = 1, + /* TODO: Add reg_bus_bw with real value */ +}; + static const struct of_device_id mdss_dt_match[] = { { .compatible = "qcom,mdss" }, { .compatible = "qcom,msm8998-mdss", .data = &msm8998_data }, @@ -656,6 +719,7 @@ static const struct of_device_id mdss_dt_match[] = { { .compatible = "qcom,sm8450-mdss", .data = &sm8350_data }, { .compatible = "qcom,sm8550-mdss", .data = &sm8550_data }, { .compatible = "qcom,sm8650-mdss", .data = &sm8550_data}, + { .compatible = "qcom,x1e80100-mdss", .data = &x1e80100_data}, {} }; MODULE_DEVICE_TABLE(of, mdss_dt_match); |