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authorNur Hussein <hussein@unixcat.org>2023-04-06 04:25:59 +0800
committerThierry Reding <treding@nvidia.com>2023-04-06 14:02:33 +0200
commit2429b3c529da29d4277d519bd66d034842dcd70c (patch)
treed4d9285d158e44b0b0238ac30f1e3ceed206e5dd /drivers/gpu/drm/tegra/sor.c
parent71ec16f45ef8d10e20c58e85f7d3644e324d3c13 (diff)
drm/tegra: Avoid potential 32-bit integer overflow
In tegra_sor_compute_config(), the 32-bit value mode->clock is multiplied by 1000, and assigned to the u64 variable pclk. We can avoid a potential 32-bit integer overflow by casting mode->clock to u64 before we do the arithmetic and assignment. Signed-off-by: Nur Hussein <hussein@unixcat.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'drivers/gpu/drm/tegra/sor.c')
-rw-r--r--drivers/gpu/drm/tegra/sor.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/tegra/sor.c b/drivers/gpu/drm/tegra/sor.c
index cd25f409979c..8d910695775c 100644
--- a/drivers/gpu/drm/tegra/sor.c
+++ b/drivers/gpu/drm/tegra/sor.c
@@ -1153,7 +1153,7 @@ static int tegra_sor_compute_config(struct tegra_sor *sor,
struct drm_dp_link *link)
{
const u64 f = 100000, link_rate = link->rate * 1000;
- const u64 pclk = mode->clock * 1000;
+ const u64 pclk = (u64)mode->clock * 1000;
u64 input, output, watermark, num;
struct tegra_sor_params params;
u32 num_syms_per_line;