diff options
| author | Lucas De Marchi <lucas.demarchi@intel.com> | 2023-05-08 15:53:19 -0700 |
|---|---|---|
| committer | Rodrigo Vivi <rodrigo.vivi@intel.com> | 2023-12-19 18:33:49 -0500 |
| commit | ce8bf5bd059542431230eac216693a579dc09dba (patch) | |
| tree | b6841c93b343466920343f999046fb596aa50e30 /drivers/gpu/drm/xe/xe_gt_topology.c | |
| parent | 34f89ac8e66cd5121fb05c765acc3c67ddbef7a0 (diff) | |
drm/xe/mmio: Use struct xe_reg
Convert all the callers to deal with xe_mmio_*() using struct xe_reg
instead of plain u32. In a few places there was also a rename
s/reg/reg_val/ when dealing with the value returned so it doesn't get
mixed up with the register address.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://lore.kernel.org/r/20230508225322.2692066-2-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Diffstat (limited to 'drivers/gpu/drm/xe/xe_gt_topology.c')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_gt_topology.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/drivers/gpu/drm/xe/xe_gt_topology.c b/drivers/gpu/drm/xe/xe_gt_topology.c index 14cf135fd648..7c3e347e4d74 100644 --- a/drivers/gpu/drm/xe/xe_gt_topology.c +++ b/drivers/gpu/drm/xe/xe_gt_topology.c @@ -26,7 +26,7 @@ load_dss_mask(struct xe_gt *gt, xe_dss_mask_t mask, int numregs, ...) va_start(argp, numregs); for (i = 0; i < numregs; i++) - fuse_val[i] = xe_mmio_read32(gt, va_arg(argp, u32)); + fuse_val[i] = xe_mmio_read32(gt, va_arg(argp, struct xe_reg)); va_end(argp); bitmap_from_arr32(mask, fuse_val, numregs * 32); @@ -36,7 +36,7 @@ static void load_eu_mask(struct xe_gt *gt, xe_eu_mask_t mask) { struct xe_device *xe = gt_to_xe(gt); - u32 reg = xe_mmio_read32(gt, XELP_EU_ENABLE.reg); + u32 reg_val = xe_mmio_read32(gt, XELP_EU_ENABLE); u32 val = 0; int i; @@ -47,15 +47,15 @@ load_eu_mask(struct xe_gt *gt, xe_eu_mask_t mask) * of enable). */ if (GRAPHICS_VERx100(xe) < 1250) - reg = ~reg & XELP_EU_MASK; + reg_val = ~reg_val & XELP_EU_MASK; /* On PVC, one bit = one EU */ if (GRAPHICS_VERx100(xe) == 1260) { - val = reg; + val = reg_val; } else { /* All other platforms, one bit = 2 EU */ - for (i = 0; i < fls(reg); i++) - if (reg & BIT(i)) + for (i = 0; i < fls(reg_val); i++) + if (reg_val & BIT(i)) val |= 0x3 << 2 * i; } @@ -95,10 +95,10 @@ xe_gt_topology_init(struct xe_gt *gt) load_dss_mask(gt, gt->fuse_topo.g_dss_mask, num_geometry_regs, - XELP_GT_GEOMETRY_DSS_ENABLE.reg); + XELP_GT_GEOMETRY_DSS_ENABLE); load_dss_mask(gt, gt->fuse_topo.c_dss_mask, num_compute_regs, - XEHP_GT_COMPUTE_DSS_ENABLE.reg, - XEHPC_GT_COMPUTE_DSS_ENABLE_EXT.reg); + XEHP_GT_COMPUTE_DSS_ENABLE, + XEHPC_GT_COMPUTE_DSS_ENABLE_EXT); load_eu_mask(gt, gt->fuse_topo.eu_mask_per_dss); xe_gt_topology_dump(gt, &p); |