diff options
| author | Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> | 2024-03-26 15:44:56 -0700 |
|---|---|---|
| committer | Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> | 2024-03-28 13:26:31 -0700 |
| commit | d62753a57de2547c72819cc82b76731f04563433 (patch) | |
| tree | e78b2994a3eb1c22604e709148cd8c8855e2bdf4 /drivers/gpu/drm/xe/xe_wa_oob.rules | |
| parent | aed2c1d70aa008b83c806d33d55b1f782f4fff41 (diff) | |
drm/xe/gsc: Implement WA 14018094691
The WA states that we need to keep the primary GT powered up during GSC
load to allow the GSC FW to access its registers. We also need to make
sure that one of the registers is locked before starting the load.
v2: fix location of register def (Matt)
Bspec: 55928
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240326224456.518548-1-daniele.ceraolospurio@intel.com
Diffstat (limited to 'drivers/gpu/drm/xe/xe_wa_oob.rules')
| -rw-r--r-- | drivers/gpu/drm/xe/xe_wa_oob.rules | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules index 48cdba1cbf95..68600cdead84 100644 --- a/drivers/gpu/drm/xe/xe_wa_oob.rules +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules @@ -19,3 +19,4 @@ GRAPHICS_VERSION_RANGE(1270, 1274) MEDIA_VERSION(1300) PLATFORM(DG2) +14018094691 GRAPHICS_VERSION(2004) |