diff options
| author | Sakari Ailus <sakari.ailus@linux.intel.com> | 2020-08-07 11:00:59 +0200 |
|---|---|---|
| committer | Mauro Carvalho Chehab <mchehab+huawei@kernel.org> | 2020-12-07 15:57:07 +0100 |
| commit | c4c0b222720d413cc866275a0200019eb3c58f33 (patch) | |
| tree | 9b3469ff28633d2ef2fcdd1df09ba8794e18ba51 /drivers/media/i2c/ccs/ccs-core.c | |
| parent | 4e1e8d240dff96bd8dd2c00c5fcd7f04088ace3c (diff) | |
media: ccs-pll: Support two cycles per pixel on OP domain
The l parameter defines the number of clock cycles to process a single
pixel per OP lane. It is calculated based on a new register
op_bits_per_lane.
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Diffstat (limited to 'drivers/media/i2c/ccs/ccs-core.c')
| -rw-r--r-- | drivers/media/i2c/ccs/ccs-core.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c index 6c2b8a4259fd..d39da0f31d90 100644 --- a/drivers/media/i2c/ccs/ccs-core.c +++ b/drivers/media/i2c/ccs/ccs-core.c @@ -3222,6 +3222,7 @@ static int ccs_probe(struct i2c_client *client) if (CCS_LIM(sensor, CLOCK_TREE_PLL_CAPABILITY) & CCS_CLOCK_TREE_PLL_CAPABILITY_EXT_DIVIDER) sensor->pll.flags |= CCS_PLL_FLAG_EXT_IP_PLL_DIVIDER; + sensor->pll.op_bits_per_lane = CCS_LIM(sensor, OP_BITS_PER_LANE); sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk; sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN); |