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authorBen Chuang <ben.chuang@genesyslogic.com.tw>2020-11-25 19:01:45 +0800
committerUlf Hansson <ulf.hansson@linaro.org>2020-12-04 12:30:56 +0100
commit98991b1853ab699451afcc2223c5f1173a0aade9 (patch)
tree1bcc5132bfbcffd1bbeb341b704fb22ef42dc255 /drivers/mmc
parentcb80a7e917483150ca592bc7e15163341e7d4150 (diff)
mmc: sdhci-pci-gli: Disable slow mode in HS400 mode for GL9763E
The GL9763E uses 150Mhz (slow mode) by default in HS400 mode. In order to make HS400 mode run at 200Mhz, the slow mode needs to be turned off. Signed-off-by: Ben Chuang <ben.chuang@genesyslogic.com.tw> Link: https://lore.kernel.org/r/20201125110145.2824-1-benchuanggli@gmail.com Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/host/sdhci-pci-gli.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/mmc/host/sdhci-pci-gli.c b/drivers/mmc/host/sdhci-pci-gli.c
index f10bdfbfce36..b85edd62e7f0 100644
--- a/drivers/mmc/host/sdhci-pci-gli.c
+++ b/drivers/mmc/host/sdhci-pci-gli.c
@@ -87,6 +87,9 @@
#define PCIE_GLI_9763E_SCR 0x8E0
#define GLI_9763E_SCR_AXI_REQ BIT(9)
+#define PCIE_GLI_9763E_MMC_CTRL 0x960
+#define GLI_9763E_HS400_SLOW BIT(3)
+
#define SDHCI_GLI_9763E_CQE_BASE_ADDR 0x200
#define GLI_9763E_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \
SDHCI_TRNS_BLK_CNT_EN | \
@@ -784,6 +787,10 @@ static void gli_set_gl9763e(struct sdhci_pci_slot *slot)
value |= GLI_9763E_SCR_AXI_REQ;
pci_write_config_dword(pdev, PCIE_GLI_9763E_SCR, value);
+ pci_read_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, &value);
+ value &= ~GLI_9763E_HS400_SLOW;
+ pci_write_config_dword(pdev, PCIE_GLI_9763E_MMC_CTRL, value);
+
pci_read_config_dword(pdev, PCIE_GLI_9763E_VHS, &value);
value &= ~GLI_9763E_VHS_REV;
value |= FIELD_PREP(GLI_9763E_VHS_REV, GLI_9763E_VHS_REV_R);