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authorRussell King (Oracle) <rmk+kernel@armlinux.org.uk>2024-10-04 11:21:37 +0100
committerDavid S. Miller <davem@davemloft.net>2024-10-09 12:13:11 +0100
commit5ba5619303902ff796c1568cf3b8ad65de288bb5 (patch)
treebeaf15c98e57452e16fa1a332439160c857dac3f /drivers/net/pcs
parentacb5fb5a42cff09eb073582ef7e15273fe318a25 (diff)
net: pcs: xpcs: correctly place DW_VR_MII_DIG_CTRL1_2G5_EN
Place DW_VR_MII_DIG_CTRL1_2G5_EN with the other DW_VR_MII_DIG_CTRL1 definitions rather than in the middle of a register list. Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'drivers/net/pcs')
-rw-r--r--drivers/net/pcs/pcs-xpcs.h3
1 files changed, 1 insertions, 2 deletions
diff --git a/drivers/net/pcs/pcs-xpcs.h b/drivers/net/pcs/pcs-xpcs.h
index b80b956ec286..9a22eed4404d 100644
--- a/drivers/net/pcs/pcs-xpcs.h
+++ b/drivers/net/pcs/pcs-xpcs.h
@@ -60,8 +60,6 @@
#define DW_VR_MII_DIG_CTRL1 0x8000
#define DW_VR_MII_AN_CTRL 0x8001
#define DW_VR_MII_AN_INTR_STS 0x8002
-/* Enable 2.5G Mode */
-#define DW_VR_MII_DIG_CTRL1_2G5_EN BIT(2)
/* EEE Mode Control Register */
#define DW_VR_MII_EEE_MCTRL0 0x8006
#define DW_VR_MII_EEE_MCTRL1 0x800b
@@ -69,6 +67,7 @@
/* VR_MII_DIG_CTRL1 */
#define DW_VR_MII_DIG_CTRL1_MAC_AUTO_SW BIT(9)
+#define DW_VR_MII_DIG_CTRL1_2G5_EN BIT(2)
#define DW_VR_MII_DIG_CTRL1_PHY_MODE_CTRL BIT(0)
/* VR_MII_DIG_CTRL2 */