diff options
| author | Frank Li <Frank.Li@nxp.com> | 2024-07-29 16:18:14 -0400 |
|---|---|---|
| committer | Krzysztof Wilczyński <kwilczynski@kernel.org> | 2024-09-09 14:08:22 +0000 |
| commit | 52ac41b5cd60e5182a5cd33d1ad44622c3d1cc05 (patch) | |
| tree | a6da1801784e4415f7f2f3eb37fbf1ee14481a43 /drivers/pci/controller/dwc/pci-imx6.c | |
| parent | 5223084d1383a9b5a72989e173fb8b566766f49f (diff) | |
PCI: imx6: Improve comment for workaround ERR010728
Improve comment about workaround ERR010728 by using official errata
document content, see:
https://www.nxp.com/webapp/Download?colCode=IMX7DS_2N09P
Link: https://lore.kernel.org/linux-pci/20240729-pci2_upstream-v8-7-b68ee5ef2b4d@nxp.com
Signed-off-by: Frank Li <Frank.Li@nxp.com>
[kwilczynski: commit log]
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Diffstat (limited to 'drivers/pci/controller/dwc/pci-imx6.c')
| -rw-r--r-- | drivers/pci/controller/dwc/pci-imx6.c | 23 |
1 files changed, 20 insertions, 3 deletions
diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index a63975bd21ed..0b165b6aa757 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -711,9 +711,26 @@ static int imx7d_pcie_core_reset(struct imx_pcie *imx_pcie, bool assert) return 0; /* - * Workaround for ERR010728, failure of PCI-e PLL VCO to - * oscillate, especially when cold. This turns off "Duty-cycle - * Corrector" and other mysterious undocumented things. + * Workaround for ERR010728 (IMX7DS_2N09P, Rev. 1.1, 4/2023): + * + * PCIe: PLL may fail to lock under corner conditions. + * + * Initial VCO oscillation may fail under corner conditions such as + * cold temperature which will cause the PCIe PLL fail to lock in the + * initialization phase. + * + * The Duty-cycle Corrector calibration must be disabled. + * + * 1. De-assert the G_RST signal by clearing + * SRC_PCIEPHY_RCR[PCIEPHY_G_RST]. + * 2. De-assert DCC_FB_EN by writing data “0x29” to the register + * address 0x306d0014 (PCIE_PHY_CMN_REG4). + * 3. Assert RX_EQS, RX_EQ_SEL by writing data “0x48” to the register + * address 0x306d0090 (PCIE_PHY_CMN_REG24). + * 4. Assert ATT_MODE by writing data “0xbc” to the register + * address 0x306d0098 (PCIE_PHY_CMN_REG26). + * 5. De-assert the CMN_RST signal by clearing register bit + * SRC_PCIEPHY_RCR[PCIEPHY_BTN] */ if (likely(imx_pcie->phy_base)) { |