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author | Serge Semin <Sergey.Semin@baikalelectronics.ru> | 2023-01-13 20:14:07 +0300 |
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committer | Bjorn Helgaas <bhelgaas@google.com> | 2023-02-22 13:46:14 -0600 |
commit | 6c784e21b3da735bd2c3dba73acf9b2c033564fa (patch) | |
tree | b4042fcfbf753d0ce6e958eee9d2719457029426 /drivers/pci/controller/dwc/pcie-designware.h | |
parent | 3bc0f149405e07c7e59985a24ce96db83973f8d7 (diff) |
PCI: dwc: Restrict only coherent DMA mask for MSI address allocation
The MSI target address must be in the lowest 4GB memory to support PCI
peripherals without 64-bit MSI support. Since the allocation is done from
DMA coherent memory, set only the coherent DMA mask, leaving the streaming
DMA mask alone.
Thus streaming DMA operations will work with no artificial limitations. It
will be specifically useful for the eDMA-capable controllers so the
corresponding DMA engine clients would map the DMA buffers with no need for
SWIOTLB for buffers allocated above 4GB.
Add a brief comment about the reason allocating the MSI target address
below 4GB.
Link: https://lore.kernel.org/r/20230113171409.30470-26-Sergey.Semin@baikalelectronics.ru
Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Diffstat (limited to 'drivers/pci/controller/dwc/pcie-designware.h')
0 files changed, 0 insertions, 0 deletions