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| author | qizhong cheng <qizhong.cheng@mediatek.com> | 2021-12-27 21:31:10 +0800 |
|---|---|---|
| committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2022-01-07 10:21:51 +0000 |
| commit | 65ace9a85fa7f88aec4d9d842061108161fa47bc (patch) | |
| tree | 75b76b6d1bbfa80991bd0dbff0c7ca13d8d13afd /drivers/pci/controller/dwc | |
| parent | fa55b7dcdc43c1aa1ba12bca9d2dd4318c2a0dbf (diff) | |
PCI: mediatek: Assert PERST# for 100ms for power and clock to stabilize
Described in PCIe CEM specification sections 2.2 (PERST# Signal) and
2.2.1 (Initial Power-Up (G3 to S0)). The deassertion of PERST# should
be delayed 100ms (TPVPERL) for the power and clock to become stable.
Link: https://lore.kernel.org/r/20211227133110.14500-1-qizhong.cheng@mediatek.com
Signed-off-by: qizhong cheng <qizhong.cheng@mediatek.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Pali Rohár <pali@kernel.org>
Diffstat (limited to 'drivers/pci/controller/dwc')
0 files changed, 0 insertions, 0 deletions