diff options
| author | Jianjun Wang <jianjun.wang@mediatek.com> | 2021-10-15 14:36:02 +0800 |
|---|---|---|
| committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2021-11-29 12:08:17 +0000 |
| commit | ab344fd43f2958726d17d651c0cb692c67dca382 (patch) | |
| tree | c54d5b45840c1ac5b2c298070ef27ce1bb79c60c /drivers/pci/controller/dwc | |
| parent | fa55b7dcdc43c1aa1ba12bca9d2dd4318c2a0dbf (diff) | |
PCI: mediatek-gen3: Disable DVFSRC voltage request
When the DVFSRC (dynamic voltage and frequency scaling resource collector)
feature is not implemented, the PCIe hardware will assert a voltage request
signal when exit from the L1 PM Substates to request a specific Vcore
voltage, but cannot receive the voltage ready signal, which will cause
the link to fail to exit the L1 PM Substates.
Disable DVFSRC voltage request by default, we need to find a common way to
enable it in the future.
Link: https://lore.kernel.org/r/20211015063602.29058-1-jianjun.wang@mediatek.com
Fixes: d3bf75b579b9 ("PCI: mediatek-gen3: Add MediaTek Gen3 driver for MT8192")
Tested-by: Qizhong Cheng <qizhong.cheng@mediatek.com>
Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Tzung-Bi Shih <tzungbi@google.com>
Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com>
Diffstat (limited to 'drivers/pci/controller/dwc')
0 files changed, 0 insertions, 0 deletions