diff options
| author | Claudiu.Beznea@microchip.com <Claudiu.Beznea@microchip.com> | 2020-01-21 10:03:37 +0000 |
|---|---|---|
| committer | Sebastian Reichel <sebastian.reichel@collabora.com> | 2020-03-08 19:38:04 +0100 |
| commit | fcd0532fac2ac82cec6d7b43298c8ecfc93e1049 (patch) | |
| tree | 98646730ecba12c82daddfa7eb40b31159c5619f /drivers/power | |
| parent | 68a84a3e68a2238036dd6c7dbb677fe62a92d70a (diff) | |
power: reset: at91-reset: make at91sam9g45_restart() generic
Make at91sam9g45_restart() generic.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Diffstat (limited to 'drivers/power')
| -rw-r--r-- | drivers/power/reset/at91-reset.c | 21 |
1 files changed, 6 insertions, 15 deletions
diff --git a/drivers/power/reset/at91-reset.c b/drivers/power/reset/at91-reset.c index 4e1961334e4d..61433060d784 100644 --- a/drivers/power/reset/at91-reset.c +++ b/drivers/power/reset/at91-reset.c @@ -105,32 +105,23 @@ static int at91sam9g45_restart(struct notifier_block *this, unsigned long mode, struct at91_reset *reset = container_of(this, struct at91_reset, nb); asm volatile( - /* - * Test wether we have a second RAM controller to care - * about. - * - * First, test that we can dereference the virtual address. - */ - "cmp %1, #0\n\t" - "beq 1f\n\t" - - /* Then, test that the RAM controller is enabled */ - "ldr r4, [%1]\n\t" - "cmp r4, #0\n\t" - /* Align to cache lines */ ".balign 32\n\t" /* Disable SDRAM0 accesses */ - "1: str %3, [%0, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t" + " tst %0, #0\n\t" + " beq 1f\n\t" + " str %3, [%0, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t" /* Power down SDRAM0 */ " str %4, [%0, %6]\n\t" /* Disable SDRAM1 accesses */ + "1: tst %1, #0\n\t" + " beq 2f\n\t" " strne %3, [%1, #" __stringify(AT91_DDRSDRC_RTR) "]\n\t" /* Power down SDRAM1 */ " strne %4, [%1, %6]\n\t" /* Reset CPU */ - " str %5, [%2, #" __stringify(AT91_RSTC_CR) "]\n\t" + "2: str %5, [%2, #" __stringify(AT91_RSTC_CR) "]\n\t" " b .\n\t" : |