diff options
| author | Peter Griffin <peter.griffin@linaro.org> | 2024-10-31 15:00:30 +0000 |
|---|---|---|
| committer | Martin K. Petersen <martin.petersen@oracle.com> | 2024-11-02 21:13:01 -0400 |
| commit | 36adb55631d0199b516a8b573fa886494d0e44a6 (patch) | |
| tree | 13f1751dbe07e73a0d584e9e0660209f7e5e7e31 /drivers/ufs | |
| parent | ef8bfb00e9f106434a43f42559a6bc42f850e2d0 (diff) | |
scsi: ufs: exynos: Set ACG to be controlled by UFS_ACG_DISABLE
HCI_IOP_ACG_DISABLE is an undocumented register in the TRM but the
downstream driver sets this register so we follow suit here.
The register is already 0 presumed to be set by the bootloader as the
comment downstream implies the reset state is 1. So whilst this is a nop
currently, it should protect us in case the bootloader behaviour ever
changes.
Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Link: https://lore.kernel.org/r/20241031150033.3440894-12-peter.griffin@linaro.org
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
Diffstat (limited to 'drivers/ufs')
| -rw-r--r-- | drivers/ufs/host/ufs-exynos.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/drivers/ufs/host/ufs-exynos.c b/drivers/ufs/host/ufs-exynos.c index 78307440107f..5078210b2a5c 100644 --- a/drivers/ufs/host/ufs-exynos.c +++ b/drivers/ufs/host/ufs-exynos.c @@ -76,6 +76,10 @@ #define CLK_CTRL_EN_MASK (REFCLK_CTRL_EN |\ UNIPRO_PCLK_CTRL_EN |\ UNIPRO_MCLK_CTRL_EN) + +#define HCI_IOP_ACG_DISABLE 0x100 +#define HCI_IOP_ACG_DISABLE_EN BIT(0) + /* Device fatal error */ #define DFES_ERR_EN BIT(31) #define DFES_DEF_L2_ERRS (UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF |\ @@ -215,10 +219,15 @@ static int exynos_ufs_shareability(struct exynos_ufs *ufs) static int gs101_ufs_drv_init(struct exynos_ufs *ufs) { struct ufs_hba *hba = ufs->hba; + u32 reg; /* Enable WriteBooster */ hba->caps |= UFSHCD_CAP_WB_EN; + /* set ACG to be controlled by UFS_ACG_DISABLE */ + reg = hci_readl(ufs, HCI_IOP_ACG_DISABLE); + hci_writel(ufs, reg & (~HCI_IOP_ACG_DISABLE_EN), HCI_IOP_ACG_DISABLE); + return exynos_ufs_shareability(ufs); } |