diff options
| author | Mario Limonciello <mario.limonciello@amd.com> | 2023-04-21 07:06:22 -0500 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2023-05-08 15:42:24 +0200 |
| commit | a855724dc08b8cb0c13ab1e065a4922f1e5a7552 (patch) | |
| tree | 66b1effb9a4df391bb529fb59e19c847c411188e /drivers | |
| parent | 968ab9261627fa305307e3935ca1a32fcddd36cb (diff) | |
pinctrl: amd: Fix mistake in handling clearing pins at startup
commit 4e5a04be88fe ("pinctrl: amd: disable and mask interrupts on probe")
had a mistake in loop iteration 63 that it would clear offset 0xFC instead
of 0x100. Offset 0xFC is actually `WAKE_INT_MASTER_REG`. This was
clearing bits 13 and 15 from the register which significantly changed the
expected handling for some platforms for GPIO0.
Cc: stable@vger.kernel.org
Link: https://bugzilla.kernel.org/show_bug.cgi?id=217315
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Link: https://lore.kernel.org/r/20230421120625.3366-3-mario.limonciello@amd.com
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/pinctrl/pinctrl-amd.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/pinctrl/pinctrl-amd.c b/drivers/pinctrl/pinctrl-amd.c index 94cab8aa2bcc..840f9b885ecf 100644 --- a/drivers/pinctrl/pinctrl-amd.c +++ b/drivers/pinctrl/pinctrl-amd.c @@ -897,9 +897,9 @@ static void amd_gpio_irq_init(struct amd_gpio *gpio_dev) raw_spin_lock_irqsave(&gpio_dev->lock, flags); - pin_reg = readl(gpio_dev->base + i * 4); + pin_reg = readl(gpio_dev->base + pin * 4); pin_reg &= ~mask; - writel(pin_reg, gpio_dev->base + i * 4); + writel(pin_reg, gpio_dev->base + pin * 4); raw_spin_unlock_irqrestore(&gpio_dev->lock, flags); } |