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authorKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>2021-06-03 21:43:54 +0200
committerKrzysztof Kozlowski <krzysztof.kozlowski@canonical.com>2021-06-03 21:43:54 +0200
commiteeafcdea46936d84e2016e7d965f0b79e75ffd9e (patch)
tree463f5ac4f1ca3351f63a4b99a9420606b8403487 /include/soc
parent6efb943b8616ec53a5e444193dccf1af9ad627b5 (diff)
parentb4f74b59b99fab61ab97fc0e506f349579d8fefc (diff)
Merge tag 'tegra-for-5.14-memory' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into for-v5.14/tegra-mc
memory: tegra: Changes for v5.14-rc1 This stable tag contains Dmitry's power domain work, including all the necessary dependencies from the regulator, clock and ARM SoC trees. Further work depends on memory controller changes here.
Diffstat (limited to 'include/soc')
-rw-r--r--include/soc/tegra/common.h31
-rw-r--r--include/soc/tegra/fuse.h20
2 files changed, 48 insertions, 3 deletions
diff --git a/include/soc/tegra/common.h b/include/soc/tegra/common.h
index 98027a76ce3d..af41ad80ec21 100644
--- a/include/soc/tegra/common.h
+++ b/include/soc/tegra/common.h
@@ -6,6 +6,37 @@
#ifndef __SOC_TEGRA_COMMON_H__
#define __SOC_TEGRA_COMMON_H__
+#include <linux/errno.h>
+#include <linux/types.h>
+
+struct device;
+
+/**
+ * Tegra SoC core device OPP table configuration
+ *
+ * @init_state: pre-initialize OPP state of a device
+ */
+struct tegra_core_opp_params {
+ bool init_state;
+};
+
+#ifdef CONFIG_ARCH_TEGRA
bool soc_is_tegra(void);
+int devm_tegra_core_dev_init_opp_table(struct device *dev,
+ struct tegra_core_opp_params *params);
+#else
+static inline bool soc_is_tegra(void)
+{
+ return false;
+}
+
+static inline int
+devm_tegra_core_dev_init_opp_table(struct device *dev,
+ struct tegra_core_opp_params *params)
+{
+ return -ENODEV;
+}
+#endif
+
#endif /* __SOC_TEGRA_COMMON_H__ */
diff --git a/include/soc/tegra/fuse.h b/include/soc/tegra/fuse.h
index 78cbc787a4dc..990701f788bc 100644
--- a/include/soc/tegra/fuse.h
+++ b/include/soc/tegra/fuse.h
@@ -52,14 +52,28 @@ struct tegra_sku_info {
enum tegra_revision revision;
};
+#ifdef CONFIG_ARCH_TEGRA
+extern struct tegra_sku_info tegra_sku_info;
u32 tegra_read_straps(void);
u32 tegra_read_ram_code(void);
int tegra_fuse_readl(unsigned long offset, u32 *value);
-
-#ifdef CONFIG_ARCH_TEGRA
-extern struct tegra_sku_info tegra_sku_info;
#else
static struct tegra_sku_info tegra_sku_info __maybe_unused;
+
+static inline u32 tegra_read_straps(void)
+{
+ return 0;
+}
+
+static inline u32 tegra_read_ram_code(void)
+{
+ return 0;
+}
+
+static inline int tegra_fuse_readl(unsigned long offset, u32 *value)
+{
+ return -ENODEV;
+}
#endif
struct device *tegra_soc_device_register(void);