diff options
| author | Kan Liang <kan.liang@linux.intel.com> | 2022-03-28 08:49:03 -0700 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2022-04-05 09:59:44 +0200 |
| commit | e590928de7547454469693da9bc7ffd562e54b7e (patch) | |
| tree | 6ca3d5e4bb1f46152e815b09f3501b7a38a4c45f /kernel | |
| parent | 4a263bf331c512849062805ef1b4ac40301a9829 (diff) | |
perf/x86/intel: Update the FRONTEND MSR mask on Sapphire Rapids
On Sapphire Rapids, the FRONTEND_RETIRED.MS_FLOWS event requires the
FRONTEND MSR value 0x8. However, the current FRONTEND MSR mask doesn't
support it.
Update intel_spr_extra_regs[] to support it.
Fixes: 61b985e3e775 ("perf/x86/intel: Add perf core PMU support for Sapphire Rapids")
Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/1648482543-14923-2-git-send-email-kan.liang@linux.intel.com
Diffstat (limited to 'kernel')
0 files changed, 0 insertions, 0 deletions