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authorMonk Liu <Monk.Liu@amd.com>2016-11-11 18:25:49 +0800
committerAlex Deucher <alexander.deucher@amd.com>2016-11-23 15:08:40 -0500
commit45682886bcd4a7d94a3281460c29a8a5c5438212 (patch)
tree5c13f4cffd83375c1278ab826d4970a58f732476 /lib/uuid.c
parent79abf1add6e6b8fa9951cfb2122c08defa57fbd1 (diff)
drm/amdgpu:impl vgt_flush for VI(V5)
when shadowing enabled, tesselation app will trigger vm fault because below three tesselation registers: VGT_TF_RING_SIZE__CI__VI, VGT_HS_OFFCHIP_PARAM__CI__VI, VGT_TF_MEMORY_BASE__CI__VI, need to be programed after vgt-flush. Tesselation picture vm fault disappeared after vgt-flush introduced. v2:implement vgt-flush for CI & SI. v3:move vgt flush inside of cntx_cntrl v4:count vgt flush in frame_size v5:squash in typo fix Signed-off-by: Monk Liu <Monk.Liu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Diffstat (limited to 'lib/uuid.c')
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