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authorMahesh Kumar <mahesh1.kumar@intel.com>2019-07-11 10:31:11 -0700
committerLucas De Marchi <lucas.demarchi@intel.com>2019-07-11 16:31:21 -0700
commit3fd53262f0dd81361efcb5ccba8312525ee6c645 (patch)
tree185cba553a2c29d76566ce47dec5545a15e42d37 /scripts/gen_compile_commands.py
parent30fcc338bc66f930dc7f692205474edb7ca6a607 (diff)
drm/i915/tgl: Add gmbus gpio pin to port mapping
Add default GPIO pin mapping for all ports. Tiger Lake has 3 combophy ports and 6 TC ports, gpio pin1-3 are mapped to combophy & pin9-14 are mapped to TC ports. Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com> Reviewed-by: José Roberto de Souza <jose.souza@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20190711173115.28296-18-lucas.demarchi@intel.com
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