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| author | José Roberto de Souza <jose.souza@intel.com> | 2019-07-11 10:31:15 -0700 |
|---|---|---|
| committer | Lucas De Marchi <lucas.demarchi@intel.com> | 2019-07-11 16:31:27 -0700 |
| commit | a1c5f1510b3f39d57a6eaa9d75c70e5beaa952ff (patch) | |
| tree | 0519e059df7260bb9ddab4ef3b72beb87577c578 /scripts/gen_compile_commands.py | |
| parent | 36ca5335f202bd54faf38b37fed1b99078e1839e (diff) | |
drm/i915/tgl: Update DPLL clock reference register
This register definition changed from ICL and has now another meaning.
Use the right bits on TGL.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190711173115.28296-22-lucas.demarchi@intel.com
Diffstat (limited to 'scripts/gen_compile_commands.py')
0 files changed, 0 insertions, 0 deletions