Merge tag 'sound-4.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound

Pull sound updates from Takashi Iwai:
 "This time was again a relatively calm development cycle; most of
  updates are about drivers, and no radical changes are seen in any core
  code.  Here are some highlights:

  ALSA core:
   - Continued hardening of ALSA hrtimer
   - A few leak fixes in timer interface
   - Fix poll error handling in PCM and compress
   - Add error propagation in compress API
   - Removal of dead rtctimer driver

  HD-audio:
   - Native ELD notify support for i915 HDMI
   - Realtek ALC234 & co support
   - Code refactoring to standardize chmap support
   - Continued development for SKL HDMI core support

  Firewire:
   - Apply delayed card registration to all drivers
   - Improved / stabilized the handling of PCM stream start / stop
   - Add tracepoints to dump a part of isochronous packet data
   - Fixed incoming/outgoing packet parameter usages
   - Add support for M-Audio profire series

  USB-audio:
   - Fixes for UAC2 clock source
   - SS+ support
   - Workaround for oft-seen repeated sample rate read errors

  ASoC:
   - Further slow progress on the topology code
   - Substantial updates and improvements for the da7219, es8328,
     fsl-ssi, Intel and rcar drivers.
   - Compress error handling in WM ADSP driver"

* tag 'sound-4.7-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound: (177 commits)
  ALSA: firewire-lib: change a member of event structure to suppress sparse wanings to bool type
  sound: oss: Use setup_timer and mod_timer.
  ASoC: hdac_hdmi: Remove the unused 'timeout' variable
  ASoC: fsl_ssi: Fix channel slipping on capture (or playback) restart in full duplex.
  ASoC: fsl_ssi: Fix channel slipping in Playback at startup
  ASoC: fsl_ssi: Fix samples being dropped at Playback startup
  ASoC: fsl_ssi: Save a dev reference for dev_err() purpose.
  ASoC: fsl_ssi: The IPG/5 limitation concerns the bitclk, not the sysclk.
  ASoC: fsl_ssi: Real hardware channels max number is 32
  ASoC: pcm5102a: Add support for PCM5102A codec
  ASoC: hdac_hdmi: add link management
  ASoC: Intel: Skylake: add link management
  ALSA: hdac: add link pm and ref counting
  ALSA: au88x0: Fix zero clear of stream->resources
  ASoC: rt298: Add DMI match for Broxton-P reference platform
  ASoC: rt298: fix null deref on acpi driver data
  ASoC: dapm: deprecate MICBIAS widget type
  ALSA: firewire-lib: drop skip argument from helper functions to queue a packet
  ALSA: firewire-lib: add context information to tracepoints
  ALSA: firewire-lib: permit to flush queued packets only in process context for better PCM period granularity
  ...

1 files changed, 16 insertions, 16 deletions

diff --git a/sound/soc/codecs/da7218.c b/sound/soc/codecs/da7218.c
index 93575f251866..99ce23e113bf 100644
--- a/sound/soc/codecs/da7218.c
+++ b/sound/soc/codecs/da7218.c
@@ -1868,27 +1868,27 @@ static int da7218_set_dai_pll(struct snd_soc_dai *codec_dai, int pll_id,
 
 	/* Verify 32KHz, 2MHz - 54MHz MCLK provided, and set input divider */
 	if (da7218->mclk_rate == 32768) {
-		indiv_bits = DA7218_PLL_INDIV_2_5_MHZ;
-		indiv = DA7218_PLL_INDIV_2_10_MHZ_VAL;
+		indiv_bits = DA7218_PLL_INDIV_9_TO_18_MHZ;
+		indiv = DA7218_PLL_INDIV_9_TO_18_MHZ_VAL;
 	} else if (da7218->mclk_rate < 2000000) {
 		dev_err(codec->dev, "PLL input clock %d below valid range\n",
 			da7218->mclk_rate);
 		return -EINVAL;
-	} else if (da7218->mclk_rate <= 5000000) {
-		indiv_bits = DA7218_PLL_INDIV_2_5_MHZ;
-		indiv = DA7218_PLL_INDIV_2_10_MHZ_VAL;
-	} else if (da7218->mclk_rate <= 10000000) {
-		indiv_bits = DA7218_PLL_INDIV_5_10_MHZ;
-		indiv = DA7218_PLL_INDIV_2_10_MHZ_VAL;
-	} else if (da7218->mclk_rate <= 20000000) {
-		indiv_bits = DA7218_PLL_INDIV_10_20_MHZ;
-		indiv = DA7218_PLL_INDIV_10_20_MHZ_VAL;
-	} else if (da7218->mclk_rate <= 40000000) {
-		indiv_bits = DA7218_PLL_INDIV_20_40_MHZ;
-		indiv = DA7218_PLL_INDIV_20_40_MHZ_VAL;
+	} else if (da7218->mclk_rate <= 4500000) {
+		indiv_bits = DA7218_PLL_INDIV_2_TO_4_5_MHZ;
+		indiv = DA7218_PLL_INDIV_2_TO_4_5_MHZ_VAL;
+	} else if (da7218->mclk_rate <= 9000000) {
+		indiv_bits = DA7218_PLL_INDIV_4_5_TO_9_MHZ;
+		indiv = DA7218_PLL_INDIV_4_5_TO_9_MHZ_VAL;
+	} else if (da7218->mclk_rate <= 18000000) {
+		indiv_bits = DA7218_PLL_INDIV_9_TO_18_MHZ;
+		indiv = DA7218_PLL_INDIV_9_TO_18_MHZ_VAL;
+	} else if (da7218->mclk_rate <= 36000000) {
+		indiv_bits = DA7218_PLL_INDIV_18_TO_36_MHZ;
+		indiv = DA7218_PLL_INDIV_18_TO_36_MHZ_VAL;
 	} else if (da7218->mclk_rate <= 54000000) {
-		indiv_bits = DA7218_PLL_INDIV_40_54_MHZ;
-		indiv = DA7218_PLL_INDIV_40_54_MHZ_VAL;
+		indiv_bits = DA7218_PLL_INDIV_36_TO_54_MHZ;
+		indiv = DA7218_PLL_INDIV_36_TO_54_MHZ_VAL;
 	} else {
 		dev_err(codec->dev, "PLL input clock %d above valid range\n",
 			da7218->mclk_rate);