diff options
| author | John Hsu <KCHSU0@nuvoton.com> | 2017-11-07 15:23:17 +0800 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2017-11-07 11:28:35 +0100 |
| commit | e4d0db60e8d25cc62b9b7e32c18e7f6acc136055 (patch) | |
| tree | fd6a4353f75dd38ed4f839852ae655d2d5bbb4e3 /sound/soc/codecs/nau8540.h | |
| parent | 2bd6bf03f4c1c59381d62c61d03f6cc3fe71f66e (diff) | |
ASoC: nau8540: reset state machine for channel phase sync
The four channel ADCs in NAU85L40 have difference control registers,
it is hard to synchronous these four channels without correct sequence.
The phase difference will not be a constant and not to conjecture easily.
It may be 2.55 degree, or more ,or less.
Intended to prevent phase difference of channels, the solution as follows:
(1)Channel_Sync need to be enabled.
(2)Do soft reset without affecting register when recording done.
Signed-off-by: John Hsu <KCHSU0@nuvoton.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
Diffstat (limited to 'sound/soc/codecs/nau8540.h')
| -rw-r--r-- | sound/soc/codecs/nau8540.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/sound/soc/codecs/nau8540.h b/sound/soc/codecs/nau8540.h index 5db5b224944d..14339f9bb01a 100644 --- a/sound/soc/codecs/nau8540.h +++ b/sound/soc/codecs/nau8540.h @@ -165,6 +165,7 @@ #define NAU8540_TDM_TX_MASK 0xf /* ADC_SAMPLE_RATE (0x3A) */ +#define NAU8540_CH_SYNC (0x1 << 14) #define NAU8540_ADC_OSR_MASK 0x3 #define NAU8540_ADC_OSR_256 0x3 #define NAU8540_ADC_OSR_128 0x2 |